| Andrew Isaacson | 4cbf2be | 2005-10-19 23:55:11 -0700 | [diff] [blame] | 1 | /* ********************************************************************* |
| 2 | * BCM1280/BCM1480 Board Support Package |
| 3 | * |
| 4 | * Memory Controller constants File: bcm1480_mc.h |
| 5 | * |
| 6 | * This module contains constants and macros useful for |
| 7 | * programming the memory controller. |
| 8 | * |
| 9 | * BCM1400 specification level: 1280-UM100-D1 (11/14/03 Review Copy) |
| 10 | * |
| 11 | ********************************************************************* |
| 12 | * |
| 13 | * Copyright 2000,2001,2002,2003 |
| 14 | * Broadcom Corporation. All rights reserved. |
| 15 | * |
| 16 | * This program is free software; you can redistribute it and/or |
| 17 | * modify it under the terms of the GNU General Public License as |
| 18 | * published by the Free Software Foundation; either version 2 of |
| 19 | * the License, or (at your option) any later version. |
| 20 | * |
| 21 | * This program is distributed in the hope that it will be useful, |
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 24 | * GNU General Public License for more details. |
| 25 | * |
| 26 | * You should have received a copy of the GNU General Public License |
| 27 | * along with this program; if not, write to the Free Software |
| 28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 29 | * MA 02111-1307 USA |
| 30 | ********************************************************************* */ |
| 31 | |
| 32 | |
| 33 | #ifndef _BCM1480_MC_H |
| 34 | #define _BCM1480_MC_H |
| 35 | |
| 36 | #include "sb1250_defs.h" |
| 37 | |
| 38 | /* |
| 39 | * Memory Channel Configuration Register (Table 81) |
| 40 | */ |
| 41 | |
| 42 | #define S_BCM1480_MC_INTLV0 0 |
| 43 | #define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV0) |
| 44 | #define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV0) |
| 45 | #define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV0,M_BCM1480_MC_INTLV0) |
| 46 | #define V_BCM1480_MC_INTLV0_DEFAULT V_BCM1480_MC_INTLV0(0) |
| 47 | |
| 48 | #define S_BCM1480_MC_INTLV1 8 |
| 49 | #define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV1) |
| 50 | #define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV1) |
| 51 | #define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV1,M_BCM1480_MC_INTLV1) |
| 52 | #define V_BCM1480_MC_INTLV1_DEFAULT V_BCM1480_MC_INTLV1(0) |
| 53 | |
| 54 | #define S_BCM1480_MC_INTLV2 16 |
| 55 | #define M_BCM1480_MC_INTLV2 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV2) |
| 56 | #define V_BCM1480_MC_INTLV2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV2) |
| 57 | #define G_BCM1480_MC_INTLV2(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV2,M_BCM1480_MC_INTLV2) |
| 58 | #define V_BCM1480_MC_INTLV2_DEFAULT V_BCM1480_MC_INTLV2(0) |
| 59 | |
| 60 | #define S_BCM1480_MC_CS_MODE 32 |
| 61 | #define M_BCM1480_MC_CS_MODE _SB_MAKEMASK(8,S_BCM1480_MC_CS_MODE) |
| 62 | #define V_BCM1480_MC_CS_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS_MODE) |
| 63 | #define G_BCM1480_MC_CS_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_CS_MODE,M_BCM1480_MC_CS_MODE) |
| 64 | #define V_BCM1480_MC_CS_MODE_DEFAULT V_BCM1480_MC_CS_MODE(0) |
| 65 | |
| 66 | #define V_BCM1480_MC_CONFIG_DEFAULT (V_BCM1480_MC_INTLV0_DEFAULT | \ |
| 67 | V_BCM1480_MC_INTLV1_DEFAULT | \ |
| 68 | V_BCM1480_MC_INTLV2_DEFAULT | \ |
| 69 | V_BCM1480_MC_CS_MODE_DEFAULT) |
| 70 | |
| 71 | #define K_BCM1480_MC_CS01_MODE 0x03 |
| 72 | #define K_BCM1480_MC_CS02_MODE 0x05 |
| 73 | #define K_BCM1480_MC_CS0123_MODE 0x0F |
| 74 | #define K_BCM1480_MC_CS0246_MODE 0x55 |
| 75 | #define K_BCM1480_MC_CS0145_MODE 0x33 |
| 76 | #define K_BCM1480_MC_CS0167_MODE 0xC3 |
| 77 | #define K_BCM1480_MC_CSFULL_MODE 0xFF |
| 78 | |
| 79 | /* |
| 80 | * Chip Select Start Address Register (Table 82) |
| 81 | */ |
| 82 | |
| 83 | #define S_BCM1480_MC_CS0_START 0 |
| 84 | #define M_BCM1480_MC_CS0_START _SB_MAKEMASK(12,S_BCM1480_MC_CS0_START) |
| 85 | #define V_BCM1480_MC_CS0_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS0_START) |
| 86 | #define G_BCM1480_MC_CS0_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS0_START,M_BCM1480_MC_CS0_START) |
| 87 | |
| 88 | #define S_BCM1480_MC_CS1_START 16 |
| 89 | #define M_BCM1480_MC_CS1_START _SB_MAKEMASK(12,S_BCM1480_MC_CS1_START) |
| 90 | #define V_BCM1480_MC_CS1_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS1_START) |
| 91 | #define G_BCM1480_MC_CS1_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS1_START,M_BCM1480_MC_CS1_START) |
| 92 | |
| 93 | #define S_BCM1480_MC_CS2_START 32 |
| 94 | #define M_BCM1480_MC_CS2_START _SB_MAKEMASK(12,S_BCM1480_MC_CS2_START) |
| 95 | #define V_BCM1480_MC_CS2_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS2_START) |
| 96 | #define G_BCM1480_MC_CS2_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS2_START,M_BCM1480_MC_CS2_START) |
| 97 | |
| 98 | #define S_BCM1480_MC_CS3_START 48 |
| 99 | #define M_BCM1480_MC_CS3_START _SB_MAKEMASK(12,S_BCM1480_MC_CS3_START) |
| 100 | #define V_BCM1480_MC_CS3_START(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS3_START) |
| 101 | #define G_BCM1480_MC_CS3_START(x) _SB_GETVALUE(x,S_BCM1480_MC_CS3_START,M_BCM1480_MC_CS3_START) |
| 102 | |
| 103 | /* |
| 104 | * Chip Select End Address Register (Table 83) |
| 105 | */ |
| 106 | |
| 107 | #define S_BCM1480_MC_CS0_END 0 |
| 108 | #define M_BCM1480_MC_CS0_END _SB_MAKEMASK(12,S_BCM1480_MC_CS0_END) |
| 109 | #define V_BCM1480_MC_CS0_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS0_END) |
| 110 | #define G_BCM1480_MC_CS0_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS0_END,M_BCM1480_MC_CS0_END) |
| 111 | |
| 112 | #define S_BCM1480_MC_CS1_END 16 |
| 113 | #define M_BCM1480_MC_CS1_END _SB_MAKEMASK(12,S_BCM1480_MC_CS1_END) |
| 114 | #define V_BCM1480_MC_CS1_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS1_END) |
| 115 | #define G_BCM1480_MC_CS1_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS1_END,M_BCM1480_MC_CS1_END) |
| 116 | |
| 117 | #define S_BCM1480_MC_CS2_END 32 |
| 118 | #define M_BCM1480_MC_CS2_END _SB_MAKEMASK(12,S_BCM1480_MC_CS2_END) |
| 119 | #define V_BCM1480_MC_CS2_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS2_END) |
| 120 | #define G_BCM1480_MC_CS2_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS2_END,M_BCM1480_MC_CS2_END) |
| 121 | |
| 122 | #define S_BCM1480_MC_CS3_END 48 |
| 123 | #define M_BCM1480_MC_CS3_END _SB_MAKEMASK(12,S_BCM1480_MC_CS3_END) |
| 124 | #define V_BCM1480_MC_CS3_END(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS3_END) |
| 125 | #define G_BCM1480_MC_CS3_END(x) _SB_GETVALUE(x,S_BCM1480_MC_CS3_END,M_BCM1480_MC_CS3_END) |
| 126 | |
| 127 | /* |
| 128 | * Row Address Bit Select Register 0 (Table 84) |
| 129 | */ |
| 130 | |
| 131 | #define S_BCM1480_MC_ROW00 0 |
| 132 | #define M_BCM1480_MC_ROW00 _SB_MAKEMASK(6,S_BCM1480_MC_ROW00) |
| 133 | #define V_BCM1480_MC_ROW00(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW00) |
| 134 | #define G_BCM1480_MC_ROW00(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW00,M_BCM1480_MC_ROW00) |
| 135 | |
| 136 | #define S_BCM1480_MC_ROW01 8 |
| 137 | #define M_BCM1480_MC_ROW01 _SB_MAKEMASK(6,S_BCM1480_MC_ROW01) |
| 138 | #define V_BCM1480_MC_ROW01(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW01) |
| 139 | #define G_BCM1480_MC_ROW01(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW01,M_BCM1480_MC_ROW01) |
| 140 | |
| 141 | #define S_BCM1480_MC_ROW02 16 |
| 142 | #define M_BCM1480_MC_ROW02 _SB_MAKEMASK(6,S_BCM1480_MC_ROW02) |
| 143 | #define V_BCM1480_MC_ROW02(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW02) |
| 144 | #define G_BCM1480_MC_ROW02(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW02,M_BCM1480_MC_ROW02) |
| 145 | |
| 146 | #define S_BCM1480_MC_ROW03 24 |
| 147 | #define M_BCM1480_MC_ROW03 _SB_MAKEMASK(6,S_BCM1480_MC_ROW03) |
| 148 | #define V_BCM1480_MC_ROW03(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW03) |
| 149 | #define G_BCM1480_MC_ROW03(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW03,M_BCM1480_MC_ROW03) |
| 150 | |
| 151 | #define S_BCM1480_MC_ROW04 32 |
| 152 | #define M_BCM1480_MC_ROW04 _SB_MAKEMASK(6,S_BCM1480_MC_ROW04) |
| 153 | #define V_BCM1480_MC_ROW04(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW04) |
| 154 | #define G_BCM1480_MC_ROW04(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW04,M_BCM1480_MC_ROW04) |
| 155 | |
| 156 | #define S_BCM1480_MC_ROW05 40 |
| 157 | #define M_BCM1480_MC_ROW05 _SB_MAKEMASK(6,S_BCM1480_MC_ROW05) |
| 158 | #define V_BCM1480_MC_ROW05(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW05) |
| 159 | #define G_BCM1480_MC_ROW05(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW05,M_BCM1480_MC_ROW05) |
| 160 | |
| 161 | #define S_BCM1480_MC_ROW06 48 |
| 162 | #define M_BCM1480_MC_ROW06 _SB_MAKEMASK(6,S_BCM1480_MC_ROW06) |
| 163 | #define V_BCM1480_MC_ROW06(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW06) |
| 164 | #define G_BCM1480_MC_ROW06(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW06,M_BCM1480_MC_ROW06) |
| 165 | |
| 166 | #define S_BCM1480_MC_ROW07 56 |
| 167 | #define M_BCM1480_MC_ROW07 _SB_MAKEMASK(6,S_BCM1480_MC_ROW07) |
| 168 | #define V_BCM1480_MC_ROW07(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW07) |
| 169 | #define G_BCM1480_MC_ROW07(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW07,M_BCM1480_MC_ROW07) |
| 170 | |
| 171 | /* |
| 172 | * Row Address Bit Select Register 1 (Table 85) |
| 173 | */ |
| 174 | |
| 175 | #define S_BCM1480_MC_ROW08 0 |
| 176 | #define M_BCM1480_MC_ROW08 _SB_MAKEMASK(6,S_BCM1480_MC_ROW08) |
| 177 | #define V_BCM1480_MC_ROW08(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW08) |
| 178 | #define G_BCM1480_MC_ROW08(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW08,M_BCM1480_MC_ROW08) |
| 179 | |
| 180 | #define S_BCM1480_MC_ROW09 8 |
| 181 | #define M_BCM1480_MC_ROW09 _SB_MAKEMASK(6,S_BCM1480_MC_ROW09) |
| 182 | #define V_BCM1480_MC_ROW09(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW09) |
| 183 | #define G_BCM1480_MC_ROW09(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW09,M_BCM1480_MC_ROW09) |
| 184 | |
| 185 | #define S_BCM1480_MC_ROW10 16 |
| 186 | #define M_BCM1480_MC_ROW10 _SB_MAKEMASK(6,S_BCM1480_MC_ROW10) |
| 187 | #define V_BCM1480_MC_ROW10(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW10) |
| 188 | #define G_BCM1480_MC_ROW10(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW10,M_BCM1480_MC_ROW10) |
| 189 | |
| 190 | #define S_BCM1480_MC_ROW11 24 |
| 191 | #define M_BCM1480_MC_ROW11 _SB_MAKEMASK(6,S_BCM1480_MC_ROW11) |
| 192 | #define V_BCM1480_MC_ROW11(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW11) |
| 193 | #define G_BCM1480_MC_ROW11(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW11,M_BCM1480_MC_ROW11) |
| 194 | |
| 195 | #define S_BCM1480_MC_ROW12 32 |
| 196 | #define M_BCM1480_MC_ROW12 _SB_MAKEMASK(6,S_BCM1480_MC_ROW12) |
| 197 | #define V_BCM1480_MC_ROW12(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW12) |
| 198 | #define G_BCM1480_MC_ROW12(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW12,M_BCM1480_MC_ROW12) |
| 199 | |
| 200 | #define S_BCM1480_MC_ROW13 40 |
| 201 | #define M_BCM1480_MC_ROW13 _SB_MAKEMASK(6,S_BCM1480_MC_ROW13) |
| 202 | #define V_BCM1480_MC_ROW13(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW13) |
| 203 | #define G_BCM1480_MC_ROW13(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW13,M_BCM1480_MC_ROW13) |
| 204 | |
| 205 | #define S_BCM1480_MC_ROW14 48 |
| 206 | #define M_BCM1480_MC_ROW14 _SB_MAKEMASK(6,S_BCM1480_MC_ROW14) |
| 207 | #define V_BCM1480_MC_ROW14(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ROW14) |
| 208 | #define G_BCM1480_MC_ROW14(x) _SB_GETVALUE(x,S_BCM1480_MC_ROW14,M_BCM1480_MC_ROW14) |
| 209 | |
| 210 | #define K_BCM1480_MC_ROWX_BIT_SPACING 8 |
| 211 | |
| 212 | /* |
| 213 | * Column Address Bit Select Register 0 (Table 86) |
| 214 | */ |
| 215 | |
| 216 | #define S_BCM1480_MC_COL00 0 |
| 217 | #define M_BCM1480_MC_COL00 _SB_MAKEMASK(6,S_BCM1480_MC_COL00) |
| 218 | #define V_BCM1480_MC_COL00(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL00) |
| 219 | #define G_BCM1480_MC_COL00(x) _SB_GETVALUE(x,S_BCM1480_MC_COL00,M_BCM1480_MC_COL00) |
| 220 | |
| 221 | #define S_BCM1480_MC_COL01 8 |
| 222 | #define M_BCM1480_MC_COL01 _SB_MAKEMASK(6,S_BCM1480_MC_COL01) |
| 223 | #define V_BCM1480_MC_COL01(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL01) |
| 224 | #define G_BCM1480_MC_COL01(x) _SB_GETVALUE(x,S_BCM1480_MC_COL01,M_BCM1480_MC_COL01) |
| 225 | |
| 226 | #define S_BCM1480_MC_COL02 16 |
| 227 | #define M_BCM1480_MC_COL02 _SB_MAKEMASK(6,S_BCM1480_MC_COL02) |
| 228 | #define V_BCM1480_MC_COL02(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL02) |
| 229 | #define G_BCM1480_MC_COL02(x) _SB_GETVALUE(x,S_BCM1480_MC_COL02,M_BCM1480_MC_COL02) |
| 230 | |
| 231 | #define S_BCM1480_MC_COL03 24 |
| 232 | #define M_BCM1480_MC_COL03 _SB_MAKEMASK(6,S_BCM1480_MC_COL03) |
| 233 | #define V_BCM1480_MC_COL03(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL03) |
| 234 | #define G_BCM1480_MC_COL03(x) _SB_GETVALUE(x,S_BCM1480_MC_COL03,M_BCM1480_MC_COL03) |
| 235 | |
| 236 | #define S_BCM1480_MC_COL04 32 |
| 237 | #define M_BCM1480_MC_COL04 _SB_MAKEMASK(6,S_BCM1480_MC_COL04) |
| 238 | #define V_BCM1480_MC_COL04(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL04) |
| 239 | #define G_BCM1480_MC_COL04(x) _SB_GETVALUE(x,S_BCM1480_MC_COL04,M_BCM1480_MC_COL04) |
| 240 | |
| 241 | #define S_BCM1480_MC_COL05 40 |
| 242 | #define M_BCM1480_MC_COL05 _SB_MAKEMASK(6,S_BCM1480_MC_COL05) |
| 243 | #define V_BCM1480_MC_COL05(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL05) |
| 244 | #define G_BCM1480_MC_COL05(x) _SB_GETVALUE(x,S_BCM1480_MC_COL05,M_BCM1480_MC_COL05) |
| 245 | |
| 246 | #define S_BCM1480_MC_COL06 48 |
| 247 | #define M_BCM1480_MC_COL06 _SB_MAKEMASK(6,S_BCM1480_MC_COL06) |
| 248 | #define V_BCM1480_MC_COL06(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL06) |
| 249 | #define G_BCM1480_MC_COL06(x) _SB_GETVALUE(x,S_BCM1480_MC_COL06,M_BCM1480_MC_COL06) |
| 250 | |
| 251 | #define S_BCM1480_MC_COL07 56 |
| 252 | #define M_BCM1480_MC_COL07 _SB_MAKEMASK(6,S_BCM1480_MC_COL07) |
| 253 | #define V_BCM1480_MC_COL07(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL07) |
| 254 | #define G_BCM1480_MC_COL07(x) _SB_GETVALUE(x,S_BCM1480_MC_COL07,M_BCM1480_MC_COL07) |
| 255 | |
| 256 | /* |
| 257 | * Column Address Bit Select Register 1 (Table 87) |
| 258 | */ |
| 259 | |
| 260 | #define S_BCM1480_MC_COL08 0 |
| 261 | #define M_BCM1480_MC_COL08 _SB_MAKEMASK(6,S_BCM1480_MC_COL08) |
| 262 | #define V_BCM1480_MC_COL08(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL08) |
| 263 | #define G_BCM1480_MC_COL08(x) _SB_GETVALUE(x,S_BCM1480_MC_COL08,M_BCM1480_MC_COL08) |
| 264 | |
| 265 | #define S_BCM1480_MC_COL09 8 |
| 266 | #define M_BCM1480_MC_COL09 _SB_MAKEMASK(6,S_BCM1480_MC_COL09) |
| 267 | #define V_BCM1480_MC_COL09(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL09) |
| 268 | #define G_BCM1480_MC_COL09(x) _SB_GETVALUE(x,S_BCM1480_MC_COL09,M_BCM1480_MC_COL09) |
| 269 | |
| 270 | #define S_BCM1480_MC_COL10 16 /* not a valid position, must be prog as 0 */ |
| 271 | |
| 272 | #define S_BCM1480_MC_COL11 24 |
| 273 | #define M_BCM1480_MC_COL11 _SB_MAKEMASK(6,S_BCM1480_MC_COL11) |
| 274 | #define V_BCM1480_MC_COL11(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL11) |
| 275 | #define G_BCM1480_MC_COL11(x) _SB_GETVALUE(x,S_BCM1480_MC_COL11,M_BCM1480_MC_COL11) |
| 276 | |
| 277 | #define S_BCM1480_MC_COL12 32 |
| 278 | #define M_BCM1480_MC_COL12 _SB_MAKEMASK(6,S_BCM1480_MC_COL12) |
| 279 | #define V_BCM1480_MC_COL12(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL12) |
| 280 | #define G_BCM1480_MC_COL12(x) _SB_GETVALUE(x,S_BCM1480_MC_COL12,M_BCM1480_MC_COL12) |
| 281 | |
| 282 | #define S_BCM1480_MC_COL13 40 |
| 283 | #define M_BCM1480_MC_COL13 _SB_MAKEMASK(6,S_BCM1480_MC_COL13) |
| 284 | #define V_BCM1480_MC_COL13(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL13) |
| 285 | #define G_BCM1480_MC_COL13(x) _SB_GETVALUE(x,S_BCM1480_MC_COL13,M_BCM1480_MC_COL13) |
| 286 | |
| 287 | #define S_BCM1480_MC_COL14 48 |
| 288 | #define M_BCM1480_MC_COL14 _SB_MAKEMASK(6,S_BCM1480_MC_COL14) |
| 289 | #define V_BCM1480_MC_COL14(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COL14) |
| 290 | #define G_BCM1480_MC_COL14(x) _SB_GETVALUE(x,S_BCM1480_MC_COL14,M_BCM1480_MC_COL14) |
| 291 | |
| 292 | #define K_BCM1480_MC_COLX_BIT_SPACING 8 |
| 293 | |
| 294 | /* |
| 295 | * CS0 and CS1 Bank Address Bit Select Register (Table 88) |
| 296 | */ |
| 297 | |
| 298 | #define S_BCM1480_MC_CS01_BANK0 0 |
| 299 | #define M_BCM1480_MC_CS01_BANK0 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK0) |
| 300 | #define V_BCM1480_MC_CS01_BANK0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK0) |
| 301 | #define G_BCM1480_MC_CS01_BANK0(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK0,M_BCM1480_MC_CS01_BANK0) |
| 302 | |
| 303 | #define S_BCM1480_MC_CS01_BANK1 8 |
| 304 | #define M_BCM1480_MC_CS01_BANK1 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK1) |
| 305 | #define V_BCM1480_MC_CS01_BANK1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK1) |
| 306 | #define G_BCM1480_MC_CS01_BANK1(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK1,M_BCM1480_MC_CS01_BANK1) |
| 307 | |
| 308 | #define S_BCM1480_MC_CS01_BANK2 16 |
| 309 | #define M_BCM1480_MC_CS01_BANK2 _SB_MAKEMASK(6,S_BCM1480_MC_CS01_BANK2) |
| 310 | #define V_BCM1480_MC_CS01_BANK2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS01_BANK2) |
| 311 | #define G_BCM1480_MC_CS01_BANK2(x) _SB_GETVALUE(x,S_BCM1480_MC_CS01_BANK2,M_BCM1480_MC_CS01_BANK2) |
| 312 | |
| 313 | /* |
| 314 | * CS2 and CS3 Bank Address Bit Select Register (Table 89) |
| 315 | */ |
| 316 | |
| 317 | #define S_BCM1480_MC_CS23_BANK0 0 |
| 318 | #define M_BCM1480_MC_CS23_BANK0 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK0) |
| 319 | #define V_BCM1480_MC_CS23_BANK0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK0) |
| 320 | #define G_BCM1480_MC_CS23_BANK0(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK0,M_BCM1480_MC_CS23_BANK0) |
| 321 | |
| 322 | #define S_BCM1480_MC_CS23_BANK1 8 |
| 323 | #define M_BCM1480_MC_CS23_BANK1 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK1) |
| 324 | #define V_BCM1480_MC_CS23_BANK1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK1) |
| 325 | #define G_BCM1480_MC_CS23_BANK1(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK1,M_BCM1480_MC_CS23_BANK1) |
| 326 | |
| 327 | #define S_BCM1480_MC_CS23_BANK2 16 |
| 328 | #define M_BCM1480_MC_CS23_BANK2 _SB_MAKEMASK(6,S_BCM1480_MC_CS23_BANK2) |
| 329 | #define V_BCM1480_MC_CS23_BANK2(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CS23_BANK2) |
| 330 | #define G_BCM1480_MC_CS23_BANK2(x) _SB_GETVALUE(x,S_BCM1480_MC_CS23_BANK2,M_BCM1480_MC_CS23_BANK2) |
| 331 | |
| 332 | #define K_BCM1480_MC_CSXX_BANKX_BIT_SPACING 8 |
| 333 | |
| 334 | /* |
| 335 | * DRAM Command Register (Table 90) |
| 336 | */ |
| 337 | |
| 338 | #define S_BCM1480_MC_COMMAND 0 |
| 339 | #define M_BCM1480_MC_COMMAND _SB_MAKEMASK(4,S_BCM1480_MC_COMMAND) |
| 340 | #define V_BCM1480_MC_COMMAND(x) _SB_MAKEVALUE(x,S_BCM1480_MC_COMMAND) |
| 341 | #define G_BCM1480_MC_COMMAND(x) _SB_GETVALUE(x,S_BCM1480_MC_COMMAND,M_BCM1480_MC_COMMAND) |
| 342 | |
| 343 | #define K_BCM1480_MC_COMMAND_EMRS 0 |
| 344 | #define K_BCM1480_MC_COMMAND_MRS 1 |
| 345 | #define K_BCM1480_MC_COMMAND_PRE 2 |
| 346 | #define K_BCM1480_MC_COMMAND_AR 3 |
| 347 | #define K_BCM1480_MC_COMMAND_SETRFSH 4 |
| 348 | #define K_BCM1480_MC_COMMAND_CLRRFSH 5 |
| 349 | #define K_BCM1480_MC_COMMAND_SETPWRDN 6 |
| 350 | #define K_BCM1480_MC_COMMAND_CLRPWRDN 7 |
| 351 | |
| 352 | #if SIBYTE_HDR_FEATURE(1480, PASS2) |
| 353 | #define K_BCM1480_MC_COMMAND_EMRS2 8 |
| 354 | #define K_BCM1480_MC_COMMAND_EMRS3 9 |
| 355 | #define K_BCM1480_MC_COMMAND_ENABLE_MCLK 10 |
| 356 | #define K_BCM1480_MC_COMMAND_DISABLE_MCLK 11 |
| 357 | #endif |
| 358 | |
| 359 | #define V_BCM1480_MC_COMMAND_EMRS V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS) |
| 360 | #define V_BCM1480_MC_COMMAND_MRS V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_MRS) |
| 361 | #define V_BCM1480_MC_COMMAND_PRE V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_PRE) |
| 362 | #define V_BCM1480_MC_COMMAND_AR V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_AR) |
| 363 | #define V_BCM1480_MC_COMMAND_SETRFSH V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETRFSH) |
| 364 | #define V_BCM1480_MC_COMMAND_CLRRFSH V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRRFSH) |
| 365 | #define V_BCM1480_MC_COMMAND_SETPWRDN V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETPWRDN) |
| 366 | #define V_BCM1480_MC_COMMAND_CLRPWRDN V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRPWRDN) |
| 367 | |
| 368 | #if SIBYTE_HDR_FEATURE(1480, PASS2) |
| 369 | #define V_BCM1480_MC_COMMAND_EMRS2 V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS2) |
| 370 | #define V_BCM1480_MC_COMMAND_EMRS3 V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS3) |
| 371 | #define V_BCM1480_MC_COMMAND_ENABLE_MCLK V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_ENABLE_MCLK) |
| 372 | #define V_BCM1480_MC_COMMAND_DISABLE_MCLK V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_DISABLE_MCLK) |
| 373 | #endif |
| 374 | |
| 375 | #define S_BCM1480_MC_CS0 4 |
| 376 | #define M_BCM1480_MC_CS0 _SB_MAKEMASK1(4) |
| 377 | #define M_BCM1480_MC_CS1 _SB_MAKEMASK1(5) |
| 378 | #define M_BCM1480_MC_CS2 _SB_MAKEMASK1(6) |
| 379 | #define M_BCM1480_MC_CS3 _SB_MAKEMASK1(7) |
| 380 | #define M_BCM1480_MC_CS4 _SB_MAKEMASK1(8) |
| 381 | #define M_BCM1480_MC_CS5 _SB_MAKEMASK1(9) |
| 382 | #define M_BCM1480_MC_CS6 _SB_MAKEMASK1(10) |
| 383 | #define M_BCM1480_MC_CS7 _SB_MAKEMASK1(11) |
| 384 | |
| 385 | #define M_BCM1480_MC_CMD_ACTIVE _SB_MAKEMASK1(16) |
| 386 | |
| 387 | /* |
| 388 | * DRAM Mode Register (Table 91) |
| 389 | */ |
| 390 | |
| 391 | #define S_BCM1480_MC_EMODE 0 |
| 392 | #define M_BCM1480_MC_EMODE _SB_MAKEMASK(15,S_BCM1480_MC_EMODE) |
| 393 | #define V_BCM1480_MC_EMODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_EMODE) |
| 394 | #define G_BCM1480_MC_EMODE(x) _SB_GETVALUE(x,S_BCM1480_MC_EMODE,M_BCM1480_MC_EMODE) |
| 395 | #define V_BCM1480_MC_EMODE_DEFAULT V_BCM1480_MC_EMODE(0) |
| 396 | |
| 397 | #define S_BCM1480_MC_MODE 16 |
| 398 | #define M_BCM1480_MC_MODE _SB_MAKEMASK(15,S_BCM1480_MC_MODE) |
| 399 | #define V_BCM1480_MC_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_MODE) |
| 400 | #define G_BCM1480_MC_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_MODE,M_BCM1480_MC_MODE) |
| 401 | #define V_BCM1480_MC_MODE_DEFAULT V_BCM1480_MC_MODE(0) |
| 402 | |
| 403 | #define S_BCM1480_MC_DRAM_TYPE 32 |
| 404 | #define M_BCM1480_MC_DRAM_TYPE _SB_MAKEMASK(4,S_BCM1480_MC_DRAM_TYPE) |
| 405 | #define V_BCM1480_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DRAM_TYPE) |
| 406 | #define G_BCM1480_MC_DRAM_TYPE(x) _SB_GETVALUE(x,S_BCM1480_MC_DRAM_TYPE,M_BCM1480_MC_DRAM_TYPE) |
| 407 | |
| 408 | #define K_BCM1480_MC_DRAM_TYPE_JEDEC 0 |
| 409 | #define K_BCM1480_MC_DRAM_TYPE_FCRAM 1 |
| 410 | |
| 411 | #if SIBYTE_HDR_FEATURE(1480, PASS2) |
| 412 | #define K_BCM1480_MC_DRAM_TYPE_DDR2 2 |
| 413 | #endif |
| 414 | |
| 415 | #define V_BCM1480_MC_DRAM_TYPE_JEDEC V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_JEDEC) |
| 416 | #define V_BCM1480_MC_DRAM_TYPE_FCRAM V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_FCRAM) |
| 417 | |
| 418 | #if SIBYTE_HDR_FEATURE(1480, PASS2) |
| 419 | #define V_BCM1480_MC_DRAM_TYPE_DDR2 V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_DDR2) |
| 420 | #endif |
| 421 | |
| 422 | #define M_BCM1480_MC_GANGED _SB_MAKEMASK1(36) |
| 423 | #define M_BCM1480_MC_BY9_INTF _SB_MAKEMASK1(37) |
| 424 | #define M_BCM1480_MC_FORCE_ECC64 _SB_MAKEMASK1(38) |
| 425 | #define M_BCM1480_MC_ECC_DISABLE _SB_MAKEMASK1(39) |
| 426 | |
| 427 | #define S_BCM1480_MC_PG_POLICY 40 |
| 428 | #define M_BCM1480_MC_PG_POLICY _SB_MAKEMASK(2,S_BCM1480_MC_PG_POLICY) |
| 429 | #define V_BCM1480_MC_PG_POLICY(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PG_POLICY) |
| 430 | #define G_BCM1480_MC_PG_POLICY(x) _SB_GETVALUE(x,S_BCM1480_MC_PG_POLICY,M_BCM1480_MC_PG_POLICY) |
| 431 | |
| 432 | #define K_BCM1480_MC_PG_POLICY_CLOSED 0 |
| 433 | #define K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK 1 |
| 434 | |
| 435 | #define V_BCM1480_MC_PG_POLICY_CLOSED V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CLOSED) |
| 436 | #define V_BCM1480_MC_PG_POLICY_CAS_TIME_CHK V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK) |
| 437 | |
| 438 | #if SIBYTE_HDR_FEATURE(1480, PASS2) |
| 439 | #define M_BCM1480_MC_2T_CMD _SB_MAKEMASK1(42) |
| 440 | #define M_BCM1480_MC_ECC_COR_DIS _SB_MAKEMASK1(43) |
| 441 | #endif |
| 442 | |
| 443 | #define V_BCM1480_MC_DRAMMODE_DEFAULT V_BCM1480_MC_EMODE_DEFAULT | V_BCM1480_MC_MODE_DEFAULT | V_BCM1480_MC_DRAM_TYPE_JEDEC | \ |
| 444 | V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK) |
| 445 | |
| 446 | /* |
| 447 | * Memory Clock Configuration Register (Table 92) |
| 448 | */ |
| 449 | |
| 450 | #define S_BCM1480_MC_CLK_RATIO 0 |
| 451 | #define M_BCM1480_MC_CLK_RATIO _SB_MAKEMASK(6,S_BCM1480_MC_CLK_RATIO) |
| 452 | #define V_BCM1480_MC_CLK_RATIO(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CLK_RATIO) |
| 453 | #define G_BCM1480_MC_CLK_RATIO(x) _SB_GETVALUE(x,S_BCM1480_MC_CLK_RATIO,M_BCM1480_MC_CLK_RATIO) |
| 454 | |
| 455 | #define V_BCM1480_MC_CLK_RATIO_DEFAULT V_BCM1480_MC_CLK_RATIO(10) |
| 456 | |
| 457 | #define S_BCM1480_MC_REF_RATE 8 |
| 458 | #define M_BCM1480_MC_REF_RATE _SB_MAKEMASK(8,S_BCM1480_MC_REF_RATE) |
| 459 | #define V_BCM1480_MC_REF_RATE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_REF_RATE) |
| 460 | #define G_BCM1480_MC_REF_RATE(x) _SB_GETVALUE(x,S_BCM1480_MC_REF_RATE,M_BCM1480_MC_REF_RATE) |
| 461 | |
| 462 | #define K_BCM1480_MC_REF_RATE_100MHz 0x31 |
| 463 | #define K_BCM1480_MC_REF_RATE_200MHz 0x62 |
| 464 | #define K_BCM1480_MC_REF_RATE_400MHz 0xC4 |
| 465 | |
| 466 | #define V_BCM1480_MC_REF_RATE_100MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_100MHz) |
| 467 | #define V_BCM1480_MC_REF_RATE_200MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_200MHz) |
| 468 | #define V_BCM1480_MC_REF_RATE_400MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_400MHz) |
| 469 | #define V_BCM1480_MC_REF_RATE_DEFAULT V_BCM1480_MC_REF_RATE_400MHz |
| 470 | |
| 471 | #if SIBYTE_HDR_FEATURE(1480, PASS2) |
| 472 | #define M_BCM1480_MC_AUTO_REF_DIS _SB_MAKEMASK1(16) |
| 473 | #endif |
| 474 | |
| 475 | /* |
| 476 | * ODT Register (Table 99) |
| 477 | */ |
| 478 | |
| 479 | #if SIBYTE_HDR_FEATURE(1480, PASS2) |
| 480 | #define M_BCM1480_MC_RD_ODT0_CS0 _SB_MAKEMASK1(0) |
| 481 | #define M_BCM1480_MC_RD_ODT0_CS2 _SB_MAKEMASK1(1) |
| 482 | #define M_BCM1480_MC_RD_ODT0_CS4 _SB_MAKEMASK1(2) |
| 483 | #define M_BCM1480_MC_RD_ODT0_CS6 _SB_MAKEMASK1(3) |
| 484 | #define M_BCM1480_MC_WR_ODT0_CS0 _SB_MAKEMASK1(4) |
| 485 | #define M_BCM1480_MC_WR_ODT0_CS2 _SB_MAKEMASK1(5) |
| 486 | #define M_BCM1480_MC_WR_ODT0_CS4 _SB_MAKEMASK1(6) |
| 487 | #define M_BCM1480_MC_WR_ODT0_CS6 _SB_MAKEMASK1(7) |
| 488 | #define M_BCM1480_MC_RD_ODT2_CS0 _SB_MAKEMASK1(8) |
| 489 | #define M_BCM1480_MC_RD_ODT2_CS2 _SB_MAKEMASK1(9) |
| 490 | #define M_BCM1480_MC_RD_ODT2_CS4 _SB_MAKEMASK1(10) |
| 491 | #define M_BCM1480_MC_RD_ODT2_CS6 _SB_MAKEMASK1(11) |
| 492 | #define M_BCM1480_MC_WR_ODT2_CS0 _SB_MAKEMASK1(12) |
| 493 | #define M_BCM1480_MC_WR_ODT2_CS2 _SB_MAKEMASK1(13) |
| 494 | #define M_BCM1480_MC_WR_ODT2_CS4 _SB_MAKEMASK1(14) |
| 495 | #define M_BCM1480_MC_WR_ODT2_CS6 _SB_MAKEMASK1(15) |
| 496 | #define M_BCM1480_MC_RD_ODT4_CS0 _SB_MAKEMASK1(16) |
| 497 | #define M_BCM1480_MC_RD_ODT4_CS2 _SB_MAKEMASK1(17) |
| 498 | #define M_BCM1480_MC_RD_ODT4_CS4 _SB_MAKEMASK1(18) |
| 499 | #define M_BCM1480_MC_RD_ODT4_CS6 _SB_MAKEMASK1(19) |
| 500 | #define M_BCM1480_MC_WR_ODT4_CS0 _SB_MAKEMASK1(20) |
| 501 | #define M_BCM1480_MC_WR_ODT4_CS2 _SB_MAKEMASK1(21) |
| 502 | #define M_BCM1480_MC_WR_ODT4_CS4 _SB_MAKEMASK1(22) |
| 503 | #define M_BCM1480_MC_WR_ODT4_CS6 _SB_MAKEMASK1(23) |
| 504 | #define M_BCM1480_MC_RD_ODT6_CS0 _SB_MAKEMASK1(24) |
| 505 | #define M_BCM1480_MC_RD_ODT6_CS2 _SB_MAKEMASK1(25) |
| 506 | #define M_BCM1480_MC_RD_ODT6_CS4 _SB_MAKEMASK1(26) |
| 507 | #define M_BCM1480_MC_RD_ODT6_CS6 _SB_MAKEMASK1(27) |
| 508 | #define M_BCM1480_MC_WR_ODT6_CS0 _SB_MAKEMASK1(28) |
| 509 | #define M_BCM1480_MC_WR_ODT6_CS2 _SB_MAKEMASK1(29) |
| 510 | #define M_BCM1480_MC_WR_ODT6_CS4 _SB_MAKEMASK1(30) |
| 511 | #define M_BCM1480_MC_WR_ODT6_CS6 _SB_MAKEMASK1(31) |
| 512 | |
| 513 | #define M_BCM1480_MC_CS_ODD_ODT_EN _SB_MAKEMASK1(32) |
| 514 | #endif |
| 515 | |
| 516 | /* |
| 517 | * Memory DLL Configuration Register (Table 93) |
| 518 | */ |
| 519 | |
| 520 | #define S_BCM1480_MC_ADDR_COARSE_ADJ 0 |
| 521 | #define M_BCM1480_MC_ADDR_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_ADDR_COARSE_ADJ) |
| 522 | #define V_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_COARSE_ADJ) |
| 523 | #define G_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_COARSE_ADJ,M_BCM1480_MC_ADDR_COARSE_ADJ) |
| 524 | #define V_BCM1480_MC_ADDR_COARSE_ADJ_DEFAULT V_BCM1480_MC_ADDR_COARSE_ADJ(0x0) |
| 525 | |
| 526 | #if SIBYTE_HDR_FEATURE(1480, PASS2) |
| 527 | #define S_BCM1480_MC_ADDR_FREQ_RANGE 8 |
| 528 | #define M_BCM1480_MC_ADDR_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_ADDR_FREQ_RANGE) |
| 529 | #define V_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_FREQ_RANGE) |
| 530 | #define G_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_FREQ_RANGE,M_BCM1480_MC_ADDR_FREQ_RANGE) |
| 531 | #define V_BCM1480_MC_ADDR_FREQ_RANGE_DEFAULT V_BCM1480_MC_ADDR_FREQ_RANGE(0x4) |
| 532 | #endif |
| 533 | |
| 534 | #define S_BCM1480_MC_ADDR_FINE_ADJ 8 |
| 535 | #define M_BCM1480_MC_ADDR_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_ADDR_FINE_ADJ) |
| 536 | #define V_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ADDR_FINE_ADJ) |
| 537 | #define G_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_ADDR_FINE_ADJ,M_BCM1480_MC_ADDR_FINE_ADJ) |
| 538 | #define V_BCM1480_MC_ADDR_FINE_ADJ_DEFAULT V_BCM1480_MC_ADDR_FINE_ADJ(0x8) |
| 539 | |
| 540 | #define S_BCM1480_MC_DQI_COARSE_ADJ 16 |
| 541 | #define M_BCM1480_MC_DQI_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_DQI_COARSE_ADJ) |
| 542 | #define V_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_COARSE_ADJ) |
| 543 | #define G_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_COARSE_ADJ,M_BCM1480_MC_DQI_COARSE_ADJ) |
| 544 | #define V_BCM1480_MC_DQI_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQI_COARSE_ADJ(0x0) |
| 545 | |
| 546 | #if SIBYTE_HDR_FEATURE(1480, PASS2) |
| 547 | #define S_BCM1480_MC_DQI_FREQ_RANGE 24 |
| 548 | #define M_BCM1480_MC_DQI_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DQI_FREQ_RANGE) |
| 549 | #define V_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_FREQ_RANGE) |
| 550 | #define G_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_FREQ_RANGE,M_BCM1480_MC_DQI_FREQ_RANGE) |
| 551 | #define V_BCM1480_MC_DQI_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQI_FREQ_RANGE(0x4) |
| 552 | #endif |
| 553 | |
| 554 | #define S_BCM1480_MC_DQI_FINE_ADJ 24 |
| 555 | #define M_BCM1480_MC_DQI_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_DQI_FINE_ADJ) |
| 556 | #define V_BCM1480_MC_DQI_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQI_FINE_ADJ) |
| 557 | #define G_BCM1480_MC_DQI_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQI_FINE_ADJ,M_BCM1480_MC_DQI_FINE_ADJ) |
| 558 | #define V_BCM1480_MC_DQI_FINE_ADJ_DEFAULT V_BCM1480_MC_DQI_FINE_ADJ(0x8) |
| 559 | |
| 560 | #define S_BCM1480_MC_DQO_COARSE_ADJ 32 |
| 561 | #define M_BCM1480_MC_DQO_COARSE_ADJ _SB_MAKEMASK(6,S_BCM1480_MC_DQO_COARSE_ADJ) |
| 562 | #define V_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_COARSE_ADJ) |
| 563 | #define G_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_COARSE_ADJ,M_BCM1480_MC_DQO_COARSE_ADJ) |
| 564 | #define V_BCM1480_MC_DQO_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQO_COARSE_ADJ(0x0) |
| 565 | |
| 566 | #if SIBYTE_HDR_FEATURE(1480, PASS2) |
| 567 | #define S_BCM1480_MC_DQO_FREQ_RANGE 40 |
| 568 | #define M_BCM1480_MC_DQO_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DQO_FREQ_RANGE) |
| 569 | #define V_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_FREQ_RANGE) |
| 570 | #define G_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_FREQ_RANGE,M_BCM1480_MC_DQO_FREQ_RANGE) |
| 571 | #define V_BCM1480_MC_DQO_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQO_FREQ_RANGE(0x4) |
| 572 | #endif |
| 573 | |
| 574 | #define S_BCM1480_MC_DQO_FINE_ADJ 40 |
| 575 | #define M_BCM1480_MC_DQO_FINE_ADJ _SB_MAKEMASK(4,S_BCM1480_MC_DQO_FINE_ADJ) |
| 576 | #define V_BCM1480_MC_DQO_FINE_ADJ(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DQO_FINE_ADJ) |
| 577 | #define G_BCM1480_MC_DQO_FINE_ADJ(x) _SB_GETVALUE(x,S_BCM1480_MC_DQO_FINE_ADJ,M_BCM1480_MC_DQO_FINE_ADJ) |
| 578 | #define V_BCM1480_MC_DQO_FINE_ADJ_DEFAULT V_BCM1480_MC_DQO_FINE_ADJ(0x8) |
| 579 | |
| 580 | #if SIBYTE_HDR_FEATURE(1480, PASS2) |
| 581 | #define S_BCM1480_MC_DLL_PDSEL 44 |
| 582 | #define M_BCM1480_MC_DLL_PDSEL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_PDSEL) |
| 583 | #define V_BCM1480_MC_DLL_PDSEL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_PDSEL) |
| 584 | #define G_BCM1480_MC_DLL_PDSEL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_PDSEL,M_BCM1480_MC_DLL_PDSEL) |
| 585 | #define V_BCM1480_MC_DLL_DEFAULT_PDSEL V_BCM1480_MC_DLL_PDSEL(0x0) |
| 586 | |
| 587 | #define M_BCM1480_MC_DLL_REGBYPASS _SB_MAKEMASK1(46) |
| 588 | #define M_BCM1480_MC_DQO_SHIFT _SB_MAKEMASK1(47) |
| 589 | #endif |
| 590 | |
| 591 | #define S_BCM1480_MC_DLL_DEFAULT 48 |
| 592 | #define M_BCM1480_MC_DLL_DEFAULT _SB_MAKEMASK(6,S_BCM1480_MC_DLL_DEFAULT) |
| 593 | #define V_BCM1480_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_DEFAULT) |
| 594 | #define G_BCM1480_MC_DLL_DEFAULT(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_DEFAULT,M_BCM1480_MC_DLL_DEFAULT) |
| 595 | #define V_BCM1480_MC_DLL_DEFAULT_DEFAULT V_BCM1480_MC_DLL_DEFAULT(0x10) |
| 596 | |
| 597 | #if SIBYTE_HDR_FEATURE(1480, PASS2) |
| 598 | #define S_BCM1480_MC_DLL_REGCTRL 54 |
| 599 | #define M_BCM1480_MC_DLL_REGCTRL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_REGCTRL) |
| 600 | #define V_BCM1480_MC_DLL_REGCTRL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_REGCTRL) |
| 601 | #define G_BCM1480_MC_DLL_REGCTRL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_REGCTRL,M_BCM1480_MC_DLL_REGCTRL) |
| 602 | #define V_BCM1480_MC_DLL_DEFAULT_REGCTRL V_BCM1480_MC_DLL_REGCTRL(0x0) |
| 603 | #endif |
| 604 | |
| 605 | #if SIBYTE_HDR_FEATURE(1480, PASS2) |
| 606 | #define S_BCM1480_MC_DLL_FREQ_RANGE 56 |
| 607 | #define M_BCM1480_MC_DLL_FREQ_RANGE _SB_MAKEMASK(4,S_BCM1480_MC_DLL_FREQ_RANGE) |
| 608 | #define V_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_FREQ_RANGE) |
| 609 | #define G_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_FREQ_RANGE,M_BCM1480_MC_DLL_FREQ_RANGE) |
| 610 | #define V_BCM1480_MC_DLL_FREQ_RANGE_DEFAULT V_BCM1480_MC_DLL_FREQ_RANGE(0x4) |
| 611 | #endif |
| 612 | |
| 613 | #define S_BCM1480_MC_DLL_STEP_SIZE 56 |
| 614 | #define M_BCM1480_MC_DLL_STEP_SIZE _SB_MAKEMASK(4,S_BCM1480_MC_DLL_STEP_SIZE) |
| 615 | #define V_BCM1480_MC_DLL_STEP_SIZE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_STEP_SIZE) |
| 616 | #define G_BCM1480_MC_DLL_STEP_SIZE(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_STEP_SIZE,M_BCM1480_MC_DLL_STEP_SIZE) |
| 617 | #define V_BCM1480_MC_DLL_STEP_SIZE_DEFAULT V_BCM1480_MC_DLL_STEP_SIZE(0x8) |
| 618 | |
| 619 | #if SIBYTE_HDR_FEATURE(1480, PASS2) |
| 620 | #define S_BCM1480_MC_DLL_BGCTRL 60 |
| 621 | #define M_BCM1480_MC_DLL_BGCTRL _SB_MAKEMASK(2,S_BCM1480_MC_DLL_BGCTRL) |
| 622 | #define V_BCM1480_MC_DLL_BGCTRL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_DLL_BGCTRL) |
| 623 | #define G_BCM1480_MC_DLL_BGCTRL(x) _SB_GETVALUE(x,S_BCM1480_MC_DLL_BGCTRL,M_BCM1480_MC_DLL_BGCTRL) |
| 624 | #define V_BCM1480_MC_DLL_DEFAULT_BGCTRL V_BCM1480_MC_DLL_BGCTRL(0x0) |
| 625 | #endif |
| 626 | |
| 627 | #define M_BCM1480_MC_DLL_BYPASS _SB_MAKEMASK1(63) |
| 628 | |
| 629 | /* |
| 630 | * Memory Drive Configuration Register (Table 94) |
| 631 | */ |
| 632 | |
| 633 | #define S_BCM1480_MC_RTT_BYP_PULLDOWN 0 |
| 634 | #define M_BCM1480_MC_RTT_BYP_PULLDOWN _SB_MAKEMASK(3,S_BCM1480_MC_RTT_BYP_PULLDOWN) |
| 635 | #define V_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_RTT_BYP_PULLDOWN) |
| 636 | #define G_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_RTT_BYP_PULLDOWN,M_BCM1480_MC_RTT_BYP_PULLDOWN) |
| 637 | |
| 638 | #define S_BCM1480_MC_RTT_BYP_PULLUP 6 |
| 639 | #define M_BCM1480_MC_RTT_BYP_PULLUP _SB_MAKEMASK(3,S_BCM1480_MC_RTT_BYP_PULLUP) |
| 640 | #define V_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_RTT_BYP_PULLUP) |
| 641 | #define G_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_RTT_BYP_PULLUP,M_BCM1480_MC_RTT_BYP_PULLUP) |
| 642 | |
| 643 | #define M_BCM1480_MC_RTT_BYPASS _SB_MAKEMASK1(8) |
| 644 | #define M_BCM1480_MC_RTT_COMP_MOV_AVG _SB_MAKEMASK1(9) |
| 645 | |
| 646 | #define S_BCM1480_MC_PVT_BYP_C1_PULLDOWN 10 |
| 647 | #define M_BCM1480_MC_PVT_BYP_C1_PULLDOWN _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) |
| 648 | #define V_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) |
| 649 | #define G_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLDOWN,M_BCM1480_MC_PVT_BYP_C1_PULLDOWN) |
| 650 | |
| 651 | #define S_BCM1480_MC_PVT_BYP_C1_PULLUP 15 |
| 652 | #define M_BCM1480_MC_PVT_BYP_C1_PULLUP _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C1_PULLUP) |
| 653 | #define V_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLUP) |
| 654 | #define G_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C1_PULLUP,M_BCM1480_MC_PVT_BYP_C1_PULLUP) |
| 655 | |
| 656 | #define S_BCM1480_MC_PVT_BYP_C2_PULLDOWN 20 |
| 657 | #define M_BCM1480_MC_PVT_BYP_C2_PULLDOWN _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) |
| 658 | #define V_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) |
| 659 | #define G_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLDOWN,M_BCM1480_MC_PVT_BYP_C2_PULLDOWN) |
| 660 | |
| 661 | #define S_BCM1480_MC_PVT_BYP_C2_PULLUP 25 |
| 662 | #define M_BCM1480_MC_PVT_BYP_C2_PULLUP _SB_MAKEMASK(4,S_BCM1480_MC_PVT_BYP_C2_PULLUP) |
| 663 | #define V_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLUP) |
| 664 | #define G_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_GETVALUE(x,S_BCM1480_MC_PVT_BYP_C2_PULLUP,M_BCM1480_MC_PVT_BYP_C2_PULLUP) |
| 665 | |
| 666 | #define M_BCM1480_MC_PVT_BYPASS _SB_MAKEMASK1(30) |
| 667 | #define M_BCM1480_MC_PVT_COMP_MOV_AVG _SB_MAKEMASK1(31) |
| 668 | |
| 669 | #define M_BCM1480_MC_CLK_CLASS _SB_MAKEMASK1(34) |
| 670 | #define M_BCM1480_MC_DATA_CLASS _SB_MAKEMASK1(35) |
| 671 | #define M_BCM1480_MC_ADDR_CLASS _SB_MAKEMASK1(36) |
| 672 | |
| 673 | #define M_BCM1480_MC_DQ_ODT_75 _SB_MAKEMASK1(37) |
| 674 | #define M_BCM1480_MC_DQ_ODT_150 _SB_MAKEMASK1(38) |
| 675 | #define M_BCM1480_MC_DQS_ODT_75 _SB_MAKEMASK1(39) |
| 676 | #define M_BCM1480_MC_DQS_ODT_150 _SB_MAKEMASK1(40) |
| 677 | #define M_BCM1480_MC_DQS_DIFF _SB_MAKEMASK1(41) |
| 678 | |
| 679 | /* |
| 680 | * ECC Test Data Register (Table 95) |
| 681 | */ |
| 682 | |
| 683 | #define S_BCM1480_MC_DATA_INVERT 0 |
| 684 | #define M_DATA_ECC_INVERT _SB_MAKEMASK(64,S_BCM1480_MC_ECC_INVERT) |
| 685 | |
| 686 | /* |
| 687 | * ECC Test ECC Register (Table 96) |
| 688 | */ |
| 689 | |
| 690 | #define S_BCM1480_MC_ECC_INVERT 0 |
| 691 | #define M_BCM1480_MC_ECC_INVERT _SB_MAKEMASK(8,S_BCM1480_MC_ECC_INVERT) |
| 692 | |
| 693 | /* |
| 694 | * SDRAM Timing Register (Table 97) |
| 695 | */ |
| 696 | |
| 697 | #define S_BCM1480_MC_tRCD 0 |
| 698 | #define M_BCM1480_MC_tRCD _SB_MAKEMASK(4,S_BCM1480_MC_tRCD) |
| 699 | #define V_BCM1480_MC_tRCD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCD) |
| 700 | #define G_BCM1480_MC_tRCD(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCD,M_BCM1480_MC_tRCD) |
| 701 | #define K_BCM1480_MC_tRCD_DEFAULT 3 |
| 702 | #define V_BCM1480_MC_tRCD_DEFAULT V_BCM1480_MC_tRCD(K_BCM1480_MC_tRCD_DEFAULT) |
| 703 | |
| 704 | #define S_BCM1480_MC_tCL 4 |
| 705 | #define M_BCM1480_MC_tCL _SB_MAKEMASK(4,S_BCM1480_MC_tCL) |
| 706 | #define V_BCM1480_MC_tCL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tCL) |
| 707 | #define G_BCM1480_MC_tCL(x) _SB_GETVALUE(x,S_BCM1480_MC_tCL,M_BCM1480_MC_tCL) |
| 708 | #define K_BCM1480_MC_tCL_DEFAULT 2 |
| 709 | #define V_BCM1480_MC_tCL_DEFAULT V_BCM1480_MC_tCL(K_BCM1480_MC_tCL_DEFAULT) |
| 710 | |
| 711 | #define M_BCM1480_MC_tCrDh _SB_MAKEMASK1(8) |
| 712 | |
| 713 | #define S_BCM1480_MC_tWR 9 |
| 714 | #define M_BCM1480_MC_tWR _SB_MAKEMASK(3,S_BCM1480_MC_tWR) |
| 715 | #define V_BCM1480_MC_tWR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tWR) |
| 716 | #define G_BCM1480_MC_tWR(x) _SB_GETVALUE(x,S_BCM1480_MC_tWR,M_BCM1480_MC_tWR) |
| 717 | #define K_BCM1480_MC_tWR_DEFAULT 2 |
| 718 | #define V_BCM1480_MC_tWR_DEFAULT V_BCM1480_MC_tWR(K_BCM1480_MC_tWR_DEFAULT) |
| 719 | |
| 720 | #define S_BCM1480_MC_tCwD 12 |
| 721 | #define M_BCM1480_MC_tCwD _SB_MAKEMASK(4,S_BCM1480_MC_tCwD) |
| 722 | #define V_BCM1480_MC_tCwD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tCwD) |
| 723 | #define G_BCM1480_MC_tCwD(x) _SB_GETVALUE(x,S_BCM1480_MC_tCwD,M_BCM1480_MC_tCwD) |
| 724 | #define K_BCM1480_MC_tCwD_DEFAULT 1 |
| 725 | #define V_BCM1480_MC_tCwD_DEFAULT V_BCM1480_MC_tCwD(K_BCM1480_MC_tCwD_DEFAULT) |
| 726 | |
| 727 | #define S_BCM1480_MC_tRP 16 |
| 728 | #define M_BCM1480_MC_tRP _SB_MAKEMASK(4,S_BCM1480_MC_tRP) |
| 729 | #define V_BCM1480_MC_tRP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRP) |
| 730 | #define G_BCM1480_MC_tRP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRP,M_BCM1480_MC_tRP) |
| 731 | #define K_BCM1480_MC_tRP_DEFAULT 4 |
| 732 | #define V_BCM1480_MC_tRP_DEFAULT V_BCM1480_MC_tRP(K_BCM1480_MC_tRP_DEFAULT) |
| 733 | |
| 734 | #define S_BCM1480_MC_tRRD 20 |
| 735 | #define M_BCM1480_MC_tRRD _SB_MAKEMASK(4,S_BCM1480_MC_tRRD) |
| 736 | #define V_BCM1480_MC_tRRD(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRRD) |
| 737 | #define G_BCM1480_MC_tRRD(x) _SB_GETVALUE(x,S_BCM1480_MC_tRRD,M_BCM1480_MC_tRRD) |
| 738 | #define K_BCM1480_MC_tRRD_DEFAULT 2 |
| 739 | #define V_BCM1480_MC_tRRD_DEFAULT V_BCM1480_MC_tRRD(K_BCM1480_MC_tRRD_DEFAULT) |
| 740 | |
| 741 | #define S_BCM1480_MC_tRCw 24 |
| 742 | #define M_BCM1480_MC_tRCw _SB_MAKEMASK(5,S_BCM1480_MC_tRCw) |
| 743 | #define V_BCM1480_MC_tRCw(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCw) |
| 744 | #define G_BCM1480_MC_tRCw(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCw,M_BCM1480_MC_tRCw) |
| 745 | #define K_BCM1480_MC_tRCw_DEFAULT 10 |
| 746 | #define V_BCM1480_MC_tRCw_DEFAULT V_BCM1480_MC_tRCw(K_BCM1480_MC_tRCw_DEFAULT) |
| 747 | |
| 748 | #define S_BCM1480_MC_tRCr 32 |
| 749 | #define M_BCM1480_MC_tRCr _SB_MAKEMASK(5,S_BCM1480_MC_tRCr) |
| 750 | #define V_BCM1480_MC_tRCr(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRCr) |
| 751 | #define G_BCM1480_MC_tRCr(x) _SB_GETVALUE(x,S_BCM1480_MC_tRCr,M_BCM1480_MC_tRCr) |
| 752 | #define K_BCM1480_MC_tRCr_DEFAULT 9 |
| 753 | #define V_BCM1480_MC_tRCr_DEFAULT V_BCM1480_MC_tRCr(K_BCM1480_MC_tRCr_DEFAULT) |
| 754 | |
| 755 | #if SIBYTE_HDR_FEATURE(1480, PASS2) |
| 756 | #define S_BCM1480_MC_tFAW 40 |
| 757 | #define M_BCM1480_MC_tFAW _SB_MAKEMASK(6,S_BCM1480_MC_tFAW) |
| 758 | #define V_BCM1480_MC_tFAW(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tFAW) |
| 759 | #define G_BCM1480_MC_tFAW(x) _SB_GETVALUE(x,S_BCM1480_MC_tFAW,M_BCM1480_MC_tFAW) |
| 760 | #define K_BCM1480_MC_tFAW_DEFAULT 0 |
| 761 | #define V_BCM1480_MC_tFAW_DEFAULT V_BCM1480_MC_tFAW(K_BCM1480_MC_tFAW_DEFAULT) |
| 762 | #endif |
| 763 | |
| 764 | #define S_BCM1480_MC_tRFC 48 |
| 765 | #define M_BCM1480_MC_tRFC _SB_MAKEMASK(7,S_BCM1480_MC_tRFC) |
| 766 | #define V_BCM1480_MC_tRFC(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRFC) |
| 767 | #define G_BCM1480_MC_tRFC(x) _SB_GETVALUE(x,S_BCM1480_MC_tRFC,M_BCM1480_MC_tRFC) |
| 768 | #define K_BCM1480_MC_tRFC_DEFAULT 12 |
| 769 | #define V_BCM1480_MC_tRFC_DEFAULT V_BCM1480_MC_tRFC(K_BCM1480_MC_tRFC_DEFAULT) |
| 770 | |
| 771 | #define S_BCM1480_MC_tFIFO 56 |
| 772 | #define M_BCM1480_MC_tFIFO _SB_MAKEMASK(2,S_BCM1480_MC_tFIFO) |
| 773 | #define V_BCM1480_MC_tFIFO(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tFIFO) |
| 774 | #define G_BCM1480_MC_tFIFO(x) _SB_GETVALUE(x,S_BCM1480_MC_tFIFO,M_BCM1480_MC_tFIFO) |
| 775 | #define K_BCM1480_MC_tFIFO_DEFAULT 0 |
| 776 | #define V_BCM1480_MC_tFIFO_DEFAULT V_BCM1480_MC_tFIFO(K_BCM1480_MC_tFIFO_DEFAULT) |
| 777 | |
| 778 | #define S_BCM1480_MC_tW2R 58 |
| 779 | #define M_BCM1480_MC_tW2R _SB_MAKEMASK(2,S_BCM1480_MC_tW2R) |
| 780 | #define V_BCM1480_MC_tW2R(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tW2R) |
| 781 | #define G_BCM1480_MC_tW2R(x) _SB_GETVALUE(x,S_BCM1480_MC_tW2R,M_BCM1480_MC_tW2R) |
| 782 | #define K_BCM1480_MC_tW2R_DEFAULT 1 |
| 783 | #define V_BCM1480_MC_tW2R_DEFAULT V_BCM1480_MC_tW2R(K_BCM1480_MC_tW2R_DEFAULT) |
| 784 | |
| 785 | #define S_BCM1480_MC_tR2W 60 |
| 786 | #define M_BCM1480_MC_tR2W _SB_MAKEMASK(2,S_BCM1480_MC_tR2W) |
| 787 | #define V_BCM1480_MC_tR2W(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tR2W) |
| 788 | #define G_BCM1480_MC_tR2W(x) _SB_GETVALUE(x,S_BCM1480_MC_tR2W,M_BCM1480_MC_tR2W) |
| 789 | #define K_BCM1480_MC_tR2W_DEFAULT 0 |
| 790 | #define V_BCM1480_MC_tR2W_DEFAULT V_BCM1480_MC_tR2W(K_BCM1480_MC_tR2W_DEFAULT) |
| 791 | |
| 792 | #define M_BCM1480_MC_tR2R _SB_MAKEMASK1(62) |
| 793 | |
| 794 | #define V_BCM1480_MC_TIMING_DEFAULT (M_BCM1480_MC_tR2R | \ |
| 795 | V_BCM1480_MC_tFIFO_DEFAULT | \ |
| 796 | V_BCM1480_MC_tR2W_DEFAULT | \ |
| 797 | V_BCM1480_MC_tW2R_DEFAULT | \ |
| 798 | V_BCM1480_MC_tRFC_DEFAULT | \ |
| 799 | V_BCM1480_MC_tRCr_DEFAULT | \ |
| 800 | V_BCM1480_MC_tRCw_DEFAULT | \ |
| 801 | V_BCM1480_MC_tRRD_DEFAULT | \ |
| 802 | V_BCM1480_MC_tRP_DEFAULT | \ |
| 803 | V_BCM1480_MC_tCwD_DEFAULT | \ |
| 804 | V_BCM1480_MC_tWR_DEFAULT | \ |
| 805 | M_BCM1480_MC_tCrDh | \ |
| 806 | V_BCM1480_MC_tCL_DEFAULT | \ |
| 807 | V_BCM1480_MC_tRCD_DEFAULT) |
| 808 | |
| 809 | /* |
| 810 | * SDRAM Timing Register 2 |
| 811 | */ |
| 812 | |
| 813 | #if SIBYTE_HDR_FEATURE(1480, PASS2) |
| 814 | |
| 815 | #define S_BCM1480_MC_tAL 0 |
| 816 | #define M_BCM1480_MC_tAL _SB_MAKEMASK(4,S_BCM1480_MC_tAL) |
| 817 | #define V_BCM1480_MC_tAL(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tAL) |
| 818 | #define G_BCM1480_MC_tAL(x) _SB_GETVALUE(x,S_BCM1480_MC_tAL,M_BCM1480_MC_tAL) |
| 819 | #define K_BCM1480_MC_tAL_DEFAULT 0 |
| 820 | #define V_BCM1480_MC_tAL_DEFAULT V_BCM1480_MC_tAL(K_BCM1480_MC_tAL_DEFAULT) |
| 821 | |
| 822 | #define S_BCM1480_MC_tRTP 4 |
| 823 | #define M_BCM1480_MC_tRTP _SB_MAKEMASK(3,S_BCM1480_MC_tRTP) |
| 824 | #define V_BCM1480_MC_tRTP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRTP) |
| 825 | #define G_BCM1480_MC_tRTP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRTP,M_BCM1480_MC_tRTP) |
| 826 | #define K_BCM1480_MC_tRTP_DEFAULT 2 |
| 827 | #define V_BCM1480_MC_tRTP_DEFAULT V_BCM1480_MC_tRTP(K_BCM1480_MC_tRTP_DEFAULT) |
| 828 | |
| 829 | #define S_BCM1480_MC_tW2W 8 |
| 830 | #define M_BCM1480_MC_tW2W _SB_MAKEMASK(2,S_BCM1480_MC_tW2W) |
| 831 | #define V_BCM1480_MC_tW2W(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tW2W) |
| 832 | #define G_BCM1480_MC_tW2W(x) _SB_GETVALUE(x,S_BCM1480_MC_tW2W,M_BCM1480_MC_tW2W) |
| 833 | #define K_BCM1480_MC_tW2W_DEFAULT 0 |
| 834 | #define V_BCM1480_MC_tW2W_DEFAULT V_BCM1480_MC_tW2W(K_BCM1480_MC_tW2W_DEFAULT) |
| 835 | |
| 836 | #define S_BCM1480_MC_tRAP 12 |
| 837 | #define M_BCM1480_MC_tRAP _SB_MAKEMASK(4,S_BCM1480_MC_tRAP) |
| 838 | #define V_BCM1480_MC_tRAP(x) _SB_MAKEVALUE(x,S_BCM1480_MC_tRAP) |
| 839 | #define G_BCM1480_MC_tRAP(x) _SB_GETVALUE(x,S_BCM1480_MC_tRAP,M_BCM1480_MC_tRAP) |
| 840 | #define K_BCM1480_MC_tRAP_DEFAULT 0 |
| 841 | #define V_BCM1480_MC_tRAP_DEFAULT V_BCM1480_MC_tRAP(K_BCM1480_MC_tRAP_DEFAULT) |
| 842 | |
| 843 | #endif |
| 844 | |
| 845 | |
| 846 | |
| 847 | /* |
| 848 | * Global Registers: single instances per BCM1480 |
| 849 | */ |
| 850 | |
| 851 | /* |
| 852 | * Global Configuration Register (Table 99) |
| 853 | */ |
| 854 | |
| 855 | #define S_BCM1480_MC_BLK_SET_MARK 8 |
| 856 | #define M_BCM1480_MC_BLK_SET_MARK _SB_MAKEMASK(4,S_BCM1480_MC_BLK_SET_MARK) |
| 857 | #define V_BCM1480_MC_BLK_SET_MARK(x) _SB_MAKEVALUE(x,S_BCM1480_MC_BLK_SET_MARK) |
| 858 | #define G_BCM1480_MC_BLK_SET_MARK(x) _SB_GETVALUE(x,S_BCM1480_MC_BLK_SET_MARK,M_BCM1480_MC_BLK_SET_MARK) |
| 859 | |
| 860 | #define S_BCM1480_MC_BLK_CLR_MARK 12 |
| 861 | #define M_BCM1480_MC_BLK_CLR_MARK _SB_MAKEMASK(4,S_BCM1480_MC_BLK_CLR_MARK) |
| 862 | #define V_BCM1480_MC_BLK_CLR_MARK(x) _SB_MAKEVALUE(x,S_BCM1480_MC_BLK_CLR_MARK) |
| 863 | #define G_BCM1480_MC_BLK_CLR_MARK(x) _SB_GETVALUE(x,S_BCM1480_MC_BLK_CLR_MARK,M_BCM1480_MC_BLK_CLR_MARK) |
| 864 | |
| 865 | #define M_BCM1480_MC_PKT_PRIORITY _SB_MAKEMASK1(16) |
| 866 | |
| 867 | #define S_BCM1480_MC_MAX_AGE 20 |
| 868 | #define M_BCM1480_MC_MAX_AGE _SB_MAKEMASK(4,S_BCM1480_MC_MAX_AGE) |
| 869 | #define V_BCM1480_MC_MAX_AGE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_MAX_AGE) |
| 870 | #define G_BCM1480_MC_MAX_AGE(x) _SB_GETVALUE(x,S_BCM1480_MC_MAX_AGE,M_BCM1480_MC_MAX_AGE) |
| 871 | |
| 872 | #define M_BCM1480_MC_BERR_DISABLE _SB_MAKEMASK1(29) |
| 873 | #define M_BCM1480_MC_FORCE_SEQ _SB_MAKEMASK1(30) |
| 874 | #define M_BCM1480_MC_VGEN _SB_MAKEMASK1(32) |
| 875 | |
| 876 | #define S_BCM1480_MC_SLEW 33 |
| 877 | #define M_BCM1480_MC_SLEW _SB_MAKEMASK(2,S_BCM1480_MC_SLEW) |
| 878 | #define V_BCM1480_MC_SLEW(x) _SB_MAKEVALUE(x,S_BCM1480_MC_SLEW) |
| 879 | #define G_BCM1480_MC_SLEW(x) _SB_GETVALUE(x,S_BCM1480_MC_SLEW,M_BCM1480_MC_SLEW) |
| 880 | |
| 881 | #define M_BCM1480_MC_SSTL_VOLTAGE _SB_MAKEMASK1(35) |
| 882 | |
| 883 | /* |
| 884 | * Global Channel Interleave Register (Table 100) |
| 885 | */ |
| 886 | |
| 887 | #define S_BCM1480_MC_INTLV0 0 |
| 888 | #define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV0) |
| 889 | #define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV0) |
| 890 | #define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV0,M_BCM1480_MC_INTLV0) |
| 891 | |
| 892 | #define S_BCM1480_MC_INTLV1 8 |
| 893 | #define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6,S_BCM1480_MC_INTLV1) |
| 894 | #define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV1) |
| 895 | #define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV1,M_BCM1480_MC_INTLV1) |
| 896 | |
| 897 | #define S_BCM1480_MC_INTLV_MODE 16 |
| 898 | #define M_BCM1480_MC_INTLV_MODE _SB_MAKEMASK(3,S_BCM1480_MC_INTLV_MODE) |
| 899 | #define V_BCM1480_MC_INTLV_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_MC_INTLV_MODE) |
| 900 | #define G_BCM1480_MC_INTLV_MODE(x) _SB_GETVALUE(x,S_BCM1480_MC_INTLV_MODE,M_BCM1480_MC_INTLV_MODE) |
| 901 | |
| 902 | #define K_BCM1480_MC_INTLV_MODE_NONE 0x0 |
| 903 | #define K_BCM1480_MC_INTLV_MODE_01 0x1 |
| 904 | #define K_BCM1480_MC_INTLV_MODE_23 0x2 |
| 905 | #define K_BCM1480_MC_INTLV_MODE_01_23 0x3 |
| 906 | #define K_BCM1480_MC_INTLV_MODE_0123 0x4 |
| 907 | |
| 908 | #define V_BCM1480_MC_INTLV_MODE_NONE V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_NONE) |
| 909 | #define V_BCM1480_MC_INTLV_MODE_01 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01) |
| 910 | #define V_BCM1480_MC_INTLV_MODE_23 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_23) |
| 911 | #define V_BCM1480_MC_INTLV_MODE_01_23 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01_23) |
| 912 | #define V_BCM1480_MC_INTLV_MODE_0123 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_0123) |
| 913 | |
| 914 | /* |
| 915 | * ECC Status Register |
| 916 | */ |
| 917 | |
| 918 | #define S_BCM1480_MC_ECC_ERR_ADDR 0 |
| 919 | #define M_BCM1480_MC_ECC_ERR_ADDR _SB_MAKEMASK(37,S_BCM1480_MC_ECC_ERR_ADDR) |
| 920 | #define V_BCM1480_MC_ECC_ERR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_ERR_ADDR) |
| 921 | #define G_BCM1480_MC_ECC_ERR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_ERR_ADDR,M_BCM1480_MC_ECC_ERR_ADDR) |
| 922 | |
| 923 | #if SIBYTE_HDR_FEATURE(1480, PASS2) |
| 924 | #define M_BCM1480_MC_ECC_ERR_RMW _SB_MAKEMASK1(60) |
| 925 | #endif |
| 926 | |
| 927 | #define M_BCM1480_MC_ECC_MULT_ERR_DET _SB_MAKEMASK1(61) |
| 928 | #define M_BCM1480_MC_ECC_UERR_DET _SB_MAKEMASK1(62) |
| 929 | #define M_BCM1480_MC_ECC_CERR_DET _SB_MAKEMASK1(63) |
| 930 | |
| 931 | /* |
| 932 | * Global ECC Address Register (Table 102) |
| 933 | */ |
| 934 | |
| 935 | #define S_BCM1480_MC_ECC_CORR_ADDR 0 |
| 936 | #define M_BCM1480_MC_ECC_CORR_ADDR _SB_MAKEMASK(37,S_BCM1480_MC_ECC_CORR_ADDR) |
| 937 | #define V_BCM1480_MC_ECC_CORR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_CORR_ADDR) |
| 938 | #define G_BCM1480_MC_ECC_CORR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_CORR_ADDR,M_BCM1480_MC_ECC_CORR_ADDR) |
| 939 | |
| 940 | /* |
| 941 | * Global ECC Correction Register (Table 103) |
| 942 | */ |
| 943 | |
| 944 | #define S_BCM1480_MC_ECC_CORRECT 0 |
| 945 | #define M_BCM1480_MC_ECC_CORRECT _SB_MAKEMASK(64,S_BCM1480_MC_ECC_CORRECT) |
| 946 | #define V_BCM1480_MC_ECC_CORRECT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_ECC_CORRECT) |
| 947 | #define G_BCM1480_MC_ECC_CORRECT(x) _SB_GETVALUE(x,S_BCM1480_MC_ECC_CORRECT,M_BCM1480_MC_ECC_CORRECT) |
| 948 | |
| 949 | /* |
| 950 | * Global ECC Performance Counters Control Register (Table 104) |
| 951 | */ |
| 952 | |
| 953 | #define S_BCM1480_MC_CHANNEL_SELECT 0 |
| 954 | #define M_BCM1480_MC_CHANNEL_SELECT _SB_MAKEMASK(4,S_BCM1480_MC_CHANNEL_SELECT) |
| 955 | #define V_BCM1480_MC_CHANNEL_SELECT(x) _SB_MAKEVALUE(x,S_BCM1480_MC_CHANNEL_SELECT) |
| 956 | #define G_BCM1480_MC_CHANNEL_SELECT(x) _SB_GETVALUE(x,S_BCM1480_MC_CHANNEL_SELECT,M_BCM1480_MC_CHANNEL_SELECT) |
| 957 | #define K_BCM1480_MC_CHANNEL_SELECT_0 0x1 |
| 958 | #define K_BCM1480_MC_CHANNEL_SELECT_1 0x2 |
| 959 | #define K_BCM1480_MC_CHANNEL_SELECT_2 0x4 |
| 960 | #define K_BCM1480_MC_CHANNEL_SELECT_3 0x8 |
| 961 | |
| 962 | #endif /* _BCM1480_MC_H */ |
