Kalle Valo | 2f01a1f | 2009-04-29 23:33:31 +0300 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of wl12xx |
| 3 | * |
| 4 | * Copyright (C) 2008 Nokia Corporation |
| 5 | * |
| 6 | * Contact: Kalle Valo <kalle.valo@nokia.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License |
| 10 | * version 2 as published by the Free Software Foundation. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, but |
| 13 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA |
| 20 | * 02110-1301 USA |
| 21 | * |
| 22 | */ |
| 23 | |
| 24 | #ifndef __WL1251_H__ |
| 25 | #define __WL1251_H__ |
| 26 | |
| 27 | #include <linux/bitops.h> |
| 28 | |
| 29 | #include "wl12xx.h" |
| 30 | #include "acx.h" |
| 31 | |
| 32 | #define WL1251_FW_NAME "wl1251-fw.bin" |
| 33 | #define WL1251_NVS_NAME "wl1251-nvs.bin" |
| 34 | |
| 35 | #define WL1251_POWER_ON_SLEEP 10 /* in miliseconds */ |
| 36 | |
| 37 | void wl1251_setup(struct wl12xx *wl); |
| 38 | |
| 39 | |
| 40 | struct wl1251_acx_memory { |
| 41 | __le16 num_stations; /* number of STAs to be supported. */ |
| 42 | u16 reserved_1; |
| 43 | |
| 44 | /* |
| 45 | * Nmber of memory buffers for the RX mem pool. |
| 46 | * The actual number may be less if there are |
| 47 | * not enough blocks left for the minimum num |
| 48 | * of TX ones. |
| 49 | */ |
| 50 | u8 rx_mem_block_num; |
| 51 | u8 reserved_2; |
| 52 | u8 num_tx_queues; /* From 1 to 16 */ |
| 53 | u8 host_if_options; /* HOST_IF* */ |
| 54 | u8 tx_min_mem_block_num; |
| 55 | u8 num_ssid_profiles; |
| 56 | __le16 debug_buffer_size; |
| 57 | } __attribute__ ((packed)); |
| 58 | |
| 59 | |
| 60 | #define ACX_RX_DESC_MIN 1 |
| 61 | #define ACX_RX_DESC_MAX 127 |
| 62 | #define ACX_RX_DESC_DEF 32 |
| 63 | struct wl1251_acx_rx_queue_config { |
| 64 | u8 num_descs; |
| 65 | u8 pad; |
| 66 | u8 type; |
| 67 | u8 priority; |
| 68 | __le32 dma_address; |
| 69 | } __attribute__ ((packed)); |
| 70 | |
| 71 | #define ACX_TX_DESC_MIN 1 |
| 72 | #define ACX_TX_DESC_MAX 127 |
| 73 | #define ACX_TX_DESC_DEF 16 |
| 74 | struct wl1251_acx_tx_queue_config { |
| 75 | u8 num_descs; |
| 76 | u8 pad[2]; |
| 77 | u8 attributes; |
| 78 | } __attribute__ ((packed)); |
| 79 | |
| 80 | #define MAX_TX_QUEUE_CONFIGS 5 |
| 81 | #define MAX_TX_QUEUES 4 |
| 82 | struct wl1251_acx_config_memory { |
| 83 | struct acx_header header; |
| 84 | |
| 85 | struct wl1251_acx_memory mem_config; |
| 86 | struct wl1251_acx_rx_queue_config rx_queue_config; |
| 87 | struct wl1251_acx_tx_queue_config tx_queue_config[MAX_TX_QUEUE_CONFIGS]; |
| 88 | } __attribute__ ((packed)); |
| 89 | |
| 90 | struct wl1251_acx_mem_map { |
| 91 | struct acx_header header; |
| 92 | |
| 93 | void *code_start; |
| 94 | void *code_end; |
| 95 | |
| 96 | void *wep_defkey_start; |
| 97 | void *wep_defkey_end; |
| 98 | |
| 99 | void *sta_table_start; |
| 100 | void *sta_table_end; |
| 101 | |
| 102 | void *packet_template_start; |
| 103 | void *packet_template_end; |
| 104 | |
| 105 | void *queue_memory_start; |
| 106 | void *queue_memory_end; |
| 107 | |
| 108 | void *packet_memory_pool_start; |
| 109 | void *packet_memory_pool_end; |
| 110 | |
| 111 | void *debug_buffer1_start; |
| 112 | void *debug_buffer1_end; |
| 113 | |
| 114 | void *debug_buffer2_start; |
| 115 | void *debug_buffer2_end; |
| 116 | |
| 117 | /* Number of blocks FW allocated for TX packets */ |
| 118 | u32 num_tx_mem_blocks; |
| 119 | |
| 120 | /* Number of blocks FW allocated for RX packets */ |
| 121 | u32 num_rx_mem_blocks; |
| 122 | } __attribute__ ((packed)); |
| 123 | |
| 124 | /************************************************************************* |
| 125 | |
| 126 | Host Interrupt Register (WiLink -> Host) |
| 127 | |
| 128 | **************************************************************************/ |
| 129 | |
| 130 | /* RX packet is ready in Xfer buffer #0 */ |
| 131 | #define WL1251_ACX_INTR_RX0_DATA BIT(0) |
| 132 | |
| 133 | /* TX result(s) are in the TX complete buffer */ |
| 134 | #define WL1251_ACX_INTR_TX_RESULT BIT(1) |
| 135 | |
| 136 | /* OBSOLETE */ |
| 137 | #define WL1251_ACX_INTR_TX_XFR BIT(2) |
| 138 | |
| 139 | /* RX packet is ready in Xfer buffer #1 */ |
| 140 | #define WL1251_ACX_INTR_RX1_DATA BIT(3) |
| 141 | |
| 142 | /* Event was entered to Event MBOX #A */ |
| 143 | #define WL1251_ACX_INTR_EVENT_A BIT(4) |
| 144 | |
| 145 | /* Event was entered to Event MBOX #B */ |
| 146 | #define WL1251_ACX_INTR_EVENT_B BIT(5) |
| 147 | |
| 148 | /* OBSOLETE */ |
| 149 | #define WL1251_ACX_INTR_WAKE_ON_HOST BIT(6) |
| 150 | |
| 151 | /* Trace meassge on MBOX #A */ |
| 152 | #define WL1251_ACX_INTR_TRACE_A BIT(7) |
| 153 | |
| 154 | /* Trace meassge on MBOX #B */ |
| 155 | #define WL1251_ACX_INTR_TRACE_B BIT(8) |
| 156 | |
| 157 | /* Command processing completion */ |
| 158 | #define WL1251_ACX_INTR_CMD_COMPLETE BIT(9) |
| 159 | |
| 160 | /* Init sequence is done */ |
| 161 | #define WL1251_ACX_INTR_INIT_COMPLETE BIT(14) |
| 162 | |
| 163 | #define WL1251_ACX_INTR_ALL 0xFFFFFFFF |
| 164 | |
| 165 | #endif |