blob: 1970ef911c99b368e2f1f9e947bcdae71d2a2d84 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Machine check handler.
Ingo Molnare9eee032009-04-08 12:31:17 +02003 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
Thomas Gleixnerd88203d2007-10-23 22:37:23 +02005 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
Andi Kleenb79109c2009-02-12 13:43:23 +01007 * Copyright 2008 Intel Corporation
8 * Author: Andi Kleen
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 */
Tim Hockine02e68d2007-07-21 17:10:36 +020010#include <linux/thread_info.h>
Ingo Molnare9eee032009-04-08 12:31:17 +020011#include <linux/capability.h>
12#include <linux/miscdevice.h>
Andi Kleenccc3c312009-05-27 21:56:54 +020013#include <linux/interrupt.h>
Andi Kleen8457c842009-02-12 13:49:33 +010014#include <linux/ratelimit.h>
Ingo Molnare9eee032009-04-08 12:31:17 +020015#include <linux/kallsyms.h>
16#include <linux/rcupdate.h>
Ingo Molnare9eee032009-04-08 12:31:17 +020017#include <linux/kobject.h>
Hidetoshi Seto14a02532009-04-30 16:04:51 +090018#include <linux/uaccess.h>
Ingo Molnare9eee032009-04-08 12:31:17 +020019#include <linux/kdebug.h>
20#include <linux/kernel.h>
21#include <linux/percpu.h>
22#include <linux/string.h>
23#include <linux/sysdev.h>
Andi Kleen3c079792009-05-27 21:56:55 +020024#include <linux/delay.h>
Ingo Molnare9eee032009-04-08 12:31:17 +020025#include <linux/ctype.h>
26#include <linux/sched.h>
27#include <linux/sysfs.h>
28#include <linux/types.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090029#include <linux/slab.h>
Ingo Molnare9eee032009-04-08 12:31:17 +020030#include <linux/init.h>
31#include <linux/kmod.h>
32#include <linux/poll.h>
Andi Kleen3c079792009-05-27 21:56:55 +020033#include <linux/nmi.h>
Ingo Molnare9eee032009-04-08 12:31:17 +020034#include <linux/cpu.h>
Hidetoshi Seto14a02532009-04-30 16:04:51 +090035#include <linux/smp.h>
Ingo Molnare9eee032009-04-08 12:31:17 +020036#include <linux/fs.h>
Andi Kleen9b1beaf2009-05-27 21:56:59 +020037#include <linux/mm.h>
Huang Ying5be9ed22009-07-31 09:41:42 +080038#include <linux/debugfs.h>
Mauro Carvalho Chehab696e4092009-07-23 06:57:45 -030039#include <linux/edac_mce.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070040
Ingo Molnare9eee032009-04-08 12:31:17 +020041#include <asm/processor.h>
Andi Kleenccc3c312009-05-27 21:56:54 +020042#include <asm/hw_irq.h>
43#include <asm/apic.h>
Ingo Molnare9eee032009-04-08 12:31:17 +020044#include <asm/idle.h>
Andi Kleenccc3c312009-05-27 21:56:54 +020045#include <asm/ipi.h>
Ingo Molnare9eee032009-04-08 12:31:17 +020046#include <asm/mce.h>
47#include <asm/msr.h>
Ingo Molnare9eee032009-04-08 12:31:17 +020048
Andi Kleenbd19a5e2009-05-27 21:56:55 +020049#include "mce-internal.h"
Ingo Molnar711c2e42009-04-08 12:31:26 +020050
Ingo Molnar2aa2b502010-03-14 08:57:03 +010051static DEFINE_MUTEX(mce_read_mutex);
52
Paul E. McKenneyf56e8a02010-03-05 15:03:27 -080053#define rcu_dereference_check_mce(p) \
54 rcu_dereference_check((p), \
55 rcu_read_lock_sched_held() || \
56 lockdep_is_held(&mce_read_mutex))
57
Hidetoshi Seto8968f9d2009-10-13 16:19:41 +090058#define CREATE_TRACE_POINTS
59#include <trace/events/mce.h>
60
Hidetoshi Seto4e5b3e62009-06-15 17:20:20 +090061int mce_disabled __read_mostly;
Andi Kleen04b2b1a2009-04-28 22:50:19 +020062
Ingo Molnare9eee032009-04-08 12:31:17 +020063#define MISC_MCELOG_MINOR 227
Andi Kleen0d7482e2009-02-17 23:07:13 +010064
Andi Kleen3c079792009-05-27 21:56:55 +020065#define SPINUNIT 100 /* 100ns */
66
Andi Kleen553f2652006-04-07 19:49:57 +020067atomic_t mce_entry;
68
Andi Kleen01ca79f2009-05-27 21:56:52 +020069DEFINE_PER_CPU(unsigned, mce_exception_count);
70
Tim Hockinbd784322007-07-21 17:10:37 +020071/*
72 * Tolerant levels:
73 * 0: always panic on uncorrected errors, log corrected errors
74 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
75 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
76 * 3: never panic or SIGBUS, log all errors (for testing only)
77 */
Hidetoshi Seto4e5b3e62009-06-15 17:20:20 +090078static int tolerant __read_mostly = 1;
79static int banks __read_mostly;
Hidetoshi Seto4e5b3e62009-06-15 17:20:20 +090080static int rip_msr __read_mostly;
81static int mce_bootlog __read_mostly = -1;
82static int monarch_timeout __read_mostly = -1;
83static int mce_panic_timeout __read_mostly;
84static int mce_dont_log_ce __read_mostly;
85int mce_cmci_disabled __read_mostly;
86int mce_ignore_ce __read_mostly;
87int mce_ser __read_mostly;
Andi Kleena98f0dd2007-02-13 13:26:23 +010088
Andi Kleencebe1822009-07-09 00:31:43 +020089struct mce_bank *mce_banks __read_mostly;
90
Hidetoshi Seto1020bcb2009-06-15 17:20:57 +090091/* User mode helper program triggered by machine check event */
92static unsigned long mce_need_notify;
93static char mce_helper[128];
94static char *mce_helper_argv[2] = { mce_helper, NULL };
Linus Torvalds1da177e2005-04-16 15:20:36 -070095
Tim Hockine02e68d2007-07-21 17:10:36 +020096static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
Andi Kleen3c079792009-05-27 21:56:55 +020097static DEFINE_PER_CPU(struct mce, mces_seen);
98static int cpu_missing;
99
Borislav Petkovfb253192009-10-07 13:20:38 +0200100/*
101 * CPU/chipset specific EDAC code can register a notifier call here to print
102 * MCE errors in a human-readable form.
103 */
104ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
105EXPORT_SYMBOL_GPL(x86_mce_decoder_chain);
106
107static int default_decode_mce(struct notifier_block *nb, unsigned long val,
108 void *data)
Ingo Molnarf436f8b2009-10-01 16:14:32 +0200109{
110 pr_emerg("No human readable MCE decoding support on this CPU type.\n");
111 pr_emerg("Run the message through 'mcelog --ascii' to decode.\n");
Borislav Petkovfb253192009-10-07 13:20:38 +0200112
113 return NOTIFY_STOP;
Ingo Molnarf436f8b2009-10-01 16:14:32 +0200114}
115
Borislav Petkovfb253192009-10-07 13:20:38 +0200116static struct notifier_block mce_dec_nb = {
117 .notifier_call = default_decode_mce,
118 .priority = -1,
119};
Tim Hockine02e68d2007-07-21 17:10:36 +0200120
Andi Kleenee031c32009-02-12 13:49:34 +0100121/* MCA banks polled by the period polling timer for corrected events */
122DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
123 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
124};
125
Andi Kleen9b1beaf2009-05-27 21:56:59 +0200126static DEFINE_PER_CPU(struct work_struct, mce_work);
127
Andi Kleenb5f2fa42009-02-12 13:43:22 +0100128/* Do initial initialization of a struct mce */
129void mce_setup(struct mce *m)
130{
131 memset(m, 0, sizeof(struct mce));
Andi Kleend620c672009-05-27 21:56:56 +0200132 m->cpu = m->extcpu = smp_processor_id();
Andi Kleenb5f2fa42009-02-12 13:43:22 +0100133 rdtscll(m->tsc);
Andi Kleen8ee08342009-05-27 21:56:56 +0200134 /* We hope get_seconds stays lockless */
135 m->time = get_seconds();
136 m->cpuvendor = boot_cpu_data.x86_vendor;
137 m->cpuid = cpuid_eax(1);
138#ifdef CONFIG_SMP
139 m->socketid = cpu_data(m->extcpu).phys_proc_id;
140#endif
141 m->apicid = cpu_data(m->extcpu).initial_apicid;
142 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
Andi Kleenb5f2fa42009-02-12 13:43:22 +0100143}
144
Andi Kleenea149b32009-04-29 19:31:00 +0200145DEFINE_PER_CPU(struct mce, injectm);
146EXPORT_PER_CPU_SYMBOL_GPL(injectm);
147
Linus Torvalds1da177e2005-04-16 15:20:36 -0700148/*
149 * Lockless MCE logging infrastructure.
150 * This avoids deadlocks on printk locks without having to break locks. Also
151 * separate MCEs from kernel messages to avoid bogus bug reports.
152 */
153
Adrian Bunk231fd902008-01-30 13:30:30 +0100154static struct mce_log mcelog = {
Andi Kleenf6fb0ac2009-05-27 21:56:55 +0200155 .signature = MCE_LOG_SIGNATURE,
156 .len = MCE_LOG_LEN,
157 .recordlen = sizeof(struct mce),
Thomas Gleixnerd88203d2007-10-23 22:37:23 +0200158};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700159
160void mce_log(struct mce *mce)
161{
162 unsigned next, entry;
Ingo Molnare9eee032009-04-08 12:31:17 +0200163
Hidetoshi Seto8968f9d2009-10-13 16:19:41 +0900164 /* Emit the trace record: */
165 trace_mce_record(mce);
166
Linus Torvalds1da177e2005-04-16 15:20:36 -0700167 mce->finished = 0;
Mike Waychison76441432005-09-30 00:01:27 +0200168 wmb();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700169 for (;;) {
Paul E. McKenneyf56e8a02010-03-05 15:03:27 -0800170 entry = rcu_dereference_check_mce(mcelog.next);
Andi Kleen673242c2005-09-12 18:49:24 +0200171 for (;;) {
Ingo Molnare9eee032009-04-08 12:31:17 +0200172 /*
Mauro Carvalho Chehab696e4092009-07-23 06:57:45 -0300173 * If edac_mce is enabled, it will check the error type
174 * and will process it, if it is a known error.
175 * Otherwise, the error will be sent through mcelog
176 * interface
177 */
178 if (edac_mce_parse(mce))
179 return;
180
181 /*
Ingo Molnare9eee032009-04-08 12:31:17 +0200182 * When the buffer fills up discard new entries.
183 * Assume that the earlier errors are the more
184 * interesting ones:
185 */
Andi Kleen673242c2005-09-12 18:49:24 +0200186 if (entry >= MCE_LOG_LEN) {
Hidetoshi Seto14a02532009-04-30 16:04:51 +0900187 set_bit(MCE_OVERFLOW,
188 (unsigned long *)&mcelog.flags);
Andi Kleen673242c2005-09-12 18:49:24 +0200189 return;
190 }
Ingo Molnare9eee032009-04-08 12:31:17 +0200191 /* Old left over entry. Skip: */
Andi Kleen673242c2005-09-12 18:49:24 +0200192 if (mcelog.entry[entry].finished) {
193 entry++;
194 continue;
195 }
Mike Waychison76441432005-09-30 00:01:27 +0200196 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700197 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700198 smp_rmb();
199 next = entry + 1;
200 if (cmpxchg(&mcelog.next, entry, next) == entry)
201 break;
202 }
203 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
Mike Waychison76441432005-09-30 00:01:27 +0200204 wmb();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700205 mcelog.entry[entry].finished = 1;
Mike Waychison76441432005-09-30 00:01:27 +0200206 wmb();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700207
Andi Kleena0189c72009-05-27 21:56:54 +0200208 mce->finished = 1;
Hidetoshi Seto1020bcb2009-06-15 17:20:57 +0900209 set_bit(0, &mce_need_notify);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700210}
211
Hidetoshi Seto77e26cc2009-06-11 16:04:35 +0900212static void print_mce(struct mce *m)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700213{
Ingo Molnarf436f8b2009-10-01 16:14:32 +0200214 pr_emerg("CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
Andi Kleend620c672009-05-27 21:56:56 +0200215 m->extcpu, m->mcgstatus, m->bank, m->status);
Ingo Molnarf436f8b2009-10-01 16:14:32 +0200216
H. Peter Anvin65ea5b02008-01-30 13:30:56 +0100217 if (m->ip) {
Ingo Molnarf436f8b2009-10-01 16:14:32 +0200218 pr_emerg("RIP%s %02x:<%016Lx> ",
219 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
220 m->cs, m->ip);
221
Linus Torvalds1da177e2005-04-16 15:20:36 -0700222 if (m->cs == __KERNEL_CS)
H. Peter Anvin65ea5b02008-01-30 13:30:56 +0100223 print_symbol("{%s}", m->ip);
Ingo Molnarf436f8b2009-10-01 16:14:32 +0200224 pr_cont("\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700225 }
Borislav Petkov549d0422009-07-24 13:51:42 +0200226
Ingo Molnarf436f8b2009-10-01 16:14:32 +0200227 pr_emerg("TSC %llx ", m->tsc);
228 if (m->addr)
229 pr_cont("ADDR %llx ", m->addr);
230 if (m->misc)
231 pr_cont("MISC %llx ", m->misc);
232
233 pr_cont("\n");
234 pr_emerg("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
235 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
236
237 /*
238 * Print out human-readable details about the MCE error,
Borislav Petkovfb253192009-10-07 13:20:38 +0200239 * (if the CPU has an implementation for that)
Ingo Molnarf436f8b2009-10-01 16:14:32 +0200240 */
Borislav Petkovfb253192009-10-07 13:20:38 +0200241 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
Andi Kleen86503562009-05-27 21:56:58 +0200242}
243
Hidetoshi Seto77e26cc2009-06-11 16:04:35 +0900244static void print_mce_head(void)
245{
Ingo Molnarf436f8b2009-10-01 16:14:32 +0200246 pr_emerg("\nHARDWARE ERROR\n");
Hidetoshi Seto77e26cc2009-06-11 16:04:35 +0900247}
248
Andi Kleen86503562009-05-27 21:56:58 +0200249static void print_mce_tail(void)
250{
Ingo Molnarf436f8b2009-10-01 16:14:32 +0200251 pr_emerg("This is not a software problem!\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700252}
253
Andi Kleenf94b61c2009-05-27 21:56:55 +0200254#define PANIC_TIMEOUT 5 /* 5 seconds */
255
256static atomic_t mce_paniced;
257
Huang Yingbf783f92009-07-31 09:41:43 +0800258static int fake_panic;
259static atomic_t mce_fake_paniced;
260
Andi Kleenf94b61c2009-05-27 21:56:55 +0200261/* Panic in progress. Enable interrupts and wait for final IPI */
262static void wait_for_panic(void)
263{
264 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
Ingo Molnarf436f8b2009-10-01 16:14:32 +0200265
Andi Kleenf94b61c2009-05-27 21:56:55 +0200266 preempt_disable();
267 local_irq_enable();
268 while (timeout-- > 0)
269 udelay(1);
Andi Kleen29b0f592009-05-27 21:56:56 +0200270 if (panic_timeout == 0)
271 panic_timeout = mce_panic_timeout;
Andi Kleenf94b61c2009-05-27 21:56:55 +0200272 panic("Panicing machine check CPU died");
273}
274
Andi Kleenbd19a5e2009-05-27 21:56:55 +0200275static void mce_panic(char *msg, struct mce *final, char *exp)
Thomas Gleixnerd88203d2007-10-23 22:37:23 +0200276{
Huang Ying482908b2010-05-18 14:35:22 +0800277 int i, apei_err = 0;
Tim Hockine02e68d2007-07-21 17:10:36 +0200278
Huang Yingbf783f92009-07-31 09:41:43 +0800279 if (!fake_panic) {
280 /*
281 * Make sure only one CPU runs in machine check panic
282 */
283 if (atomic_inc_return(&mce_paniced) > 1)
284 wait_for_panic();
285 barrier();
Andi Kleenf94b61c2009-05-27 21:56:55 +0200286
Huang Yingbf783f92009-07-31 09:41:43 +0800287 bust_spinlocks(1);
288 console_verbose();
289 } else {
290 /* Don't log too much for fake panic */
291 if (atomic_inc_return(&mce_fake_paniced) > 1)
292 return;
293 }
Hidetoshi Seto77e26cc2009-06-11 16:04:35 +0900294 print_mce_head();
Andi Kleena0189c72009-05-27 21:56:54 +0200295 /* First print corrected ones that are still unlogged */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700296 for (i = 0; i < MCE_LOG_LEN; i++) {
Andi Kleena0189c72009-05-27 21:56:54 +0200297 struct mce *m = &mcelog.entry[i];
Hidetoshi Seto77e26cc2009-06-11 16:04:35 +0900298 if (!(m->status & MCI_STATUS_VAL))
299 continue;
Huang Ying482908b2010-05-18 14:35:22 +0800300 if (!(m->status & MCI_STATUS_UC)) {
Hidetoshi Seto77e26cc2009-06-11 16:04:35 +0900301 print_mce(m);
Huang Ying482908b2010-05-18 14:35:22 +0800302 if (!apei_err)
303 apei_err = apei_write_mce(m);
304 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700305 }
Andi Kleena0189c72009-05-27 21:56:54 +0200306 /* Now print uncorrected but with the final one last */
307 for (i = 0; i < MCE_LOG_LEN; i++) {
308 struct mce *m = &mcelog.entry[i];
309 if (!(m->status & MCI_STATUS_VAL))
310 continue;
Hidetoshi Seto77e26cc2009-06-11 16:04:35 +0900311 if (!(m->status & MCI_STATUS_UC))
312 continue;
Huang Ying482908b2010-05-18 14:35:22 +0800313 if (!final || memcmp(m, final, sizeof(struct mce))) {
Hidetoshi Seto77e26cc2009-06-11 16:04:35 +0900314 print_mce(m);
Huang Ying482908b2010-05-18 14:35:22 +0800315 if (!apei_err)
316 apei_err = apei_write_mce(m);
317 }
Andi Kleena0189c72009-05-27 21:56:54 +0200318 }
Huang Ying482908b2010-05-18 14:35:22 +0800319 if (final) {
Hidetoshi Seto77e26cc2009-06-11 16:04:35 +0900320 print_mce(final);
Huang Ying482908b2010-05-18 14:35:22 +0800321 if (!apei_err)
322 apei_err = apei_write_mce(final);
323 }
Andi Kleen3c079792009-05-27 21:56:55 +0200324 if (cpu_missing)
325 printk(KERN_EMERG "Some CPUs didn't answer in synchronization\n");
Andi Kleen86503562009-05-27 21:56:58 +0200326 print_mce_tail();
Andi Kleenbd19a5e2009-05-27 21:56:55 +0200327 if (exp)
328 printk(KERN_EMERG "Machine check: %s\n", exp);
Huang Yingbf783f92009-07-31 09:41:43 +0800329 if (!fake_panic) {
330 if (panic_timeout == 0)
331 panic_timeout = mce_panic_timeout;
332 panic(msg);
333 } else
334 printk(KERN_EMERG "Fake kernel panic: %s\n", msg);
Thomas Gleixnerd88203d2007-10-23 22:37:23 +0200335}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700336
Andi Kleenea149b32009-04-29 19:31:00 +0200337/* Support code for software error injection */
338
339static int msr_to_offset(u32 msr)
340{
341 unsigned bank = __get_cpu_var(injectm.bank);
Ingo Molnarf436f8b2009-10-01 16:14:32 +0200342
Andi Kleenea149b32009-04-29 19:31:00 +0200343 if (msr == rip_msr)
344 return offsetof(struct mce, ip);
Andi Kleena2d32bc2009-07-09 00:31:44 +0200345 if (msr == MSR_IA32_MCx_STATUS(bank))
Andi Kleenea149b32009-04-29 19:31:00 +0200346 return offsetof(struct mce, status);
Andi Kleena2d32bc2009-07-09 00:31:44 +0200347 if (msr == MSR_IA32_MCx_ADDR(bank))
Andi Kleenea149b32009-04-29 19:31:00 +0200348 return offsetof(struct mce, addr);
Andi Kleena2d32bc2009-07-09 00:31:44 +0200349 if (msr == MSR_IA32_MCx_MISC(bank))
Andi Kleenea149b32009-04-29 19:31:00 +0200350 return offsetof(struct mce, misc);
351 if (msr == MSR_IA32_MCG_STATUS)
352 return offsetof(struct mce, mcgstatus);
353 return -1;
354}
355
Andi Kleen5f8c1a52009-04-29 19:29:12 +0200356/* MSR access wrappers used for error injection */
357static u64 mce_rdmsrl(u32 msr)
358{
359 u64 v;
Ingo Molnar11868a22009-09-23 17:49:55 +0200360
Andi Kleenea149b32009-04-29 19:31:00 +0200361 if (__get_cpu_var(injectm).finished) {
362 int offset = msr_to_offset(msr);
Ingo Molnar11868a22009-09-23 17:49:55 +0200363
Andi Kleenea149b32009-04-29 19:31:00 +0200364 if (offset < 0)
365 return 0;
366 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
367 }
Ingo Molnar11868a22009-09-23 17:49:55 +0200368
369 if (rdmsrl_safe(msr, &v)) {
370 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
371 /*
372 * Return zero in case the access faulted. This should
373 * not happen normally but can happen if the CPU does
374 * something weird, or if the code is buggy.
375 */
376 v = 0;
377 }
378
Andi Kleen5f8c1a52009-04-29 19:29:12 +0200379 return v;
380}
381
382static void mce_wrmsrl(u32 msr, u64 v)
383{
Andi Kleenea149b32009-04-29 19:31:00 +0200384 if (__get_cpu_var(injectm).finished) {
385 int offset = msr_to_offset(msr);
Ingo Molnar11868a22009-09-23 17:49:55 +0200386
Andi Kleenea149b32009-04-29 19:31:00 +0200387 if (offset >= 0)
388 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
389 return;
390 }
Andi Kleen5f8c1a52009-04-29 19:29:12 +0200391 wrmsrl(msr, v);
392}
393
Andi Kleen9b1beaf2009-05-27 21:56:59 +0200394/*
395 * Simple lockless ring to communicate PFNs from the exception handler with the
396 * process context work function. This is vastly simplified because there's
397 * only a single reader and a single writer.
398 */
399#define MCE_RING_SIZE 16 /* we use one entry less */
400
401struct mce_ring {
402 unsigned short start;
403 unsigned short end;
404 unsigned long ring[MCE_RING_SIZE];
405};
406static DEFINE_PER_CPU(struct mce_ring, mce_ring);
407
408/* Runs with CPU affinity in workqueue */
409static int mce_ring_empty(void)
410{
411 struct mce_ring *r = &__get_cpu_var(mce_ring);
412
413 return r->start == r->end;
414}
415
416static int mce_ring_get(unsigned long *pfn)
417{
418 struct mce_ring *r;
419 int ret = 0;
420
421 *pfn = 0;
422 get_cpu();
423 r = &__get_cpu_var(mce_ring);
424 if (r->start == r->end)
425 goto out;
426 *pfn = r->ring[r->start];
427 r->start = (r->start + 1) % MCE_RING_SIZE;
428 ret = 1;
429out:
430 put_cpu();
431 return ret;
432}
433
434/* Always runs in MCE context with preempt off */
435static int mce_ring_add(unsigned long pfn)
436{
437 struct mce_ring *r = &__get_cpu_var(mce_ring);
438 unsigned next;
439
440 next = (r->end + 1) % MCE_RING_SIZE;
441 if (next == r->start)
442 return -1;
443 r->ring[r->end] = pfn;
444 wmb();
445 r->end = next;
446 return 0;
447}
448
Andi Kleen88ccbed2009-02-12 13:49:36 +0100449int mce_available(struct cpuinfo_x86 *c)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700450{
Andi Kleen04b2b1a2009-04-28 22:50:19 +0200451 if (mce_disabled)
Andi Kleen5b4408f2009-02-12 13:39:30 +0100452 return 0;
Akinobu Mita3d1712c2006-03-24 03:15:11 -0800453 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700454}
455
Andi Kleen9b1beaf2009-05-27 21:56:59 +0200456static void mce_schedule_work(void)
457{
458 if (!mce_ring_empty()) {
459 struct work_struct *work = &__get_cpu_var(mce_work);
460 if (!work_pending(work))
461 schedule_work(work);
462 }
463}
464
Huang Ying1b2797d2009-05-27 21:56:51 +0200465/*
466 * Get the address of the instruction at the time of the machine check
467 * error.
468 */
Andi Kleen94ad8472005-04-16 15:25:09 -0700469static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
470{
Huang Ying1b2797d2009-05-27 21:56:51 +0200471
472 if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) {
H. Peter Anvin65ea5b02008-01-30 13:30:56 +0100473 m->ip = regs->ip;
Andi Kleen94ad8472005-04-16 15:25:09 -0700474 m->cs = regs->cs;
475 } else {
H. Peter Anvin65ea5b02008-01-30 13:30:56 +0100476 m->ip = 0;
Andi Kleen94ad8472005-04-16 15:25:09 -0700477 m->cs = 0;
478 }
Huang Ying1b2797d2009-05-27 21:56:51 +0200479 if (rip_msr)
Andi Kleen5f8c1a52009-04-29 19:29:12 +0200480 m->ip = mce_rdmsrl(rip_msr);
Andi Kleen94ad8472005-04-16 15:25:09 -0700481}
482
Ingo Molnar11868a22009-09-23 17:49:55 +0200483#ifdef CONFIG_X86_LOCAL_APIC
Andi Kleenccc3c312009-05-27 21:56:54 +0200484/*
485 * Called after interrupts have been reenabled again
486 * when a MCE happened during an interrupts off region
487 * in the kernel.
488 */
489asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs)
490{
491 ack_APIC_irq();
492 exit_idle();
493 irq_enter();
Andi Kleen9ff36ee2009-05-27 21:56:58 +0200494 mce_notify_irq();
Andi Kleen9b1beaf2009-05-27 21:56:59 +0200495 mce_schedule_work();
Andi Kleenccc3c312009-05-27 21:56:54 +0200496 irq_exit();
497}
498#endif
499
500static void mce_report_event(struct pt_regs *regs)
501{
502 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
Andi Kleen9ff36ee2009-05-27 21:56:58 +0200503 mce_notify_irq();
Andi Kleen9b1beaf2009-05-27 21:56:59 +0200504 /*
505 * Triggering the work queue here is just an insurance
506 * policy in case the syscall exit notify handler
507 * doesn't run soon enough or ends up running on the
508 * wrong CPU (can happen when audit sleeps)
509 */
510 mce_schedule_work();
Andi Kleenccc3c312009-05-27 21:56:54 +0200511 return;
512 }
513
514#ifdef CONFIG_X86_LOCAL_APIC
515 /*
516 * Without APIC do not notify. The event will be picked
517 * up eventually.
518 */
519 if (!cpu_has_apic)
520 return;
521
522 /*
523 * When interrupts are disabled we cannot use
524 * kernel services safely. Trigger an self interrupt
525 * through the APIC to instead do the notification
526 * after interrupts are reenabled again.
527 */
528 apic->send_IPI_self(MCE_SELF_VECTOR);
529
530 /*
531 * Wait for idle afterwards again so that we don't leave the
532 * APIC in a non idle state because the normal APIC writes
533 * cannot exclude us.
534 */
535 apic_wait_icr_idle();
536#endif
537}
538
Andi Kleenca84f692009-05-27 21:56:57 +0200539DEFINE_PER_CPU(unsigned, mce_poll_count);
540
Thomas Gleixnerd88203d2007-10-23 22:37:23 +0200541/*
Andi Kleenb79109c2009-02-12 13:43:23 +0100542 * Poll for corrected events or events that happened before reset.
543 * Those are just logged through /dev/mcelog.
544 *
545 * This is executed in standard interrupt context.
Andi Kleened7290d2009-05-27 21:56:57 +0200546 *
547 * Note: spec recommends to panic for fatal unsignalled
548 * errors here. However this would be quite problematic --
549 * we would need to reimplement the Monarch handling and
550 * it would mess up the exclusion between exception handler
551 * and poll hander -- * so we skip this for now.
552 * These cases should not happen anyways, or only when the CPU
553 * is already totally * confused. In this case it's likely it will
554 * not fully execute the machine check handler either.
Andi Kleenb79109c2009-02-12 13:43:23 +0100555 */
Andi Kleenee031c32009-02-12 13:49:34 +0100556void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
Andi Kleenb79109c2009-02-12 13:43:23 +0100557{
558 struct mce m;
559 int i;
560
Jan Beulich402af0d2010-04-21 15:21:51 +0100561 percpu_inc(mce_poll_count);
Andi Kleenca84f692009-05-27 21:56:57 +0200562
Andi Kleenb79109c2009-02-12 13:43:23 +0100563 mce_setup(&m);
564
Andi Kleen5f8c1a52009-04-29 19:29:12 +0200565 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
Andi Kleenb79109c2009-02-12 13:43:23 +0100566 for (i = 0; i < banks; i++) {
Andi Kleencebe1822009-07-09 00:31:43 +0200567 if (!mce_banks[i].ctl || !test_bit(i, *b))
Andi Kleenb79109c2009-02-12 13:43:23 +0100568 continue;
569
570 m.misc = 0;
571 m.addr = 0;
572 m.bank = i;
573 m.tsc = 0;
574
575 barrier();
Andi Kleena2d32bc2009-07-09 00:31:44 +0200576 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
Andi Kleenb79109c2009-02-12 13:43:23 +0100577 if (!(m.status & MCI_STATUS_VAL))
578 continue;
579
580 /*
Andi Kleened7290d2009-05-27 21:56:57 +0200581 * Uncorrected or signalled events are handled by the exception
582 * handler when it is enabled, so don't process those here.
Andi Kleenb79109c2009-02-12 13:43:23 +0100583 *
584 * TBD do the same check for MCI_STATUS_EN here?
585 */
Andi Kleened7290d2009-05-27 21:56:57 +0200586 if (!(flags & MCP_UC) &&
587 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
Andi Kleenb79109c2009-02-12 13:43:23 +0100588 continue;
589
590 if (m.status & MCI_STATUS_MISCV)
Andi Kleena2d32bc2009-07-09 00:31:44 +0200591 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
Andi Kleenb79109c2009-02-12 13:43:23 +0100592 if (m.status & MCI_STATUS_ADDRV)
Andi Kleena2d32bc2009-07-09 00:31:44 +0200593 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
Andi Kleenb79109c2009-02-12 13:43:23 +0100594
595 if (!(flags & MCP_TIMESTAMP))
596 m.tsc = 0;
597 /*
598 * Don't get the IP here because it's unlikely to
599 * have anything to do with the actual error location.
600 */
Hidetoshi Seto62fdac52009-06-11 16:06:07 +0900601 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) {
Andi Kleen5679af42009-04-07 17:06:55 +0200602 mce_log(&m);
Borislav Petkov98a5ae22010-05-18 13:59:05 +0200603 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, &m);
Andi Kleen5679af42009-04-07 17:06:55 +0200604 add_taint(TAINT_MACHINE_CHECK);
605 }
Andi Kleenb79109c2009-02-12 13:43:23 +0100606
607 /*
608 * Clear state for this bank.
609 */
Andi Kleena2d32bc2009-07-09 00:31:44 +0200610 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
Andi Kleenb79109c2009-02-12 13:43:23 +0100611 }
612
613 /*
614 * Don't clear MCG_STATUS here because it's only defined for
615 * exceptions.
616 */
Andi Kleen88921be2009-05-27 21:56:51 +0200617
618 sync_core();
Andi Kleenb79109c2009-02-12 13:43:23 +0100619}
Andi Kleenea149b32009-04-29 19:31:00 +0200620EXPORT_SYMBOL_GPL(machine_check_poll);
Andi Kleenb79109c2009-02-12 13:43:23 +0100621
622/*
Andi Kleenbd19a5e2009-05-27 21:56:55 +0200623 * Do a quick check if any of the events requires a panic.
624 * This decides if we keep the events around or clear them.
625 */
626static int mce_no_way_out(struct mce *m, char **msg)
627{
628 int i;
629
630 for (i = 0; i < banks; i++) {
Andi Kleena2d32bc2009-07-09 00:31:44 +0200631 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
Andi Kleenbd19a5e2009-05-27 21:56:55 +0200632 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
633 return 1;
634 }
635 return 0;
636}
637
638/*
Andi Kleen3c079792009-05-27 21:56:55 +0200639 * Variable to establish order between CPUs while scanning.
640 * Each CPU spins initially until executing is equal its number.
641 */
642static atomic_t mce_executing;
643
644/*
645 * Defines order of CPUs on entry. First CPU becomes Monarch.
646 */
647static atomic_t mce_callin;
648
649/*
650 * Check if a timeout waiting for other CPUs happened.
651 */
652static int mce_timed_out(u64 *t)
653{
654 /*
655 * The others already did panic for some reason.
656 * Bail out like in a timeout.
657 * rmb() to tell the compiler that system_state
658 * might have been modified by someone else.
659 */
660 rmb();
661 if (atomic_read(&mce_paniced))
662 wait_for_panic();
663 if (!monarch_timeout)
664 goto out;
665 if ((s64)*t < SPINUNIT) {
666 /* CHECKME: Make panic default for 1 too? */
667 if (tolerant < 1)
668 mce_panic("Timeout synchronizing machine check over CPUs",
669 NULL, NULL);
670 cpu_missing = 1;
671 return 1;
672 }
673 *t -= SPINUNIT;
674out:
675 touch_nmi_watchdog();
676 return 0;
677}
678
679/*
680 * The Monarch's reign. The Monarch is the CPU who entered
681 * the machine check handler first. It waits for the others to
682 * raise the exception too and then grades them. When any
683 * error is fatal panic. Only then let the others continue.
684 *
685 * The other CPUs entering the MCE handler will be controlled by the
686 * Monarch. They are called Subjects.
687 *
688 * This way we prevent any potential data corruption in a unrecoverable case
689 * and also makes sure always all CPU's errors are examined.
690 *
Hidetoshi Seto680b6cf2009-08-26 16:20:36 +0900691 * Also this detects the case of a machine check event coming from outer
Andi Kleen3c079792009-05-27 21:56:55 +0200692 * space (not detected by any CPUs) In this case some external agent wants
693 * us to shut down, so panic too.
694 *
695 * The other CPUs might still decide to panic if the handler happens
696 * in a unrecoverable place, but in this case the system is in a semi-stable
697 * state and won't corrupt anything by itself. It's ok to let the others
698 * continue for a bit first.
699 *
700 * All the spin loops have timeouts; when a timeout happens a CPU
701 * typically elects itself to be Monarch.
702 */
703static void mce_reign(void)
704{
705 int cpu;
706 struct mce *m = NULL;
707 int global_worst = 0;
708 char *msg = NULL;
709 char *nmsg = NULL;
710
711 /*
712 * This CPU is the Monarch and the other CPUs have run
713 * through their handlers.
714 * Grade the severity of the errors of all the CPUs.
715 */
716 for_each_possible_cpu(cpu) {
717 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
718 &nmsg);
719 if (severity > global_worst) {
720 msg = nmsg;
721 global_worst = severity;
722 m = &per_cpu(mces_seen, cpu);
723 }
724 }
725
726 /*
727 * Cannot recover? Panic here then.
728 * This dumps all the mces in the log buffer and stops the
729 * other CPUs.
730 */
731 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
Andi Kleenac960372009-05-27 21:56:58 +0200732 mce_panic("Fatal Machine check", m, msg);
Andi Kleen3c079792009-05-27 21:56:55 +0200733
734 /*
735 * For UC somewhere we let the CPU who detects it handle it.
736 * Also must let continue the others, otherwise the handling
737 * CPU could deadlock on a lock.
738 */
739
740 /*
741 * No machine check event found. Must be some external
742 * source or one CPU is hung. Panic.
743 */
Hidetoshi Seto680b6cf2009-08-26 16:20:36 +0900744 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
Andi Kleen3c079792009-05-27 21:56:55 +0200745 mce_panic("Machine check from unknown source", NULL, NULL);
746
747 /*
748 * Now clear all the mces_seen so that they don't reappear on
749 * the next mce.
750 */
751 for_each_possible_cpu(cpu)
752 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
753}
754
755static atomic_t global_nwo;
756
757/*
758 * Start of Monarch synchronization. This waits until all CPUs have
759 * entered the exception handler and then determines if any of them
760 * saw a fatal event that requires panic. Then it executes them
761 * in the entry order.
762 * TBD double check parallel CPU hotunplug
763 */
Hidetoshi Seto7fb06fc2009-06-15 18:18:43 +0900764static int mce_start(int *no_way_out)
Andi Kleen3c079792009-05-27 21:56:55 +0200765{
Hidetoshi Seto7fb06fc2009-06-15 18:18:43 +0900766 int order;
Andi Kleen3c079792009-05-27 21:56:55 +0200767 int cpus = num_online_cpus();
768 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
769
Hidetoshi Seto7fb06fc2009-06-15 18:18:43 +0900770 if (!timeout)
771 return -1;
Andi Kleen3c079792009-05-27 21:56:55 +0200772
Hidetoshi Seto7fb06fc2009-06-15 18:18:43 +0900773 atomic_add(*no_way_out, &global_nwo);
Huang Ying184e1fd2009-06-15 15:37:07 +0800774 /*
775 * global_nwo should be updated before mce_callin
776 */
777 smp_wmb();
Borislav Petkova95436e2009-06-20 23:28:22 -0700778 order = atomic_inc_return(&mce_callin);
Andi Kleen3c079792009-05-27 21:56:55 +0200779
780 /*
781 * Wait for everyone.
782 */
783 while (atomic_read(&mce_callin) != cpus) {
784 if (mce_timed_out(&timeout)) {
785 atomic_set(&global_nwo, 0);
Hidetoshi Seto7fb06fc2009-06-15 18:18:43 +0900786 return -1;
Andi Kleen3c079792009-05-27 21:56:55 +0200787 }
788 ndelay(SPINUNIT);
789 }
790
791 /*
Huang Ying184e1fd2009-06-15 15:37:07 +0800792 * mce_callin should be read before global_nwo
793 */
794 smp_rmb();
Hidetoshi Seto7fb06fc2009-06-15 18:18:43 +0900795
796 if (order == 1) {
797 /*
798 * Monarch: Starts executing now, the others wait.
799 */
800 atomic_set(&mce_executing, 1);
801 } else {
802 /*
803 * Subject: Now start the scanning loop one by one in
804 * the original callin order.
805 * This way when there are any shared banks it will be
806 * only seen by one CPU before cleared, avoiding duplicates.
807 */
808 while (atomic_read(&mce_executing) < order) {
809 if (mce_timed_out(&timeout)) {
810 atomic_set(&global_nwo, 0);
811 return -1;
812 }
813 ndelay(SPINUNIT);
814 }
815 }
816
Huang Ying184e1fd2009-06-15 15:37:07 +0800817 /*
Andi Kleen3c079792009-05-27 21:56:55 +0200818 * Cache the global no_way_out state.
819 */
Hidetoshi Seto7fb06fc2009-06-15 18:18:43 +0900820 *no_way_out = atomic_read(&global_nwo);
Andi Kleen3c079792009-05-27 21:56:55 +0200821
Hidetoshi Seto7fb06fc2009-06-15 18:18:43 +0900822 return order;
Andi Kleen3c079792009-05-27 21:56:55 +0200823}
824
825/*
826 * Synchronize between CPUs after main scanning loop.
827 * This invokes the bulk of the Monarch processing.
828 */
829static int mce_end(int order)
830{
831 int ret = -1;
832 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
833
834 if (!timeout)
835 goto reset;
836 if (order < 0)
837 goto reset;
838
839 /*
840 * Allow others to run.
841 */
842 atomic_inc(&mce_executing);
843
844 if (order == 1) {
845 /* CHECKME: Can this race with a parallel hotplug? */
846 int cpus = num_online_cpus();
847
848 /*
849 * Monarch: Wait for everyone to go through their scanning
850 * loops.
851 */
852 while (atomic_read(&mce_executing) <= cpus) {
853 if (mce_timed_out(&timeout))
854 goto reset;
855 ndelay(SPINUNIT);
856 }
857
858 mce_reign();
859 barrier();
860 ret = 0;
861 } else {
862 /*
863 * Subject: Wait for Monarch to finish.
864 */
865 while (atomic_read(&mce_executing) != 0) {
866 if (mce_timed_out(&timeout))
867 goto reset;
868 ndelay(SPINUNIT);
869 }
870
871 /*
872 * Don't reset anything. That's done by the Monarch.
873 */
874 return 0;
875 }
876
877 /*
878 * Reset all global state.
879 */
880reset:
881 atomic_set(&global_nwo, 0);
882 atomic_set(&mce_callin, 0);
883 barrier();
884
885 /*
886 * Let others run again.
887 */
888 atomic_set(&mce_executing, 0);
889 return ret;
890}
891
Andi Kleen9b1beaf2009-05-27 21:56:59 +0200892/*
893 * Check if the address reported by the CPU is in a format we can parse.
894 * It would be possible to add code for most other cases, but all would
895 * be somewhat complicated (e.g. segment offset would require an instruction
896 * parser). So only support physical addresses upto page granuality for now.
897 */
898static int mce_usable_address(struct mce *m)
899{
900 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
901 return 0;
902 if ((m->misc & 0x3f) > PAGE_SHIFT)
903 return 0;
904 if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS)
905 return 0;
906 return 1;
907}
908
Andi Kleen3c079792009-05-27 21:56:55 +0200909static void mce_clear_state(unsigned long *toclear)
910{
911 int i;
912
913 for (i = 0; i < banks; i++) {
914 if (test_bit(i, toclear))
Andi Kleena2d32bc2009-07-09 00:31:44 +0200915 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
Andi Kleen3c079792009-05-27 21:56:55 +0200916 }
917}
918
919/*
Andi Kleenb79109c2009-02-12 13:43:23 +0100920 * The actual machine check handler. This only handles real
921 * exceptions when something got corrupted coming in through int 18.
922 *
923 * This is executed in NMI context not subject to normal locking rules. This
924 * implies that most kernel services cannot be safely used. Don't even
925 * think about putting a printk in there!
Andi Kleen3c079792009-05-27 21:56:55 +0200926 *
927 * On Intel systems this is entered on all CPUs in parallel through
928 * MCE broadcast. However some CPUs might be broken beyond repair,
929 * so be always careful when synchronizing with others.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700930 */
Ingo Molnare9eee032009-04-08 12:31:17 +0200931void do_machine_check(struct pt_regs *regs, long error_code)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700932{
Andi Kleen3c079792009-05-27 21:56:55 +0200933 struct mce m, *final;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700934 int i;
Andi Kleen3c079792009-05-27 21:56:55 +0200935 int worst = 0;
936 int severity;
937 /*
938 * Establish sequential order between the CPUs entering the machine
939 * check handler.
940 */
Hidetoshi Seto7fb06fc2009-06-15 18:18:43 +0900941 int order;
Tim Hockinbd784322007-07-21 17:10:37 +0200942 /*
943 * If no_way_out gets set, there is no safe way to recover from this
944 * MCE. If tolerant is cranked up, we'll try anyway.
945 */
946 int no_way_out = 0;
947 /*
948 * If kill_it gets set, there might be a way to recover from this
949 * error.
950 */
951 int kill_it = 0;
Andi Kleenb79109c2009-02-12 13:43:23 +0100952 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
Andi Kleenbd19a5e2009-05-27 21:56:55 +0200953 char *msg = "Unknown";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700954
Andi Kleen553f2652006-04-07 19:49:57 +0200955 atomic_inc(&mce_entry);
956
Jan Beulich402af0d2010-04-21 15:21:51 +0100957 percpu_inc(mce_exception_count);
Andi Kleen01ca79f2009-05-27 21:56:52 +0200958
Andi Kleenb79109c2009-02-12 13:43:23 +0100959 if (notify_die(DIE_NMI, "machine check", regs, error_code,
Jan Beulich22f59912008-01-30 13:31:23 +0100960 18, SIGKILL) == NOTIFY_STOP)
Andi Kleen32561692009-05-27 21:56:53 +0200961 goto out;
Andi Kleenb79109c2009-02-12 13:43:23 +0100962 if (!banks)
Andi Kleen32561692009-05-27 21:56:53 +0200963 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700964
Andi Kleenb5f2fa42009-02-12 13:43:22 +0100965 mce_setup(&m);
966
Andi Kleen5f8c1a52009-04-29 19:29:12 +0200967 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
Andi Kleen3c079792009-05-27 21:56:55 +0200968 final = &__get_cpu_var(mces_seen);
969 *final = m;
970
Hidetoshi Seto680b6cf2009-08-26 16:20:36 +0900971 no_way_out = mce_no_way_out(&m, &msg);
972
Linus Torvalds1da177e2005-04-16 15:20:36 -0700973 barrier();
974
Andi Kleen3c079792009-05-27 21:56:55 +0200975 /*
Andi Kleened7290d2009-05-27 21:56:57 +0200976 * When no restart IP must always kill or panic.
977 */
978 if (!(m.mcgstatus & MCG_STATUS_RIPV))
979 kill_it = 1;
980
981 /*
Andi Kleen3c079792009-05-27 21:56:55 +0200982 * Go through all the banks in exclusion of the other CPUs.
983 * This way we don't report duplicated events on shared banks
984 * because the first one to see it will clear it.
985 */
Hidetoshi Seto7fb06fc2009-06-15 18:18:43 +0900986 order = mce_start(&no_way_out);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700987 for (i = 0; i < banks; i++) {
Andi Kleenb79109c2009-02-12 13:43:23 +0100988 __clear_bit(i, toclear);
Andi Kleencebe1822009-07-09 00:31:43 +0200989 if (!mce_banks[i].ctl)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700990 continue;
Thomas Gleixnerd88203d2007-10-23 22:37:23 +0200991
992 m.misc = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700993 m.addr = 0;
994 m.bank = i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700995
Andi Kleena2d32bc2009-07-09 00:31:44 +0200996 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700997 if ((m.status & MCI_STATUS_VAL) == 0)
998 continue;
999
Andi Kleenb79109c2009-02-12 13:43:23 +01001000 /*
Andi Kleened7290d2009-05-27 21:56:57 +02001001 * Non uncorrected or non signaled errors are handled by
1002 * machine_check_poll. Leave them alone, unless this panics.
Andi Kleenb79109c2009-02-12 13:43:23 +01001003 */
Andi Kleened7290d2009-05-27 21:56:57 +02001004 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1005 !no_way_out)
Andi Kleenb79109c2009-02-12 13:43:23 +01001006 continue;
1007
1008 /*
1009 * Set taint even when machine check was not enabled.
1010 */
1011 add_taint(TAINT_MACHINE_CHECK);
1012
Andi Kleened7290d2009-05-27 21:56:57 +02001013 severity = mce_severity(&m, tolerant, NULL);
Andi Kleenb79109c2009-02-12 13:43:23 +01001014
Andi Kleened7290d2009-05-27 21:56:57 +02001015 /*
1016 * When machine check was for corrected handler don't touch,
1017 * unless we're panicing.
1018 */
1019 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
1020 continue;
1021 __set_bit(i, toclear);
1022 if (severity == MCE_NO_SEVERITY) {
Andi Kleenb79109c2009-02-12 13:43:23 +01001023 /*
1024 * Machine check event was not enabled. Clear, but
1025 * ignore.
1026 */
1027 continue;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001028 }
1029
Andi Kleened7290d2009-05-27 21:56:57 +02001030 /*
1031 * Kill on action required.
1032 */
1033 if (severity == MCE_AR_SEVERITY)
1034 kill_it = 1;
1035
Linus Torvalds1da177e2005-04-16 15:20:36 -07001036 if (m.status & MCI_STATUS_MISCV)
Andi Kleena2d32bc2009-07-09 00:31:44 +02001037 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001038 if (m.status & MCI_STATUS_ADDRV)
Andi Kleena2d32bc2009-07-09 00:31:44 +02001039 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001040
Andi Kleen9b1beaf2009-05-27 21:56:59 +02001041 /*
1042 * Action optional error. Queue address for later processing.
1043 * When the ring overflows we just ignore the AO error.
1044 * RED-PEN add some logging mechanism when
1045 * usable_address or mce_add_ring fails.
1046 * RED-PEN don't ignore overflow for tolerant == 0
1047 */
1048 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
1049 mce_ring_add(m.addr >> PAGE_SHIFT);
1050
Andi Kleen94ad8472005-04-16 15:25:09 -07001051 mce_get_rip(&m, regs);
Andi Kleenb79109c2009-02-12 13:43:23 +01001052 mce_log(&m);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001053
Andi Kleen3c079792009-05-27 21:56:55 +02001054 if (severity > worst) {
1055 *final = m;
1056 worst = severity;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001057 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001058 }
1059
Andi Kleen3c079792009-05-27 21:56:55 +02001060 if (!no_way_out)
1061 mce_clear_state(toclear);
1062
Ingo Molnare9eee032009-04-08 12:31:17 +02001063 /*
Andi Kleen3c079792009-05-27 21:56:55 +02001064 * Do most of the synchronization with other CPUs.
1065 * When there's any problem use only local no_way_out state.
Ingo Molnare9eee032009-04-08 12:31:17 +02001066 */
Andi Kleen3c079792009-05-27 21:56:55 +02001067 if (mce_end(order) < 0)
1068 no_way_out = worst >= MCE_PANIC_SEVERITY;
Tim Hockinbd784322007-07-21 17:10:37 +02001069
1070 /*
1071 * If we have decided that we just CAN'T continue, and the user
Ingo Molnare9eee032009-04-08 12:31:17 +02001072 * has not set tolerant to an insane level, give up and die.
Andi Kleen3c079792009-05-27 21:56:55 +02001073 *
1074 * This is mainly used in the case when the system doesn't
1075 * support MCE broadcasting or it has been disabled.
Tim Hockinbd784322007-07-21 17:10:37 +02001076 */
1077 if (no_way_out && tolerant < 3)
Andi Kleenac960372009-05-27 21:56:58 +02001078 mce_panic("Fatal machine check on current CPU", final, msg);
Tim Hockinbd784322007-07-21 17:10:37 +02001079
1080 /*
1081 * If the error seems to be unrecoverable, something should be
1082 * done. Try to kill as little as possible. If we can kill just
1083 * one task, do that. If the user has set the tolerance very
1084 * high, don't try to do anything at all.
1085 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001086
Andi Kleened7290d2009-05-27 21:56:57 +02001087 if (kill_it && tolerant < 3)
1088 force_sig(SIGBUS, current);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001089
Tim Hockine02e68d2007-07-21 17:10:36 +02001090 /* notify userspace ASAP */
1091 set_thread_flag(TIF_MCE_NOTIFY);
1092
Andi Kleen3c079792009-05-27 21:56:55 +02001093 if (worst > 0)
1094 mce_report_event(regs);
Andi Kleen5f8c1a52009-04-29 19:29:12 +02001095 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
Andi Kleen32561692009-05-27 21:56:53 +02001096out:
Andi Kleen553f2652006-04-07 19:49:57 +02001097 atomic_dec(&mce_entry);
Andi Kleen88921be2009-05-27 21:56:51 +02001098 sync_core();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001099}
Andi Kleenea149b32009-04-29 19:31:00 +02001100EXPORT_SYMBOL_GPL(do_machine_check);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001101
Andi Kleen9b1beaf2009-05-27 21:56:59 +02001102/* dummy to break dependency. actual code is in mm/memory-failure.c */
1103void __attribute__((weak)) memory_failure(unsigned long pfn, int vector)
1104{
1105 printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn);
1106}
1107
1108/*
1109 * Called after mce notification in process context. This code
1110 * is allowed to sleep. Call the high level VM handler to process
1111 * any corrupted pages.
1112 * Assume that the work queue code only calls this one at a time
1113 * per CPU.
1114 * Note we don't disable preemption, so this code might run on the wrong
1115 * CPU. In this case the event is picked up by the scheduled work queue.
1116 * This is merely a fast path to expedite processing in some common
1117 * cases.
1118 */
1119void mce_notify_process(void)
1120{
1121 unsigned long pfn;
1122 mce_notify_irq();
1123 while (mce_ring_get(&pfn))
1124 memory_failure(pfn, MCE_VECTOR);
1125}
1126
1127static void mce_process_work(struct work_struct *dummy)
1128{
1129 mce_notify_process();
1130}
1131
Dmitriy Zavin15d5f832006-09-26 10:52:42 +02001132#ifdef CONFIG_X86_MCE_INTEL
1133/***
1134 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
Simon Arlott676b1852007-10-20 01:25:36 +02001135 * @cpu: The CPU on which the event occurred.
Dmitriy Zavin15d5f832006-09-26 10:52:42 +02001136 * @status: Event status information
1137 *
1138 * This function should be called by the thermal interrupt after the
1139 * event has been processed and the decision was made to log the event
1140 * further.
1141 *
1142 * The status parameter will be saved to the 'status' field of 'struct mce'
1143 * and historically has been the register value of the
1144 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1145 */
Andi Kleenb5f2fa42009-02-12 13:43:22 +01001146void mce_log_therm_throt_event(__u64 status)
Dmitriy Zavin15d5f832006-09-26 10:52:42 +02001147{
1148 struct mce m;
1149
Andi Kleenb5f2fa42009-02-12 13:43:22 +01001150 mce_setup(&m);
Dmitriy Zavin15d5f832006-09-26 10:52:42 +02001151 m.bank = MCE_THERMAL_BANK;
1152 m.status = status;
Dmitriy Zavin15d5f832006-09-26 10:52:42 +02001153 mce_log(&m);
1154}
1155#endif /* CONFIG_X86_MCE_INTEL */
1156
Linus Torvalds1da177e2005-04-16 15:20:36 -07001157/*
Tim Hockin8a336b02007-05-02 19:27:19 +02001158 * Periodic polling timer for "silent" machine check errors. If the
1159 * poller finds an MCE, poll 2x faster. When the poller finds no more
1160 * errors, poll 2x slower (up to check_interval seconds).
Linus Torvalds1da177e2005-04-16 15:20:36 -07001161 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001162static int check_interval = 5 * 60; /* 5 minutes */
Ingo Molnare9eee032009-04-08 12:31:17 +02001163
Tejun Heo245b2e72009-06-24 15:13:48 +09001164static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */
Andi Kleen52d168e2009-02-12 13:39:29 +01001165static DEFINE_PER_CPU(struct timer_list, mce_timer);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001166
Borislav Petkov5e099542009-10-16 12:31:32 +02001167static void mce_start_timer(unsigned long data)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001168{
Andi Kleen52d168e2009-02-12 13:39:29 +01001169 struct timer_list *t = &per_cpu(mce_timer, data);
Andi Kleen6298c512009-04-09 12:28:22 +02001170 int *n;
Andi Kleen52d168e2009-02-12 13:39:29 +01001171
1172 WARN_ON(smp_processor_id() != data);
1173
Ingo Molnare9eee032009-04-08 12:31:17 +02001174 if (mce_available(&current_cpu_data)) {
Andi Kleenee031c32009-02-12 13:49:34 +01001175 machine_check_poll(MCP_TIMESTAMP,
1176 &__get_cpu_var(mce_poll_banks));
Ingo Molnare9eee032009-04-08 12:31:17 +02001177 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001178
1179 /*
Tim Hockine02e68d2007-07-21 17:10:36 +02001180 * Alert userspace if needed. If we logged an MCE, reduce the
1181 * polling interval, otherwise increase the polling interval.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001182 */
Tejun Heo245b2e72009-06-24 15:13:48 +09001183 n = &__get_cpu_var(mce_next_interval);
Andi Kleen9ff36ee2009-05-27 21:56:58 +02001184 if (mce_notify_irq())
Andi Kleen6298c512009-04-09 12:28:22 +02001185 *n = max(*n/2, HZ/100);
Hidetoshi Seto14a02532009-04-30 16:04:51 +09001186 else
Andi Kleen6298c512009-04-09 12:28:22 +02001187 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
Tim Hockin8a336b02007-05-02 19:27:19 +02001188
Andi Kleen6298c512009-04-09 12:28:22 +02001189 t->expires = jiffies + *n;
Hidetoshi Seto5be60662009-06-24 09:21:10 +09001190 add_timer_on(t, smp_processor_id());
Linus Torvalds1da177e2005-04-16 15:20:36 -07001191}
1192
Andi Kleen9bd98402009-02-12 13:39:28 +01001193static void mce_do_trigger(struct work_struct *work)
1194{
Hidetoshi Seto1020bcb2009-06-15 17:20:57 +09001195 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
Andi Kleen9bd98402009-02-12 13:39:28 +01001196}
1197
1198static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1199
Tim Hockine02e68d2007-07-21 17:10:36 +02001200/*
Andi Kleen9bd98402009-02-12 13:39:28 +01001201 * Notify the user(s) about new machine check events.
1202 * Can be called from interrupt context, but not from machine check/NMI
1203 * context.
Tim Hockine02e68d2007-07-21 17:10:36 +02001204 */
Andi Kleen9ff36ee2009-05-27 21:56:58 +02001205int mce_notify_irq(void)
Tim Hockine02e68d2007-07-21 17:10:36 +02001206{
Andi Kleen8457c842009-02-12 13:49:33 +01001207 /* Not more than two messages every minute */
1208 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1209
Tim Hockine02e68d2007-07-21 17:10:36 +02001210 clear_thread_flag(TIF_MCE_NOTIFY);
Ingo Molnare9eee032009-04-08 12:31:17 +02001211
Hidetoshi Seto1020bcb2009-06-15 17:20:57 +09001212 if (test_and_clear_bit(0, &mce_need_notify)) {
Tim Hockine02e68d2007-07-21 17:10:36 +02001213 wake_up_interruptible(&mce_wait);
Andi Kleen9bd98402009-02-12 13:39:28 +01001214
1215 /*
1216 * There is no risk of missing notifications because
1217 * work_pending is always cleared before the function is
1218 * executed.
1219 */
Hidetoshi Seto1020bcb2009-06-15 17:20:57 +09001220 if (mce_helper[0] && !work_pending(&mce_trigger_work))
Andi Kleen9bd98402009-02-12 13:39:28 +01001221 schedule_work(&mce_trigger_work);
Tim Hockine02e68d2007-07-21 17:10:36 +02001222
Andi Kleen8457c842009-02-12 13:49:33 +01001223 if (__ratelimit(&ratelimit))
Tim Hockine02e68d2007-07-21 17:10:36 +02001224 printk(KERN_INFO "Machine check events logged\n");
Tim Hockine02e68d2007-07-21 17:10:36 +02001225
1226 return 1;
1227 }
1228 return 0;
1229}
Andi Kleen9ff36ee2009-05-27 21:56:58 +02001230EXPORT_SYMBOL_GPL(mce_notify_irq);
Tim Hockine02e68d2007-07-21 17:10:36 +02001231
Hidetoshi Setocffd3772009-11-12 15:52:40 +09001232static int __cpuinit __mcheck_cpu_mce_banks_init(void)
Andi Kleencebe1822009-07-09 00:31:43 +02001233{
1234 int i;
1235
1236 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1237 if (!mce_banks)
1238 return -ENOMEM;
1239 for (i = 0; i < banks; i++) {
1240 struct mce_bank *b = &mce_banks[i];
Ingo Molnar11868a22009-09-23 17:49:55 +02001241
Andi Kleencebe1822009-07-09 00:31:43 +02001242 b->ctl = -1ULL;
1243 b->init = 1;
1244 }
1245 return 0;
1246}
1247
Thomas Gleixnerd88203d2007-10-23 22:37:23 +02001248/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001249 * Initialize Machine Checks for a CPU.
1250 */
Borislav Petkov5e099542009-10-16 12:31:32 +02001251static int __cpuinit __mcheck_cpu_cap_init(void)
Andi Kleen0d7482e2009-02-17 23:07:13 +01001252{
Andi Kleen0d7482e2009-02-17 23:07:13 +01001253 unsigned b;
Ingo Molnare9eee032009-04-08 12:31:17 +02001254 u64 cap;
Andi Kleen0d7482e2009-02-17 23:07:13 +01001255
1256 rdmsrl(MSR_IA32_MCG_CAP, cap);
Thomas Gleixner01c66802009-04-08 12:31:24 +02001257
1258 b = cap & MCG_BANKCNT_MASK;
Roland Dreier93ae5012009-10-15 14:21:14 -07001259 if (!banks)
1260 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
Ingo Molnarb6592942009-04-08 12:31:27 +02001261
Andi Kleen0d7482e2009-02-17 23:07:13 +01001262 if (b > MAX_NR_BANKS) {
1263 printk(KERN_WARNING
1264 "MCE: Using only %u machine check banks out of %u\n",
1265 MAX_NR_BANKS, b);
1266 b = MAX_NR_BANKS;
1267 }
1268
1269 /* Don't support asymmetric configurations today */
1270 WARN_ON(banks != 0 && b != banks);
1271 banks = b;
Andi Kleencebe1822009-07-09 00:31:43 +02001272 if (!mce_banks) {
Hidetoshi Setocffd3772009-11-12 15:52:40 +09001273 int err = __mcheck_cpu_mce_banks_init();
Ingo Molnar11868a22009-09-23 17:49:55 +02001274
Andi Kleencebe1822009-07-09 00:31:43 +02001275 if (err)
1276 return err;
Andi Kleen0d7482e2009-02-17 23:07:13 +01001277 }
1278
1279 /* Use accurate RIP reporting if available. */
Thomas Gleixner01c66802009-04-08 12:31:24 +02001280 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
Andi Kleen0d7482e2009-02-17 23:07:13 +01001281 rip_msr = MSR_IA32_MCG_EIP;
1282
Andi Kleened7290d2009-05-27 21:56:57 +02001283 if (cap & MCG_SER_P)
1284 mce_ser = 1;
1285
Andi Kleen0d7482e2009-02-17 23:07:13 +01001286 return 0;
1287}
1288
Borislav Petkov5e099542009-10-16 12:31:32 +02001289static void __mcheck_cpu_init_generic(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001290{
Ingo Molnare9eee032009-04-08 12:31:17 +02001291 mce_banks_t all_banks;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001292 u64 cap;
1293 int i;
1294
Andi Kleenb79109c2009-02-12 13:43:23 +01001295 /*
1296 * Log the machine checks left over from the previous reset.
1297 */
Andi Kleenee031c32009-02-12 13:49:34 +01001298 bitmap_fill(all_banks, MAX_NR_BANKS);
Andi Kleen5679af42009-04-07 17:06:55 +02001299 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001300
1301 set_in_cr4(X86_CR4_MCE);
1302
Andi Kleen0d7482e2009-02-17 23:07:13 +01001303 rdmsrl(MSR_IA32_MCG_CAP, cap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001304 if (cap & MCG_CTL_P)
1305 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1306
1307 for (i = 0; i < banks; i++) {
Andi Kleencebe1822009-07-09 00:31:43 +02001308 struct mce_bank *b = &mce_banks[i];
Ingo Molnar11868a22009-09-23 17:49:55 +02001309
Andi Kleencebe1822009-07-09 00:31:43 +02001310 if (!b->init)
Andi Kleen06b7a7a2009-04-27 18:37:43 +02001311 continue;
Andi Kleena2d32bc2009-07-09 00:31:44 +02001312 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1313 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
Thomas Gleixnerd88203d2007-10-23 22:37:23 +02001314 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001315}
1316
1317/* Add per CPU specific workarounds here */
Borislav Petkov5e099542009-10-16 12:31:32 +02001318static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
Thomas Gleixnerd88203d2007-10-23 22:37:23 +02001319{
Ingo Molnare412cd22009-08-17 10:19:00 +02001320 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1321 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1322 return -EOPNOTSUPP;
1323 }
1324
Linus Torvalds1da177e2005-04-16 15:20:36 -07001325 /* This should be disabled by the BIOS, but isn't always */
Jan Beulich911f6a72008-04-22 16:22:21 +01001326 if (c->x86_vendor == X86_VENDOR_AMD) {
Ingo Molnare9eee032009-04-08 12:31:17 +02001327 if (c->x86 == 15 && banks > 4) {
1328 /*
1329 * disable GART TBL walk error reporting, which
1330 * trips off incorrectly with the IOMMU & 3ware
1331 * & Cerberus:
1332 */
Andi Kleencebe1822009-07-09 00:31:43 +02001333 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
Ingo Molnare9eee032009-04-08 12:31:17 +02001334 }
1335 if (c->x86 <= 17 && mce_bootlog < 0) {
1336 /*
1337 * Lots of broken BIOS around that don't clear them
1338 * by default and leave crap in there. Don't log:
1339 */
Jan Beulich911f6a72008-04-22 16:22:21 +01001340 mce_bootlog = 0;
Ingo Molnare9eee032009-04-08 12:31:17 +02001341 }
Andi Kleen2e6f6942009-04-27 18:42:48 +02001342 /*
1343 * Various K7s with broken bank 0 around. Always disable
1344 * by default.
1345 */
Andi Kleen203abd62009-06-15 14:52:01 +02001346 if (c->x86 == 6 && banks > 0)
Andi Kleencebe1822009-07-09 00:31:43 +02001347 mce_banks[0].ctl = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001348 }
Andi Kleene5835382005-11-05 17:25:54 +01001349
Andi Kleen06b7a7a2009-04-27 18:37:43 +02001350 if (c->x86_vendor == X86_VENDOR_INTEL) {
1351 /*
1352 * SDM documents that on family 6 bank 0 should not be written
1353 * because it aliases to another special BIOS controlled
1354 * register.
1355 * But it's not aliased anymore on model 0x1a+
1356 * Don't ignore bank 0 completely because there could be a
1357 * valid event later, merely don't write CTL0.
1358 */
1359
Andi Kleencebe1822009-07-09 00:31:43 +02001360 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1361 mce_banks[0].init = 0;
Andi Kleen3c079792009-05-27 21:56:55 +02001362
1363 /*
1364 * All newer Intel systems support MCE broadcasting. Enable
1365 * synchronization with a one second timeout.
1366 */
1367 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1368 monarch_timeout < 0)
1369 monarch_timeout = USEC_PER_SEC;
Bartlomiej Zolnierkiewiczc7f6fa42009-07-28 23:52:54 +02001370
Ingo Molnare412cd22009-08-17 10:19:00 +02001371 /*
1372 * There are also broken BIOSes on some Pentium M and
1373 * earlier systems:
1374 */
1375 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
Bartlomiej Zolnierkiewiczc7f6fa42009-07-28 23:52:54 +02001376 mce_bootlog = 0;
Andi Kleen06b7a7a2009-04-27 18:37:43 +02001377 }
Andi Kleen3c079792009-05-27 21:56:55 +02001378 if (monarch_timeout < 0)
1379 monarch_timeout = 0;
Andi Kleen29b0f592009-05-27 21:56:56 +02001380 if (mce_bootlog != 0)
1381 mce_panic_timeout = 30;
Ingo Molnare412cd22009-08-17 10:19:00 +02001382
1383 return 0;
Thomas Gleixnerd88203d2007-10-23 22:37:23 +02001384}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001385
Borislav Petkov5e099542009-10-16 12:31:32 +02001386static void __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
Andi Kleen4efc0672009-04-28 19:07:31 +02001387{
1388 if (c->x86 != 5)
1389 return;
1390 switch (c->x86_vendor) {
1391 case X86_VENDOR_INTEL:
Hidetoshi Setoc6978362009-06-15 17:22:49 +09001392 intel_p5_mcheck_init(c);
Andi Kleen4efc0672009-04-28 19:07:31 +02001393 break;
1394 case X86_VENDOR_CENTAUR:
1395 winchip_mcheck_init(c);
1396 break;
1397 }
1398}
1399
Borislav Petkov5e099542009-10-16 12:31:32 +02001400static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001401{
1402 switch (c->x86_vendor) {
1403 case X86_VENDOR_INTEL:
1404 mce_intel_feature_init(c);
1405 break;
Jacob Shin89b831e2005-11-05 17:25:53 +01001406 case X86_VENDOR_AMD:
1407 mce_amd_feature_init(c);
1408 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001409 default:
1410 break;
1411 }
1412}
1413
Borislav Petkov5e099542009-10-16 12:31:32 +02001414static void __mcheck_cpu_init_timer(void)
Andi Kleen52d168e2009-02-12 13:39:29 +01001415{
1416 struct timer_list *t = &__get_cpu_var(mce_timer);
Tejun Heo245b2e72009-06-24 15:13:48 +09001417 int *n = &__get_cpu_var(mce_next_interval);
Andi Kleen52d168e2009-02-12 13:39:29 +01001418
Jan Beulichbc09eff2009-12-08 11:21:37 +09001419 setup_timer(t, mce_start_timer, smp_processor_id());
1420
Hidetoshi Seto62fdac52009-06-11 16:06:07 +09001421 if (mce_ignore_ce)
1422 return;
1423
Andi Kleen6298c512009-04-09 12:28:22 +02001424 *n = check_interval * HZ;
1425 if (!*n)
Andi Kleen52d168e2009-02-12 13:39:29 +01001426 return;
Andi Kleen6298c512009-04-09 12:28:22 +02001427 t->expires = round_jiffies(jiffies + *n);
Hidetoshi Seto5be60662009-06-24 09:21:10 +09001428 add_timer_on(t, smp_processor_id());
Andi Kleen52d168e2009-02-12 13:39:29 +01001429}
1430
Andi Kleen9eda8cb2009-07-09 00:31:42 +02001431/* Handle unconfigured int18 (should never happen) */
1432static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1433{
1434 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
1435 smp_processor_id());
1436}
1437
1438/* Call the installed machine check handler for this CPU setup. */
1439void (*machine_check_vector)(struct pt_regs *, long error_code) =
1440 unexpected_machine_check;
1441
Thomas Gleixnerd88203d2007-10-23 22:37:23 +02001442/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001443 * Called for each booted CPU to set up machine checks.
Ingo Molnare9eee032009-04-08 12:31:17 +02001444 * Must be called with preempt off:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001445 */
Borislav Petkov5e099542009-10-16 12:31:32 +02001446void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001447{
Andi Kleen4efc0672009-04-28 19:07:31 +02001448 if (mce_disabled)
1449 return;
1450
Borislav Petkov5e099542009-10-16 12:31:32 +02001451 __mcheck_cpu_ancient_init(c);
Andi Kleen4efc0672009-04-28 19:07:31 +02001452
Andi Kleen5b4408f2009-02-12 13:39:30 +01001453 if (!mce_available(c))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001454 return;
1455
Borislav Petkov5e099542009-10-16 12:31:32 +02001456 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
Andi Kleen04b2b1a2009-04-28 22:50:19 +02001457 mce_disabled = 1;
Andi Kleen0d7482e2009-02-17 23:07:13 +01001458 return;
1459 }
Andi Kleen0d7482e2009-02-17 23:07:13 +01001460
Andi Kleen5d727922009-04-27 19:25:48 +02001461 machine_check_vector = do_machine_check;
1462
Borislav Petkov5e099542009-10-16 12:31:32 +02001463 __mcheck_cpu_init_generic();
1464 __mcheck_cpu_init_vendor(c);
1465 __mcheck_cpu_init_timer();
Andi Kleen9b1beaf2009-05-27 21:56:59 +02001466 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
Borislav Petkovfb253192009-10-07 13:20:38 +02001467
Linus Torvalds1da177e2005-04-16 15:20:36 -07001468}
1469
1470/*
1471 * Character device to read and clear the MCE log.
1472 */
1473
Tim Hockinf528e7b2007-07-21 17:10:35 +02001474static DEFINE_SPINLOCK(mce_state_lock);
Ingo Molnare9eee032009-04-08 12:31:17 +02001475static int open_count; /* #times opened */
1476static int open_exclu; /* already open exclusive? */
Tim Hockinf528e7b2007-07-21 17:10:35 +02001477
1478static int mce_open(struct inode *inode, struct file *file)
1479{
1480 spin_lock(&mce_state_lock);
1481
1482 if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
1483 spin_unlock(&mce_state_lock);
Ingo Molnare9eee032009-04-08 12:31:17 +02001484
Tim Hockinf528e7b2007-07-21 17:10:35 +02001485 return -EBUSY;
1486 }
1487
1488 if (file->f_flags & O_EXCL)
1489 open_exclu = 1;
1490 open_count++;
1491
1492 spin_unlock(&mce_state_lock);
1493
Tim Hockinbd784322007-07-21 17:10:37 +02001494 return nonseekable_open(inode, file);
Tim Hockinf528e7b2007-07-21 17:10:35 +02001495}
1496
1497static int mce_release(struct inode *inode, struct file *file)
1498{
1499 spin_lock(&mce_state_lock);
1500
1501 open_count--;
1502 open_exclu = 0;
1503
1504 spin_unlock(&mce_state_lock);
1505
1506 return 0;
1507}
1508
Thomas Gleixnerd88203d2007-10-23 22:37:23 +02001509static void collect_tscs(void *data)
1510{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001511 unsigned long *cpu_tsc = (unsigned long *)data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001512
Thomas Gleixnerd88203d2007-10-23 22:37:23 +02001513 rdtscll(cpu_tsc[smp_processor_id()]);
1514}
1515
Huang Ying482908b2010-05-18 14:35:22 +08001516static int mce_apei_read_done;
1517
1518/* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1519static int __mce_read_apei(char __user **ubuf, size_t usize)
1520{
1521 int rc;
1522 u64 record_id;
1523 struct mce m;
1524
1525 if (usize < sizeof(struct mce))
1526 return -EINVAL;
1527
1528 rc = apei_read_mce(&m, &record_id);
1529 /* Error or no more MCE record */
1530 if (rc <= 0) {
1531 mce_apei_read_done = 1;
1532 return rc;
1533 }
1534 rc = -EFAULT;
1535 if (copy_to_user(*ubuf, &m, sizeof(struct mce)))
1536 return rc;
1537 /*
1538 * In fact, we should have cleared the record after that has
1539 * been flushed to the disk or sent to network in
1540 * /sbin/mcelog, but we have no interface to support that now,
1541 * so just clear it to avoid duplication.
1542 */
1543 rc = apei_clear_mce(record_id);
1544 if (rc) {
1545 mce_apei_read_done = 1;
1546 return rc;
1547 }
1548 *ubuf += sizeof(struct mce);
1549
1550 return 0;
1551}
1552
Thomas Gleixnerd88203d2007-10-23 22:37:23 +02001553static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
1554 loff_t *off)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001555{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001556 char __user *buf = ubuf;
Ingo Molnare9eee032009-04-08 12:31:17 +02001557 unsigned long *cpu_tsc;
1558 unsigned prev, next;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001559 int i, err;
1560
Mike Travis6bca67f2008-07-18 18:11:27 -07001561 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
Andi Kleenf0de53b2005-04-16 15:25:10 -07001562 if (!cpu_tsc)
1563 return -ENOMEM;
1564
Daniel Walker8c8b8852008-01-30 13:31:17 +01001565 mutex_lock(&mce_read_mutex);
Huang Ying482908b2010-05-18 14:35:22 +08001566
1567 if (!mce_apei_read_done) {
1568 err = __mce_read_apei(&buf, usize);
1569 if (err || buf != ubuf)
1570 goto out;
1571 }
1572
Paul E. McKenneyf56e8a02010-03-05 15:03:27 -08001573 next = rcu_dereference_check_mce(mcelog.next);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001574
1575 /* Only supports full reads right now */
Huang Ying482908b2010-05-18 14:35:22 +08001576 err = -EINVAL;
1577 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce))
1578 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001579
1580 err = 0;
Huang Yingef41df4342009-02-12 13:39:34 +01001581 prev = 0;
1582 do {
1583 for (i = prev; i < next; i++) {
1584 unsigned long start = jiffies;
Thomas Gleixnerd88203d2007-10-23 22:37:23 +02001585
Huang Yingef41df4342009-02-12 13:39:34 +01001586 while (!mcelog.entry[i].finished) {
1587 if (time_after_eq(jiffies, start + 2)) {
1588 memset(mcelog.entry + i, 0,
1589 sizeof(struct mce));
1590 goto timeout;
1591 }
1592 cpu_relax();
Andi Kleen673242c2005-09-12 18:49:24 +02001593 }
Huang Yingef41df4342009-02-12 13:39:34 +01001594 smp_rmb();
1595 err |= copy_to_user(buf, mcelog.entry + i,
1596 sizeof(struct mce));
1597 buf += sizeof(struct mce);
1598timeout:
1599 ;
Andi Kleen673242c2005-09-12 18:49:24 +02001600 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001601
Huang Yingef41df4342009-02-12 13:39:34 +01001602 memset(mcelog.entry + prev, 0,
1603 (next - prev) * sizeof(struct mce));
1604 prev = next;
1605 next = cmpxchg(&mcelog.next, prev, 0);
1606 } while (next != prev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001607
Paul E. McKenneyb2b18662005-06-25 14:55:38 -07001608 synchronize_sched();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001609
Thomas Gleixnerd88203d2007-10-23 22:37:23 +02001610 /*
1611 * Collect entries that were still getting written before the
1612 * synchronize.
1613 */
Jens Axboe15c8b6c2008-05-09 09:39:44 +02001614 on_each_cpu(collect_tscs, cpu_tsc, 1);
Ingo Molnare9eee032009-04-08 12:31:17 +02001615
Thomas Gleixnerd88203d2007-10-23 22:37:23 +02001616 for (i = next; i < MCE_LOG_LEN; i++) {
1617 if (mcelog.entry[i].finished &&
1618 mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
1619 err |= copy_to_user(buf, mcelog.entry+i,
1620 sizeof(struct mce));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001621 smp_rmb();
1622 buf += sizeof(struct mce);
1623 memset(&mcelog.entry[i], 0, sizeof(struct mce));
1624 }
Thomas Gleixnerd88203d2007-10-23 22:37:23 +02001625 }
Huang Ying482908b2010-05-18 14:35:22 +08001626
1627 if (err)
1628 err = -EFAULT;
1629
1630out:
Daniel Walker8c8b8852008-01-30 13:31:17 +01001631 mutex_unlock(&mce_read_mutex);
Andi Kleenf0de53b2005-04-16 15:25:10 -07001632 kfree(cpu_tsc);
Ingo Molnare9eee032009-04-08 12:31:17 +02001633
Huang Ying482908b2010-05-18 14:35:22 +08001634 return err ? err : buf - ubuf;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001635}
1636
Tim Hockine02e68d2007-07-21 17:10:36 +02001637static unsigned int mce_poll(struct file *file, poll_table *wait)
1638{
1639 poll_wait(file, &mce_wait, wait);
Paul E. McKenneyf56e8a02010-03-05 15:03:27 -08001640 if (rcu_dereference_check_mce(mcelog.next))
Tim Hockine02e68d2007-07-21 17:10:36 +02001641 return POLLIN | POLLRDNORM;
Huang Ying482908b2010-05-18 14:35:22 +08001642 if (!mce_apei_read_done && apei_check_mce())
1643 return POLLIN | POLLRDNORM;
Tim Hockine02e68d2007-07-21 17:10:36 +02001644 return 0;
1645}
1646
Nikanth Karthikesanc68461b2008-01-30 13:32:59 +01001647static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001648{
1649 int __user *p = (int __user *)arg;
Thomas Gleixnerd88203d2007-10-23 22:37:23 +02001650
Linus Torvalds1da177e2005-04-16 15:20:36 -07001651 if (!capable(CAP_SYS_ADMIN))
Thomas Gleixnerd88203d2007-10-23 22:37:23 +02001652 return -EPERM;
Ingo Molnare9eee032009-04-08 12:31:17 +02001653
Linus Torvalds1da177e2005-04-16 15:20:36 -07001654 switch (cmd) {
Thomas Gleixnerd88203d2007-10-23 22:37:23 +02001655 case MCE_GET_RECORD_LEN:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001656 return put_user(sizeof(struct mce), p);
1657 case MCE_GET_LOG_LEN:
Thomas Gleixnerd88203d2007-10-23 22:37:23 +02001658 return put_user(MCE_LOG_LEN, p);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001659 case MCE_GETCLEAR_FLAGS: {
1660 unsigned flags;
Thomas Gleixnerd88203d2007-10-23 22:37:23 +02001661
1662 do {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001663 flags = mcelog.flags;
Thomas Gleixnerd88203d2007-10-23 22:37:23 +02001664 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
Ingo Molnare9eee032009-04-08 12:31:17 +02001665
Thomas Gleixnerd88203d2007-10-23 22:37:23 +02001666 return put_user(flags, p);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001667 }
1668 default:
Thomas Gleixnerd88203d2007-10-23 22:37:23 +02001669 return -ENOTTY;
1670 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001671}
1672
H. Peter Anvina1ff41b2009-05-25 22:16:14 -07001673/* Modified in mce-inject.c, so not static or const */
Andi Kleenea149b32009-04-29 19:31:00 +02001674struct file_operations mce_chrdev_ops = {
Ingo Molnare9eee032009-04-08 12:31:17 +02001675 .open = mce_open,
1676 .release = mce_release,
1677 .read = mce_read,
1678 .poll = mce_poll,
1679 .unlocked_ioctl = mce_ioctl,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001680};
Andi Kleenea149b32009-04-29 19:31:00 +02001681EXPORT_SYMBOL_GPL(mce_chrdev_ops);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001682
1683static struct miscdevice mce_log_device = {
1684 MISC_MCELOG_MINOR,
1685 "mcelog",
1686 &mce_chrdev_ops,
1687};
1688
Thomas Gleixnerd88203d2007-10-23 22:37:23 +02001689/*
Hidetoshi Seto62fdac52009-06-11 16:06:07 +09001690 * mce=off Disables machine check
1691 * mce=no_cmci Disables CMCI
1692 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1693 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
Andi Kleen3c079792009-05-27 21:56:55 +02001694 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1695 * monarchtimeout is how long to wait for other CPUs on machine
1696 * check, or 0 to not wait
Hidetoshi Seto13503fa2009-03-26 17:39:20 +09001697 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1698 * mce=nobootlog Don't log MCEs from before booting.
1699 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001700static int __init mcheck_enable(char *str)
1701{
Bartlomiej Zolnierkiewicze3346fc2009-07-28 23:55:09 +02001702 if (*str == 0) {
Andi Kleen4efc0672009-04-28 19:07:31 +02001703 enable_p5_mce();
Bartlomiej Zolnierkiewicze3346fc2009-07-28 23:55:09 +02001704 return 1;
1705 }
Andi Kleen4efc0672009-04-28 19:07:31 +02001706 if (*str == '=')
1707 str++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001708 if (!strcmp(str, "off"))
Andi Kleen04b2b1a2009-04-28 22:50:19 +02001709 mce_disabled = 1;
Hidetoshi Seto62fdac52009-06-11 16:06:07 +09001710 else if (!strcmp(str, "no_cmci"))
1711 mce_cmci_disabled = 1;
1712 else if (!strcmp(str, "dont_log_ce"))
1713 mce_dont_log_ce = 1;
1714 else if (!strcmp(str, "ignore_ce"))
1715 mce_ignore_ce = 1;
Hidetoshi Seto13503fa2009-03-26 17:39:20 +09001716 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1717 mce_bootlog = (str[0] == 'b');
Andi Kleen3c079792009-05-27 21:56:55 +02001718 else if (isdigit(str[0])) {
Andi Kleen8c566ef2005-09-12 18:49:24 +02001719 get_option(&str, &tolerant);
Andi Kleen3c079792009-05-27 21:56:55 +02001720 if (*str == ',') {
1721 ++str;
1722 get_option(&str, &monarch_timeout);
1723 }
1724 } else {
Andi Kleen4efc0672009-04-28 19:07:31 +02001725 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
Hidetoshi Seto13503fa2009-03-26 17:39:20 +09001726 str);
1727 return 0;
1728 }
OGAWA Hirofumi9b410462006-03-31 02:30:33 -08001729 return 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001730}
Andi Kleen4efc0672009-04-28 19:07:31 +02001731__setup("mce", mcheck_enable);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001732
Yong Wanga2202aa2009-11-10 09:38:24 +08001733int __init mcheck_init(void)
Borislav Petkovb33a6362009-10-16 12:31:33 +02001734{
1735 atomic_notifier_chain_register(&x86_mce_decoder_chain, &mce_dec_nb);
1736
Yong Wanga2202aa2009-11-10 09:38:24 +08001737 mcheck_intel_therm_init();
1738
Borislav Petkovb33a6362009-10-16 12:31:33 +02001739 return 0;
1740}
Borislav Petkovb33a6362009-10-16 12:31:33 +02001741
Thomas Gleixnerd88203d2007-10-23 22:37:23 +02001742/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001743 * Sysfs support
Thomas Gleixnerd88203d2007-10-23 22:37:23 +02001744 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001745
Andi Kleen973a2dd2009-02-12 13:39:32 +01001746/*
1747 * Disable machine checks on suspend and shutdown. We can't really handle
1748 * them later.
1749 */
Borislav Petkov5e099542009-10-16 12:31:32 +02001750static int mce_disable_error_reporting(void)
Andi Kleen973a2dd2009-02-12 13:39:32 +01001751{
1752 int i;
1753
Andi Kleen06b7a7a2009-04-27 18:37:43 +02001754 for (i = 0; i < banks; i++) {
Andi Kleencebe1822009-07-09 00:31:43 +02001755 struct mce_bank *b = &mce_banks[i];
Ingo Molnar11868a22009-09-23 17:49:55 +02001756
Andi Kleencebe1822009-07-09 00:31:43 +02001757 if (b->init)
Andi Kleena2d32bc2009-07-09 00:31:44 +02001758 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
Andi Kleen06b7a7a2009-04-27 18:37:43 +02001759 }
Andi Kleen973a2dd2009-02-12 13:39:32 +01001760 return 0;
1761}
1762
1763static int mce_suspend(struct sys_device *dev, pm_message_t state)
1764{
Borislav Petkov5e099542009-10-16 12:31:32 +02001765 return mce_disable_error_reporting();
Andi Kleen973a2dd2009-02-12 13:39:32 +01001766}
1767
1768static int mce_shutdown(struct sys_device *dev)
1769{
Borislav Petkov5e099542009-10-16 12:31:32 +02001770 return mce_disable_error_reporting();
Andi Kleen973a2dd2009-02-12 13:39:32 +01001771}
1772
Ingo Molnare9eee032009-04-08 12:31:17 +02001773/*
1774 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1775 * Only one CPU is active at this time, the others get re-added later using
1776 * CPU hotplug:
1777 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001778static int mce_resume(struct sys_device *dev)
1779{
Borislav Petkov5e099542009-10-16 12:31:32 +02001780 __mcheck_cpu_init_generic();
1781 __mcheck_cpu_init_vendor(&current_cpu_data);
Ingo Molnare9eee032009-04-08 12:31:17 +02001782
Linus Torvalds1da177e2005-04-16 15:20:36 -07001783 return 0;
1784}
1785
Andi Kleen52d168e2009-02-12 13:39:29 +01001786static void mce_cpu_restart(void *data)
1787{
1788 del_timer_sync(&__get_cpu_var(mce_timer));
Hidetoshi Seto33edbf02009-06-15 17:18:45 +09001789 if (!mce_available(&current_cpu_data))
1790 return;
Borislav Petkov5e099542009-10-16 12:31:32 +02001791 __mcheck_cpu_init_generic();
1792 __mcheck_cpu_init_timer();
Andi Kleen52d168e2009-02-12 13:39:29 +01001793}
1794
Linus Torvalds1da177e2005-04-16 15:20:36 -07001795/* Reinit MCEs after user configuration changes */
Thomas Gleixnerd88203d2007-10-23 22:37:23 +02001796static void mce_restart(void)
1797{
Andi Kleen52d168e2009-02-12 13:39:29 +01001798 on_each_cpu(mce_cpu_restart, NULL, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001799}
1800
Hidetoshi Seto9af43b52009-06-15 17:21:36 +09001801/* Toggle features for corrected errors */
1802static void mce_disable_ce(void *all)
1803{
1804 if (!mce_available(&current_cpu_data))
1805 return;
1806 if (all)
1807 del_timer_sync(&__get_cpu_var(mce_timer));
1808 cmci_clear();
1809}
1810
1811static void mce_enable_ce(void *all)
1812{
1813 if (!mce_available(&current_cpu_data))
1814 return;
1815 cmci_reenable();
1816 cmci_recheck();
1817 if (all)
Borislav Petkov5e099542009-10-16 12:31:32 +02001818 __mcheck_cpu_init_timer();
Hidetoshi Seto9af43b52009-06-15 17:21:36 +09001819}
1820
Linus Torvalds1da177e2005-04-16 15:20:36 -07001821static struct sysdev_class mce_sysclass = {
Ingo Molnare9eee032009-04-08 12:31:17 +02001822 .suspend = mce_suspend,
1823 .shutdown = mce_shutdown,
1824 .resume = mce_resume,
1825 .name = "machinecheck",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001826};
1827
Ingo Molnarcb491fc2009-04-08 12:31:17 +02001828DEFINE_PER_CPU(struct sys_device, mce_dev);
Ingo Molnare9eee032009-04-08 12:31:17 +02001829
1830__cpuinitdata
1831void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001832
Andi Kleencebe1822009-07-09 00:31:43 +02001833static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr)
1834{
1835 return container_of(attr, struct mce_bank, attr);
1836}
Andi Kleen0d7482e2009-02-17 23:07:13 +01001837
1838static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1839 char *buf)
1840{
Andi Kleencebe1822009-07-09 00:31:43 +02001841 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
Andi Kleen0d7482e2009-02-17 23:07:13 +01001842}
1843
1844static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
Hidetoshi Seto9319cec2009-04-14 17:26:30 +09001845 const char *buf, size_t size)
Andi Kleen0d7482e2009-02-17 23:07:13 +01001846{
Hidetoshi Seto9319cec2009-04-14 17:26:30 +09001847 u64 new;
Ingo Molnare9eee032009-04-08 12:31:17 +02001848
Hidetoshi Seto9319cec2009-04-14 17:26:30 +09001849 if (strict_strtoull(buf, 0, &new) < 0)
Andi Kleen0d7482e2009-02-17 23:07:13 +01001850 return -EINVAL;
Ingo Molnare9eee032009-04-08 12:31:17 +02001851
Andi Kleencebe1822009-07-09 00:31:43 +02001852 attr_to_bank(attr)->ctl = new;
Andi Kleen0d7482e2009-02-17 23:07:13 +01001853 mce_restart();
Ingo Molnare9eee032009-04-08 12:31:17 +02001854
Hidetoshi Seto9319cec2009-04-14 17:26:30 +09001855 return size;
Andi Kleen0d7482e2009-02-17 23:07:13 +01001856}
Andi Kleena98f0dd2007-02-13 13:26:23 +01001857
Ingo Molnare9eee032009-04-08 12:31:17 +02001858static ssize_t
1859show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
Andi Kleena98f0dd2007-02-13 13:26:23 +01001860{
Hidetoshi Seto1020bcb2009-06-15 17:20:57 +09001861 strcpy(buf, mce_helper);
Andi Kleena98f0dd2007-02-13 13:26:23 +01001862 strcat(buf, "\n");
Hidetoshi Seto1020bcb2009-06-15 17:20:57 +09001863 return strlen(mce_helper) + 1;
Andi Kleena98f0dd2007-02-13 13:26:23 +01001864}
1865
Andi Kleen4a0b2b42008-07-01 18:48:41 +02001866static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
Ingo Molnare9eee032009-04-08 12:31:17 +02001867 const char *buf, size_t siz)
Andi Kleena98f0dd2007-02-13 13:26:23 +01001868{
1869 char *p;
Ingo Molnare9eee032009-04-08 12:31:17 +02001870
Hidetoshi Seto1020bcb2009-06-15 17:20:57 +09001871 strncpy(mce_helper, buf, sizeof(mce_helper));
1872 mce_helper[sizeof(mce_helper)-1] = 0;
Hidetoshi Seto1020bcb2009-06-15 17:20:57 +09001873 p = strchr(mce_helper, '\n');
Ingo Molnare9eee032009-04-08 12:31:17 +02001874
Jan Beuliche9084ec2009-07-16 09:45:11 +01001875 if (p)
Ingo Molnare9eee032009-04-08 12:31:17 +02001876 *p = 0;
1877
Jan Beuliche9084ec2009-07-16 09:45:11 +01001878 return strlen(mce_helper) + !!p;
Andi Kleena98f0dd2007-02-13 13:26:23 +01001879}
1880
Hidetoshi Seto9af43b52009-06-15 17:21:36 +09001881static ssize_t set_ignore_ce(struct sys_device *s,
1882 struct sysdev_attribute *attr,
1883 const char *buf, size_t size)
1884{
1885 u64 new;
1886
1887 if (strict_strtoull(buf, 0, &new) < 0)
1888 return -EINVAL;
1889
1890 if (mce_ignore_ce ^ !!new) {
1891 if (new) {
1892 /* disable ce features */
1893 on_each_cpu(mce_disable_ce, (void *)1, 1);
1894 mce_ignore_ce = 1;
1895 } else {
1896 /* enable ce features */
1897 mce_ignore_ce = 0;
1898 on_each_cpu(mce_enable_ce, (void *)1, 1);
1899 }
1900 }
1901 return size;
1902}
1903
1904static ssize_t set_cmci_disabled(struct sys_device *s,
1905 struct sysdev_attribute *attr,
1906 const char *buf, size_t size)
1907{
1908 u64 new;
1909
1910 if (strict_strtoull(buf, 0, &new) < 0)
1911 return -EINVAL;
1912
1913 if (mce_cmci_disabled ^ !!new) {
1914 if (new) {
1915 /* disable cmci */
1916 on_each_cpu(mce_disable_ce, NULL, 1);
1917 mce_cmci_disabled = 1;
1918 } else {
1919 /* enable cmci */
1920 mce_cmci_disabled = 0;
1921 on_each_cpu(mce_enable_ce, NULL, 1);
1922 }
1923 }
1924 return size;
1925}
1926
Andi Kleenb56f6422009-05-27 21:56:52 +02001927static ssize_t store_int_with_restart(struct sys_device *s,
1928 struct sysdev_attribute *attr,
1929 const char *buf, size_t size)
1930{
1931 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1932 mce_restart();
1933 return ret;
1934}
1935
Andi Kleena98f0dd2007-02-13 13:26:23 +01001936static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
Andi Kleend95d62c2008-07-01 18:48:43 +02001937static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
Andi Kleen3c079792009-05-27 21:56:55 +02001938static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
Hidetoshi Seto9af43b52009-06-15 17:21:36 +09001939static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
Ingo Molnare9eee032009-04-08 12:31:17 +02001940
Andi Kleenb56f6422009-05-27 21:56:52 +02001941static struct sysdev_ext_attribute attr_check_interval = {
1942 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1943 store_int_with_restart),
1944 &check_interval
1945};
Ingo Molnare9eee032009-04-08 12:31:17 +02001946
Hidetoshi Seto9af43b52009-06-15 17:21:36 +09001947static struct sysdev_ext_attribute attr_ignore_ce = {
1948 _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce),
1949 &mce_ignore_ce
1950};
1951
1952static struct sysdev_ext_attribute attr_cmci_disabled = {
Yinghai Lu74b602c2009-06-17 14:43:32 -07001953 _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled),
Hidetoshi Seto9af43b52009-06-15 17:21:36 +09001954 &mce_cmci_disabled
1955};
1956
Ingo Molnarcb491fc2009-04-08 12:31:17 +02001957static struct sysdev_attribute *mce_attrs[] = {
Hidetoshi Seto9af43b52009-06-15 17:21:36 +09001958 &attr_tolerant.attr,
1959 &attr_check_interval.attr,
1960 &attr_trigger,
Andi Kleen3c079792009-05-27 21:56:55 +02001961 &attr_monarch_timeout.attr,
Hidetoshi Seto9af43b52009-06-15 17:21:36 +09001962 &attr_dont_log_ce.attr,
1963 &attr_ignore_ce.attr,
1964 &attr_cmci_disabled.attr,
Andi Kleena98f0dd2007-02-13 13:26:23 +01001965 NULL
1966};
Linus Torvalds1da177e2005-04-16 15:20:36 -07001967
Ingo Molnarcb491fc2009-04-08 12:31:17 +02001968static cpumask_var_t mce_dev_initialized;
Andreas Herrmannbae19fe2007-11-14 17:00:44 -08001969
Ingo Molnare9eee032009-04-08 12:31:17 +02001970/* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
Andi Kleen91c6d402005-07-28 21:15:39 -07001971static __cpuinit int mce_create_device(unsigned int cpu)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001972{
1973 int err;
Hidetoshi Setob1f49f92009-06-18 14:53:24 +09001974 int i, j;
Mike Travis92cb7612007-10-19 20:35:04 +02001975
Andreas Herrmann90367552007-11-07 02:12:58 +01001976 if (!mce_available(&boot_cpu_data))
Andi Kleen91c6d402005-07-28 21:15:39 -07001977 return -EIO;
1978
Ingo Molnarcb491fc2009-04-08 12:31:17 +02001979 memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject));
1980 per_cpu(mce_dev, cpu).id = cpu;
1981 per_cpu(mce_dev, cpu).cls = &mce_sysclass;
Andi Kleen91c6d402005-07-28 21:15:39 -07001982
Ingo Molnarcb491fc2009-04-08 12:31:17 +02001983 err = sysdev_register(&per_cpu(mce_dev, cpu));
Akinobu Mitad435d862007-10-18 03:05:15 -07001984 if (err)
1985 return err;
Andi Kleen91c6d402005-07-28 21:15:39 -07001986
Ingo Molnarcb491fc2009-04-08 12:31:17 +02001987 for (i = 0; mce_attrs[i]; i++) {
1988 err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
Akinobu Mitad435d862007-10-18 03:05:15 -07001989 if (err)
1990 goto error;
Andi Kleen91c6d402005-07-28 21:15:39 -07001991 }
Hidetoshi Setob1f49f92009-06-18 14:53:24 +09001992 for (j = 0; j < banks; j++) {
Ingo Molnarcb491fc2009-04-08 12:31:17 +02001993 err = sysdev_create_file(&per_cpu(mce_dev, cpu),
Andi Kleencebe1822009-07-09 00:31:43 +02001994 &mce_banks[j].attr);
Andi Kleen0d7482e2009-02-17 23:07:13 +01001995 if (err)
1996 goto error2;
1997 }
Ingo Molnarcb491fc2009-04-08 12:31:17 +02001998 cpumask_set_cpu(cpu, mce_dev_initialized);
Akinobu Mitad435d862007-10-18 03:05:15 -07001999
2000 return 0;
Andi Kleen0d7482e2009-02-17 23:07:13 +01002001error2:
Hidetoshi Setob1f49f92009-06-18 14:53:24 +09002002 while (--j >= 0)
Andi Kleencebe1822009-07-09 00:31:43 +02002003 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr);
Akinobu Mitad435d862007-10-18 03:05:15 -07002004error:
Ingo Molnarcb491fc2009-04-08 12:31:17 +02002005 while (--i >= 0)
Hidetoshi Seto5c0e9f22009-12-08 16:52:44 +09002006 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
Ingo Molnarcb491fc2009-04-08 12:31:17 +02002007
2008 sysdev_unregister(&per_cpu(mce_dev, cpu));
Akinobu Mitad435d862007-10-18 03:05:15 -07002009
Andi Kleen91c6d402005-07-28 21:15:39 -07002010 return err;
2011}
2012
Jan Beulich2d9cd6c2008-08-29 13:15:04 +01002013static __cpuinit void mce_remove_device(unsigned int cpu)
Andi Kleen91c6d402005-07-28 21:15:39 -07002014{
Shaohua Li73ca5352006-01-11 22:43:06 +01002015 int i;
2016
Ingo Molnarcb491fc2009-04-08 12:31:17 +02002017 if (!cpumask_test_cpu(cpu, mce_dev_initialized))
Andreas Herrmannbae19fe2007-11-14 17:00:44 -08002018 return;
2019
Ingo Molnarcb491fc2009-04-08 12:31:17 +02002020 for (i = 0; mce_attrs[i]; i++)
2021 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
2022
Andi Kleen0d7482e2009-02-17 23:07:13 +01002023 for (i = 0; i < banks; i++)
Andi Kleencebe1822009-07-09 00:31:43 +02002024 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr);
Ingo Molnarcb491fc2009-04-08 12:31:17 +02002025
2026 sysdev_unregister(&per_cpu(mce_dev, cpu));
2027 cpumask_clear_cpu(cpu, mce_dev_initialized);
Andi Kleen91c6d402005-07-28 21:15:39 -07002028}
Andi Kleen91c6d402005-07-28 21:15:39 -07002029
Andi Kleend6b75582009-02-12 13:39:31 +01002030/* Make sure there are no machine checks on offlined CPUs. */
Hidetoshi Seto767df1b2009-11-26 17:29:02 +09002031static void __cpuinit mce_disable_cpu(void *h)
Andi Kleend6b75582009-02-12 13:39:31 +01002032{
Andi Kleen88ccbed2009-02-12 13:49:36 +01002033 unsigned long action = *(unsigned long *)h;
Ingo Molnarcb491fc2009-04-08 12:31:17 +02002034 int i;
Andi Kleend6b75582009-02-12 13:39:31 +01002035
2036 if (!mce_available(&current_cpu_data))
2037 return;
Hidetoshi Seto767df1b2009-11-26 17:29:02 +09002038
Andi Kleen88ccbed2009-02-12 13:49:36 +01002039 if (!(action & CPU_TASKS_FROZEN))
2040 cmci_clear();
Andi Kleen06b7a7a2009-04-27 18:37:43 +02002041 for (i = 0; i < banks; i++) {
Andi Kleencebe1822009-07-09 00:31:43 +02002042 struct mce_bank *b = &mce_banks[i];
Ingo Molnar11868a22009-09-23 17:49:55 +02002043
Andi Kleencebe1822009-07-09 00:31:43 +02002044 if (b->init)
Andi Kleena2d32bc2009-07-09 00:31:44 +02002045 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
Andi Kleen06b7a7a2009-04-27 18:37:43 +02002046 }
Andi Kleend6b75582009-02-12 13:39:31 +01002047}
2048
Hidetoshi Seto767df1b2009-11-26 17:29:02 +09002049static void __cpuinit mce_reenable_cpu(void *h)
Andi Kleend6b75582009-02-12 13:39:31 +01002050{
Andi Kleen88ccbed2009-02-12 13:49:36 +01002051 unsigned long action = *(unsigned long *)h;
Ingo Molnare9eee032009-04-08 12:31:17 +02002052 int i;
Andi Kleend6b75582009-02-12 13:39:31 +01002053
2054 if (!mce_available(&current_cpu_data))
2055 return;
Ingo Molnare9eee032009-04-08 12:31:17 +02002056
Andi Kleen88ccbed2009-02-12 13:49:36 +01002057 if (!(action & CPU_TASKS_FROZEN))
2058 cmci_reenable();
Andi Kleen06b7a7a2009-04-27 18:37:43 +02002059 for (i = 0; i < banks; i++) {
Andi Kleencebe1822009-07-09 00:31:43 +02002060 struct mce_bank *b = &mce_banks[i];
Ingo Molnar11868a22009-09-23 17:49:55 +02002061
Andi Kleencebe1822009-07-09 00:31:43 +02002062 if (b->init)
Andi Kleena2d32bc2009-07-09 00:31:44 +02002063 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
Andi Kleen06b7a7a2009-04-27 18:37:43 +02002064 }
Andi Kleend6b75582009-02-12 13:39:31 +01002065}
2066
Andi Kleen91c6d402005-07-28 21:15:39 -07002067/* Get notified when a cpu comes on/off. Be hotplug friendly. */
Ingo Molnare9eee032009-04-08 12:31:17 +02002068static int __cpuinit
2069mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
Andi Kleen91c6d402005-07-28 21:15:39 -07002070{
2071 unsigned int cpu = (unsigned long)hcpu;
Andi Kleen52d168e2009-02-12 13:39:29 +01002072 struct timer_list *t = &per_cpu(mce_timer, cpu);
Andi Kleen91c6d402005-07-28 21:15:39 -07002073
2074 switch (action) {
Andreas Herrmannbae19fe2007-11-14 17:00:44 -08002075 case CPU_ONLINE:
2076 case CPU_ONLINE_FROZEN:
2077 mce_create_device(cpu);
Rafael J. Wysocki87357282008-08-22 22:23:09 +02002078 if (threshold_cpu_callback)
2079 threshold_cpu_callback(action, cpu);
Andi Kleen91c6d402005-07-28 21:15:39 -07002080 break;
Andi Kleen91c6d402005-07-28 21:15:39 -07002081 case CPU_DEAD:
Rafael J. Wysocki8bb78442007-05-09 02:35:10 -07002082 case CPU_DEAD_FROZEN:
Rafael J. Wysocki87357282008-08-22 22:23:09 +02002083 if (threshold_cpu_callback)
2084 threshold_cpu_callback(action, cpu);
Andi Kleen91c6d402005-07-28 21:15:39 -07002085 mce_remove_device(cpu);
2086 break;
Andi Kleen52d168e2009-02-12 13:39:29 +01002087 case CPU_DOWN_PREPARE:
2088 case CPU_DOWN_PREPARE_FROZEN:
2089 del_timer_sync(t);
Andi Kleen88ccbed2009-02-12 13:49:36 +01002090 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
Andi Kleen52d168e2009-02-12 13:39:29 +01002091 break;
2092 case CPU_DOWN_FAILED:
2093 case CPU_DOWN_FAILED_FROZEN:
Hidetoshi Setofe5ed912009-12-03 11:33:08 +09002094 if (!mce_ignore_ce && check_interval) {
2095 t->expires = round_jiffies(jiffies +
Tejun Heo245b2e72009-06-24 15:13:48 +09002096 __get_cpu_var(mce_next_interval));
Hidetoshi Setofe5ed912009-12-03 11:33:08 +09002097 add_timer_on(t, cpu);
2098 }
Andi Kleen88ccbed2009-02-12 13:49:36 +01002099 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
2100 break;
2101 case CPU_POST_DEAD:
2102 /* intentionally ignoring frozen here */
2103 cmci_rediscover(cpu);
Andi Kleen52d168e2009-02-12 13:39:29 +01002104 break;
Andi Kleen91c6d402005-07-28 21:15:39 -07002105 }
Andreas Herrmannbae19fe2007-11-14 17:00:44 -08002106 return NOTIFY_OK;
Andi Kleen91c6d402005-07-28 21:15:39 -07002107}
2108
Sam Ravnborg1e356692008-01-30 13:33:36 +01002109static struct notifier_block mce_cpu_notifier __cpuinitdata = {
Andi Kleen91c6d402005-07-28 21:15:39 -07002110 .notifier_call = mce_cpu_callback,
2111};
2112
Andi Kleencebe1822009-07-09 00:31:43 +02002113static __init void mce_init_banks(void)
Andi Kleen0d7482e2009-02-17 23:07:13 +01002114{
2115 int i;
2116
Andi Kleen0d7482e2009-02-17 23:07:13 +01002117 for (i = 0; i < banks; i++) {
Andi Kleencebe1822009-07-09 00:31:43 +02002118 struct mce_bank *b = &mce_banks[i];
2119 struct sysdev_attribute *a = &b->attr;
Ingo Molnare9eee032009-04-08 12:31:17 +02002120
Eric W. Biedermana07e4152010-02-11 15:23:05 -08002121 sysfs_attr_init(&a->attr);
Andi Kleencebe1822009-07-09 00:31:43 +02002122 a->attr.name = b->attrname;
2123 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
Ingo Molnare9eee032009-04-08 12:31:17 +02002124
2125 a->attr.mode = 0644;
2126 a->show = show_bank;
2127 a->store = set_bank;
Andi Kleen0d7482e2009-02-17 23:07:13 +01002128 }
Andi Kleen0d7482e2009-02-17 23:07:13 +01002129}
2130
Borislav Petkov5e099542009-10-16 12:31:32 +02002131static __init int mcheck_init_device(void)
Andi Kleen91c6d402005-07-28 21:15:39 -07002132{
2133 int err;
2134 int i = 0;
2135
Linus Torvalds1da177e2005-04-16 15:20:36 -07002136 if (!mce_available(&boot_cpu_data))
2137 return -EIO;
Andi Kleen0d7482e2009-02-17 23:07:13 +01002138
Yinghai Lue92fae02009-06-17 16:21:33 -07002139 zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
Rusty Russell996867d2009-03-13 14:49:51 +10302140
Andi Kleencebe1822009-07-09 00:31:43 +02002141 mce_init_banks();
Andi Kleen0d7482e2009-02-17 23:07:13 +01002142
Linus Torvalds1da177e2005-04-16 15:20:36 -07002143 err = sysdev_class_register(&mce_sysclass);
Akinobu Mitad435d862007-10-18 03:05:15 -07002144 if (err)
2145 return err;
Andi Kleen91c6d402005-07-28 21:15:39 -07002146
2147 for_each_online_cpu(i) {
Akinobu Mitad435d862007-10-18 03:05:15 -07002148 err = mce_create_device(i);
2149 if (err)
2150 return err;
Andi Kleen91c6d402005-07-28 21:15:39 -07002151 }
2152
Chandra Seetharamanbe6b5a32006-07-30 03:03:37 -07002153 register_hotcpu_notifier(&mce_cpu_notifier);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002154 misc_register(&mce_log_device);
Ingo Molnare9eee032009-04-08 12:31:17 +02002155
Linus Torvalds1da177e2005-04-16 15:20:36 -07002156 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002157}
Andi Kleen91c6d402005-07-28 21:15:39 -07002158
Borislav Petkov5e099542009-10-16 12:31:32 +02002159device_initcall(mcheck_init_device);
Ingo Molnara988d332009-04-08 12:31:25 +02002160
Andi Kleend7c3c9a2009-04-28 23:07:25 +02002161/*
2162 * Old style boot options parsing. Only for compatibility.
2163 */
2164static int __init mcheck_disable(char *str)
2165{
2166 mce_disabled = 1;
2167 return 1;
2168}
2169__setup("nomce", mcheck_disable);
Huang Ying5be9ed22009-07-31 09:41:42 +08002170
2171#ifdef CONFIG_DEBUG_FS
2172struct dentry *mce_get_debugfs_dir(void)
2173{
2174 static struct dentry *dmce;
2175
2176 if (!dmce)
2177 dmce = debugfs_create_dir("mce", NULL);
2178
2179 return dmce;
2180}
Huang Yingbf783f92009-07-31 09:41:43 +08002181
2182static void mce_reset(void)
2183{
2184 cpu_missing = 0;
2185 atomic_set(&mce_fake_paniced, 0);
2186 atomic_set(&mce_executing, 0);
2187 atomic_set(&mce_callin, 0);
2188 atomic_set(&global_nwo, 0);
2189}
2190
2191static int fake_panic_get(void *data, u64 *val)
2192{
2193 *val = fake_panic;
2194 return 0;
2195}
2196
2197static int fake_panic_set(void *data, u64 val)
2198{
2199 mce_reset();
2200 fake_panic = val;
2201 return 0;
2202}
2203
2204DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2205 fake_panic_set, "%llu\n");
2206
Borislav Petkov5e099542009-10-16 12:31:32 +02002207static int __init mcheck_debugfs_init(void)
Huang Yingbf783f92009-07-31 09:41:43 +08002208{
2209 struct dentry *dmce, *ffake_panic;
2210
2211 dmce = mce_get_debugfs_dir();
2212 if (!dmce)
2213 return -ENOMEM;
2214 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2215 &fake_panic_fops);
2216 if (!ffake_panic)
2217 return -ENOMEM;
2218
2219 return 0;
2220}
Borislav Petkov5e099542009-10-16 12:31:32 +02002221late_initcall(mcheck_debugfs_init);
Huang Ying5be9ed22009-07-31 09:41:42 +08002222#endif