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Paul Mackerras14cf11a2005-09-26 16:04:21 +10001/*
2 * FPU support code, moved here from head.S so that it can be used
3 * by chips which use other head-whatever.S files.
4 *
Paul Mackerrasfea23bf2006-08-30 14:45:35 +10005 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Copyright (C) 1996 Paul Mackerras.
8 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
9 *
Paul Mackerras14cf11a2005-09-26 16:04:21 +100010 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 *
15 */
16
Paul Mackerrasb3b8dc62005-10-10 22:20:10 +100017#include <asm/reg.h>
Paul Mackerras14cf11a2005-09-26 16:04:21 +100018#include <asm/page.h>
19#include <asm/mmu.h>
20#include <asm/pgtable.h>
21#include <asm/cputable.h>
22#include <asm/cache.h>
23#include <asm/thread_info.h>
24#include <asm/ppc_asm.h>
25#include <asm/asm-offsets.h>
26
Michael Neuling72ffff52008-06-25 14:07:18 +100027#ifdef CONFIG_VSX
28#define REST_32FPVSRS(n,c,base) \
29BEGIN_FTR_SECTION \
30 b 2f; \
31END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
32 REST_32FPRS(n,base); \
33 b 3f; \
342: REST_32VSRS(n,c,base); \
353:
36
37#define SAVE_32FPVSRS(n,c,base) \
38BEGIN_FTR_SECTION \
39 b 2f; \
40END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
41 SAVE_32FPRS(n,base); \
42 b 3f; \
432: SAVE_32VSRS(n,c,base); \
443:
45#else
46#define REST_32FPVSRS(n,b,base) REST_32FPRS(n, base)
47#define SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base)
48#endif
49
Paul Mackerras14cf11a2005-09-26 16:04:21 +100050/*
51 * This task wants to use the FPU now.
52 * On UP, disable FP for the task which had the FPU previously,
53 * and save its floating-point registers in its thread_struct.
54 * Load up this task's FP registers from its thread_struct,
55 * enable the FPU for the current task and return to the task.
56 */
Paul Mackerrasb85a0462005-10-06 10:59:19 +100057_GLOBAL(load_up_fpu)
Paul Mackerras14cf11a2005-09-26 16:04:21 +100058 mfmsr r5
59 ori r5,r5,MSR_FP
Michael Neulingce48b212008-06-25 14:07:18 +100060#ifdef CONFIG_VSX
61BEGIN_FTR_SECTION
62 oris r5,r5,MSR_VSX@h
63END_FTR_SECTION_IFSET(CPU_FTR_VSX)
64#endif
Paul Mackerras14cf11a2005-09-26 16:04:21 +100065 SYNC
66 MTMSRD(r5) /* enable use of fpu now */
67 isync
68/*
69 * For SMP, we don't do lazy FPU switching because it just gets too
70 * horrendously complex, especially when a task switches from one CPU
71 * to another. Instead we call giveup_fpu in switch_to.
72 */
73#ifndef CONFIG_SMP
David Gibsone58c3492006-01-13 14:56:25 +110074 LOAD_REG_ADDRBASE(r3, last_task_used_math)
Paul Mackerras63162222005-10-27 22:44:39 +100075 toreal(r3)
David Gibsone58c3492006-01-13 14:56:25 +110076 PPC_LL r4,ADDROFF(last_task_used_math)(r3)
David Gibson3ddfbcf2005-11-10 12:56:55 +110077 PPC_LCMPI 0,r4,0
Paul Mackerras14cf11a2005-09-26 16:04:21 +100078 beq 1f
Paul Mackerras63162222005-10-27 22:44:39 +100079 toreal(r4)
Paul Mackerras14cf11a2005-09-26 16:04:21 +100080 addi r4,r4,THREAD /* want last_task_used_math->thread */
Michael Neulingce48b212008-06-25 14:07:18 +100081 SAVE_32FPVSRS(0, r5, r4)
Paul Mackerras14cf11a2005-09-26 16:04:21 +100082 mffs fr0
David Gibson25c8a782005-10-27 16:27:25 +100083 stfd fr0,THREAD_FPSCR(r4)
David Gibson3ddfbcf2005-11-10 12:56:55 +110084 PPC_LL r5,PT_REGS(r4)
Paul Mackerras63162222005-10-27 22:44:39 +100085 toreal(r5)
David Gibson3ddfbcf2005-11-10 12:56:55 +110086 PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
Paul Mackerras14cf11a2005-09-26 16:04:21 +100087 li r10,MSR_FP|MSR_FE0|MSR_FE1
88 andc r4,r4,r10 /* disable FP for previous task */
David Gibson3ddfbcf2005-11-10 12:56:55 +110089 PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000901:
91#endif /* CONFIG_SMP */
92 /* enable use of FP after return */
Paul Mackerrasb85a0462005-10-06 10:59:19 +100093#ifdef CONFIG_PPC32
Benjamin Herrenschmidtee43eb72009-07-14 20:52:54 +000094 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
Paul Mackerras14cf11a2005-09-26 16:04:21 +100095 lwz r4,THREAD_FPEXC_MODE(r5)
96 ori r9,r9,MSR_FP /* enable FP for current */
97 or r9,r9,r4
Paul Mackerrasb85a0462005-10-06 10:59:19 +100098#else
99 ld r4,PACACURRENT(r13)
100 addi r5,r4,THREAD /* Get THREAD */
Paul Mackerrase2f5a3c2006-02-07 13:55:30 +1100101 lwz r4,THREAD_FPEXC_MODE(r5)
Paul Mackerrasb85a0462005-10-06 10:59:19 +1000102 ori r12,r12,MSR_FP
103 or r12,r12,r4
104 std r12,_MSR(r1)
105#endif
David Gibson25c8a782005-10-27 16:27:25 +1000106 lfd fr0,THREAD_FPSCR(r5)
Anton Blanchard3a2c48c2006-06-10 20:18:39 +1000107 MTFSF_L(fr0)
Michael Neulingce48b212008-06-25 14:07:18 +1000108 REST_32FPVSRS(0, r4, r5)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000109#ifndef CONFIG_SMP
110 subi r4,r5,THREAD
Paul Mackerras63162222005-10-27 22:44:39 +1000111 fromreal(r4)
David Gibsone58c3492006-01-13 14:56:25 +1100112 PPC_STL r4,ADDROFF(last_task_used_math)(r3)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000113#endif /* CONFIG_SMP */
114 /* restore registers and return */
115 /* we haven't used ctr or xer or lr */
Michael Neuling6f3d8e62008-06-25 14:07:18 +1000116 blr
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000117
118/*
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000119 * giveup_fpu(tsk)
120 * Disable FP for the task given as the argument,
121 * and save the floating-point registers in its thread_struct.
122 * Enables the FPU for use in the kernel on return.
123 */
Paul Mackerrasb85a0462005-10-06 10:59:19 +1000124_GLOBAL(giveup_fpu)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000125 mfmsr r5
126 ori r5,r5,MSR_FP
Michael Neulingce48b212008-06-25 14:07:18 +1000127#ifdef CONFIG_VSX
128BEGIN_FTR_SECTION
129 oris r5,r5,MSR_VSX@h
130END_FTR_SECTION_IFSET(CPU_FTR_VSX)
131#endif
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000132 SYNC_601
133 ISYNC_601
134 MTMSRD(r5) /* enable use of fpu now */
135 SYNC_601
136 isync
David Gibson3ddfbcf2005-11-10 12:56:55 +1100137 PPC_LCMPI 0,r3,0
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000138 beqlr- /* if no previous owner, done */
139 addi r3,r3,THREAD /* want THREAD of task */
David Gibson3ddfbcf2005-11-10 12:56:55 +1100140 PPC_LL r5,PT_REGS(r3)
141 PPC_LCMPI 0,r5,0
Michael Neulingce48b212008-06-25 14:07:18 +1000142 SAVE_32FPVSRS(0, r4 ,r3)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000143 mffs fr0
David Gibson25c8a782005-10-27 16:27:25 +1000144 stfd fr0,THREAD_FPSCR(r3)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000145 beq 1f
David Gibson3ddfbcf2005-11-10 12:56:55 +1100146 PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000147 li r3,MSR_FP|MSR_FE0|MSR_FE1
Michael Neuling7e875e92009-04-01 18:02:42 +0000148#ifdef CONFIG_VSX
149BEGIN_FTR_SECTION
150 oris r3,r3,MSR_VSX@h
151END_FTR_SECTION_IFSET(CPU_FTR_VSX)
152#endif
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000153 andc r4,r4,r3 /* disable FP for previous task */
David Gibson3ddfbcf2005-11-10 12:56:55 +1100154 PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
Paul Mackerras14cf11a2005-09-26 16:04:21 +10001551:
156#ifndef CONFIG_SMP
157 li r5,0
David Gibsone58c3492006-01-13 14:56:25 +1100158 LOAD_REG_ADDRBASE(r4,last_task_used_math)
159 PPC_STL r5,ADDROFF(last_task_used_math)(r4)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000160#endif /* CONFIG_SMP */
161 blr
David Gibson25c8a782005-10-27 16:27:25 +1000162
163/*
164 * These are used in the alignment trap handler when emulating
165 * single-precision loads and stores.
166 * We restore and save the fpscr so the task gets the same result
167 * and exceptions as if the cpu had performed the load or store.
168 */
169
170_GLOBAL(cvt_fd)
171 lfd 0,THREAD_FPSCR(r5) /* load up fpscr value */
Anton Blanchard3a2c48c2006-06-10 20:18:39 +1000172 MTFSF_L(0)
David Gibson25c8a782005-10-27 16:27:25 +1000173 lfs 0,0(r3)
174 stfd 0,0(r4)
175 mffs 0
176 stfd 0,THREAD_FPSCR(r5) /* save new fpscr value */
177 blr
178
179_GLOBAL(cvt_df)
180 lfd 0,THREAD_FPSCR(r5) /* load up fpscr value */
Anton Blanchard3a2c48c2006-06-10 20:18:39 +1000181 MTFSF_L(0)
David Gibson25c8a782005-10-27 16:27:25 +1000182 lfd 0,0(r3)
183 stfs 0,0(r4)
184 mffs 0
185 stfd 0,THREAD_FPSCR(r5) /* save new fpscr value */
186 blr