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Ben Dooksc6e58eb2006-09-09 21:24:13 +01001/* linux/arch/arm/mach-s3c2412/s3c2412-irq.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20*/
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/ioport.h>
26#include <linux/ptrace.h>
27#include <linux/sysdev.h>
28
29#include <asm/hardware.h>
30#include <asm/irq.h>
31#include <asm/io.h>
32
33#include <asm/mach/irq.h>
34
35#include <asm/arch/regs-irq.h>
36#include <asm/arch/regs-gpio.h>
37
38#include "cpu.h"
39#include "irq.h"
Ben Dooks1e582fc2006-09-16 00:01:39 +010040#include "pm.h"
Ben Dooksc6e58eb2006-09-09 21:24:13 +010041
42/* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by
43 * having them turn up in both the INT* and the EINT* registers. Whilst
44 * both show the status, they both now need to be acked when the IRQs
45 * go off.
46*/
47
48static void
49s3c2412_irq_mask(unsigned int irqno)
50{
51 unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
52 unsigned long mask;
53
54 mask = __raw_readl(S3C2410_INTMSK);
55 __raw_writel(mask | bitval, S3C2410_INTMSK);
56
57 mask = __raw_readl(S3C2412_EINTMASK);
58 __raw_writel(mask | bitval, S3C2412_EINTMASK);
59}
60
61static inline void
62s3c2412_irq_ack(unsigned int irqno)
63{
64 unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
65
66 __raw_writel(bitval, S3C2412_EINTPEND);
67 __raw_writel(bitval, S3C2410_SRCPND);
68 __raw_writel(bitval, S3C2410_INTPND);
69}
70
71static inline void
72s3c2412_irq_maskack(unsigned int irqno)
73{
74 unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
75 unsigned long mask;
76
77 mask = __raw_readl(S3C2410_INTMSK);
78 __raw_writel(mask|bitval, S3C2410_INTMSK);
79
80 mask = __raw_readl(S3C2412_EINTMASK);
81 __raw_writel(mask | bitval, S3C2412_EINTMASK);
82
83 __raw_writel(bitval, S3C2412_EINTPEND);
84 __raw_writel(bitval, S3C2410_SRCPND);
85 __raw_writel(bitval, S3C2410_INTPND);
86}
87
88static void
89s3c2412_irq_unmask(unsigned int irqno)
90{
91 unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
92 unsigned long mask;
93
94 mask = __raw_readl(S3C2412_EINTMASK);
95 __raw_writel(mask & ~bitval, S3C2412_EINTMASK);
96
97 mask = __raw_readl(S3C2410_INTMSK);
98 __raw_writel(mask & ~bitval, S3C2410_INTMSK);
99}
100
101static struct irqchip s3c2412_irq_eint0t4 = {
102 .ack = s3c2412_irq_ack,
103 .mask = s3c2412_irq_mask,
104 .unmask = s3c2412_irq_unmask,
105 .set_wake = s3c_irq_wake,
106 .set_type = s3c_irqext_type,
107};
108
109static int s3c2412_irq_add(struct sys_device *sysdev)
110{
111 unsigned int irqno;
112
113 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
114 set_irq_chip(irqno, &s3c2412_irq_eint0t4);
115 set_irq_handler(irqno, do_edge_IRQ);
116 set_irq_flags(irqno, IRQF_VALID);
117 }
118
119 return 0;
120}
121
122static struct sysdev_driver s3c2412_irq_driver = {
123 .add = s3c2412_irq_add,
Ben Dooks1e582fc2006-09-16 00:01:39 +0100124 .suspend = s3c24xx_irq_suspend,
125 .resume = s3c24xx_irq_resume,
Ben Dooksc6e58eb2006-09-09 21:24:13 +0100126};
127
128static int s3c2412_irq_init(void)
129{
130 return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_irq_driver);
131}
132
133arch_initcall(s3c2412_irq_init);