Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | #ifndef __ASM_CPU_SH4_DMA_H |
| 2 | #define __ASM_CPU_SH4_DMA_H |
| 3 | |
Manuel Lauss | 9f8a5e3 | 2007-01-25 15:22:11 +0900 | [diff] [blame] | 4 | /* SH7751/7760/7780 DMA IRQ sources */ |
Manuel Lauss | 9f8a5e3 | 2007-01-25 15:22:11 +0900 | [diff] [blame] | 5 | |
Paul Mundt | 0d83177 | 2006-01-16 22:14:09 -0800 | [diff] [blame] | 6 | #ifdef CONFIG_CPU_SH4A |
Paul Mundt | 5283ecb | 2006-09-27 15:59:17 +0900 | [diff] [blame] | 7 | |
Nobuhiro Iwamatsu | 71b973a | 2009-03-10 17:26:49 +0900 | [diff] [blame] | 8 | #include <cpu/dma-sh4a.h> |
Guennadi Liakhovetski | 8b1935e | 2010-02-11 16:50:14 +0000 | [diff] [blame] | 9 | |
Nobuhiro Iwamatsu | 71b973a | 2009-03-10 17:26:49 +0900 | [diff] [blame] | 10 | #else /* CONFIG_CPU_SH4A */ |
| 11 | /* |
| 12 | * SH7750/SH7751/SH7760 |
| 13 | */ |
| 14 | #define DMTE0_IRQ 34 |
| 15 | #define DMTE4_IRQ 44 |
| 16 | #define DMTE6_IRQ 46 |
| 17 | #define DMAE0_IRQ 38 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 18 | |
Nobuhiro Iwamatsu | 71b973a | 2009-03-10 17:26:49 +0900 | [diff] [blame] | 19 | #define SH_DMAC_BASE0 0xffa00000 |
| 20 | #define SH_DMAC_BASE1 0xffa00070 |
Paul Mundt | 0d83177 | 2006-01-16 22:14:09 -0800 | [diff] [blame] | 21 | /* Definitions for the SuperH DMAC */ |
Nobuhiro Iwamatsu | 71b973a | 2009-03-10 17:26:49 +0900 | [diff] [blame] | 22 | #define TM_BURST 0x00000080 |
Paul Mundt | 0d83177 | 2006-01-16 22:14:09 -0800 | [diff] [blame] | 23 | #define TS_8 0x00000010 |
| 24 | #define TS_16 0x00000020 |
| 25 | #define TS_32 0x00000030 |
| 26 | #define TS_64 0x00000000 |
| 27 | |
Paul Mundt | 0d83177 | 2006-01-16 22:14:09 -0800 | [diff] [blame] | 28 | #define DMAOR_COD 0x00000008 |
| 29 | |
Paul Mundt | 5283ecb | 2006-09-27 15:59:17 +0900 | [diff] [blame] | 30 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 31 | |
| 32 | #endif /* __ASM_CPU_SH4_DMA_H */ |