Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1 | /* |
Mike Frysinger | 26fdc1f | 2008-02-06 01:38:21 -0800 | [diff] [blame] | 2 | * Blackfin On-Chip SPI Driver |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 3 | * |
Bryan Wu | 131b17d | 2007-12-04 23:45:12 -0800 | [diff] [blame] | 4 | * Copyright 2004-2007 Analog Devices Inc. |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 5 | * |
Mike Frysinger | 26fdc1f | 2008-02-06 01:38:21 -0800 | [diff] [blame] | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 7 | * |
Mike Frysinger | 26fdc1f | 2008-02-06 01:38:21 -0800 | [diff] [blame] | 8 | * Licensed under the GPL-2 or later. |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #include <linux/init.h> |
| 12 | #include <linux/module.h> |
Bryan Wu | 131b17d | 2007-12-04 23:45:12 -0800 | [diff] [blame] | 13 | #include <linux/delay.h> |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 14 | #include <linux/device.h> |
Bryan Wu | 131b17d | 2007-12-04 23:45:12 -0800 | [diff] [blame] | 15 | #include <linux/io.h> |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 16 | #include <linux/ioport.h> |
Bryan Wu | 131b17d | 2007-12-04 23:45:12 -0800 | [diff] [blame] | 17 | #include <linux/irq.h> |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 18 | #include <linux/errno.h> |
| 19 | #include <linux/interrupt.h> |
| 20 | #include <linux/platform_device.h> |
| 21 | #include <linux/dma-mapping.h> |
| 22 | #include <linux/spi/spi.h> |
| 23 | #include <linux/workqueue.h> |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 24 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 25 | #include <asm/dma.h> |
Bryan Wu | 131b17d | 2007-12-04 23:45:12 -0800 | [diff] [blame] | 26 | #include <asm/portmux.h> |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 27 | #include <asm/bfin5xx_spi.h> |
Vitja Makarov | 8cf5858 | 2009-04-06 19:00:31 -0700 | [diff] [blame] | 28 | #include <asm/cacheflush.h> |
| 29 | |
Bryan Wu | a32c691 | 2007-12-04 23:45:15 -0800 | [diff] [blame] | 30 | #define DRV_NAME "bfin-spi" |
| 31 | #define DRV_AUTHOR "Bryan Wu, Luke Yang" |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 32 | #define DRV_DESC "Blackfin on-chip SPI Controller Driver" |
Bryan Wu | a32c691 | 2007-12-04 23:45:15 -0800 | [diff] [blame] | 33 | #define DRV_VERSION "1.0" |
| 34 | |
| 35 | MODULE_AUTHOR(DRV_AUTHOR); |
| 36 | MODULE_DESCRIPTION(DRV_DESC); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 37 | MODULE_LICENSE("GPL"); |
| 38 | |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 39 | #define START_STATE ((void *)0) |
| 40 | #define RUNNING_STATE ((void *)1) |
| 41 | #define DONE_STATE ((void *)2) |
| 42 | #define ERROR_STATE ((void *)-1) |
| 43 | #define QUEUE_RUNNING 0 |
| 44 | #define QUEUE_STOPPED 1 |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 45 | |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 46 | /* Value to send if no TX value is supplied */ |
| 47 | #define SPI_IDLE_TXVAL 0x0000 |
| 48 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 49 | struct driver_data { |
| 50 | /* Driver model hookup */ |
| 51 | struct platform_device *pdev; |
| 52 | |
| 53 | /* SPI framework hookup */ |
| 54 | struct spi_master *master; |
| 55 | |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 56 | /* Regs base of SPI controller */ |
Bryan Wu | f452126 | 2007-12-04 23:45:22 -0800 | [diff] [blame] | 57 | void __iomem *regs_base; |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 58 | |
Bryan Wu | 003d922 | 2007-12-04 23:45:22 -0800 | [diff] [blame] | 59 | /* Pin request list */ |
| 60 | u16 *pin_req; |
| 61 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 62 | /* BFIN hookup */ |
| 63 | struct bfin5xx_spi_master *master_info; |
| 64 | |
| 65 | /* Driver message queue */ |
| 66 | struct workqueue_struct *workqueue; |
| 67 | struct work_struct pump_messages; |
| 68 | spinlock_t lock; |
| 69 | struct list_head queue; |
| 70 | int busy; |
| 71 | int run; |
| 72 | |
| 73 | /* Message Transfer pump */ |
| 74 | struct tasklet_struct pump_transfers; |
| 75 | |
| 76 | /* Current message transfer state info */ |
| 77 | struct spi_message *cur_msg; |
| 78 | struct spi_transfer *cur_transfer; |
| 79 | struct chip_data *cur_chip; |
| 80 | size_t len_in_bytes; |
| 81 | size_t len; |
| 82 | void *tx; |
| 83 | void *tx_end; |
| 84 | void *rx; |
| 85 | void *rx_end; |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 86 | |
| 87 | /* DMA stuffs */ |
| 88 | int dma_channel; |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 89 | int dma_mapped; |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 90 | int dma_requested; |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 91 | dma_addr_t rx_dma; |
| 92 | dma_addr_t tx_dma; |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 93 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 94 | size_t rx_map_len; |
| 95 | size_t tx_map_len; |
| 96 | u8 n_bytes; |
Bryan Wu | fad91c8 | 2007-12-04 23:45:14 -0800 | [diff] [blame] | 97 | int cs_change; |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 98 | void (*write) (struct driver_data *); |
| 99 | void (*read) (struct driver_data *); |
| 100 | void (*duplex) (struct driver_data *); |
| 101 | }; |
| 102 | |
| 103 | struct chip_data { |
| 104 | u16 ctl_reg; |
| 105 | u16 baud; |
| 106 | u16 flag; |
| 107 | |
| 108 | u8 chip_select_num; |
| 109 | u8 n_bytes; |
Bryan Wu | 88b4036 | 2007-05-21 18:32:16 +0800 | [diff] [blame] | 110 | u8 width; /* 0 or 1 */ |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 111 | u8 enable_dma; |
| 112 | u8 bits_per_word; /* 8 or 16 */ |
| 113 | u8 cs_change_per_word; |
Bryan Wu | 62310e5 | 2007-12-04 23:45:20 -0800 | [diff] [blame] | 114 | u16 cs_chg_udelay; /* Some devices require > 255usec delay */ |
Michael Hennerich | 42c78b2 | 2009-04-06 19:00:51 -0700 | [diff] [blame] | 115 | u32 cs_gpio; |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 116 | u16 idle_tx_val; |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 117 | void (*write) (struct driver_data *); |
| 118 | void (*read) (struct driver_data *); |
| 119 | void (*duplex) (struct driver_data *); |
| 120 | }; |
| 121 | |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 122 | #define DEFINE_SPI_REG(reg, off) \ |
| 123 | static inline u16 read_##reg(struct driver_data *drv_data) \ |
| 124 | { return bfin_read16(drv_data->regs_base + off); } \ |
| 125 | static inline void write_##reg(struct driver_data *drv_data, u16 v) \ |
| 126 | { bfin_write16(drv_data->regs_base + off, v); } |
| 127 | |
| 128 | DEFINE_SPI_REG(CTRL, 0x00) |
| 129 | DEFINE_SPI_REG(FLAG, 0x04) |
| 130 | DEFINE_SPI_REG(STAT, 0x08) |
| 131 | DEFINE_SPI_REG(TDBR, 0x0C) |
| 132 | DEFINE_SPI_REG(RDBR, 0x10) |
| 133 | DEFINE_SPI_REG(BAUD, 0x14) |
| 134 | DEFINE_SPI_REG(SHAW, 0x18) |
| 135 | |
Bryan Wu | 88b4036 | 2007-05-21 18:32:16 +0800 | [diff] [blame] | 136 | static void bfin_spi_enable(struct driver_data *drv_data) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 137 | { |
| 138 | u16 cr; |
| 139 | |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 140 | cr = read_CTRL(drv_data); |
| 141 | write_CTRL(drv_data, (cr | BIT_CTL_ENABLE)); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 142 | } |
| 143 | |
Bryan Wu | 88b4036 | 2007-05-21 18:32:16 +0800 | [diff] [blame] | 144 | static void bfin_spi_disable(struct driver_data *drv_data) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 145 | { |
| 146 | u16 cr; |
| 147 | |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 148 | cr = read_CTRL(drv_data); |
| 149 | write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE))); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 150 | } |
| 151 | |
| 152 | /* Caculate the SPI_BAUD register value based on input HZ */ |
| 153 | static u16 hz_to_spi_baud(u32 speed_hz) |
| 154 | { |
| 155 | u_long sclk = get_sclk(); |
| 156 | u16 spi_baud = (sclk / (2 * speed_hz)); |
| 157 | |
| 158 | if ((sclk % (2 * speed_hz)) > 0) |
| 159 | spi_baud++; |
| 160 | |
Michael Hennerich | 7513e00 | 2009-04-06 19:00:32 -0700 | [diff] [blame] | 161 | if (spi_baud < MIN_SPI_BAUD_VAL) |
| 162 | spi_baud = MIN_SPI_BAUD_VAL; |
| 163 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 164 | return spi_baud; |
| 165 | } |
| 166 | |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 167 | static int bfin_spi_flush(struct driver_data *drv_data) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 168 | { |
| 169 | unsigned long limit = loops_per_jiffy << 1; |
| 170 | |
| 171 | /* wait for stop and clear stat */ |
Roel Kluin | b4bd2ab | 2009-06-17 16:26:02 -0700 | [diff] [blame] | 172 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && --limit) |
Bryan Wu | d8c0500 | 2007-12-04 23:45:21 -0800 | [diff] [blame] | 173 | cpu_relax(); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 174 | |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 175 | write_STAT(drv_data, BIT_STAT_CLR); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 176 | |
| 177 | return limit; |
| 178 | } |
| 179 | |
Bryan Wu | fad91c8 | 2007-12-04 23:45:14 -0800 | [diff] [blame] | 180 | /* Chip select operation functions for cs_change flag */ |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 181 | static void bfin_spi_cs_active(struct driver_data *drv_data, struct chip_data *chip) |
Bryan Wu | fad91c8 | 2007-12-04 23:45:14 -0800 | [diff] [blame] | 182 | { |
Michael Hennerich | 42c78b2 | 2009-04-06 19:00:51 -0700 | [diff] [blame] | 183 | if (likely(chip->chip_select_num)) { |
| 184 | u16 flag = read_FLAG(drv_data); |
Bryan Wu | fad91c8 | 2007-12-04 23:45:14 -0800 | [diff] [blame] | 185 | |
Michael Hennerich | 42c78b2 | 2009-04-06 19:00:51 -0700 | [diff] [blame] | 186 | flag |= chip->flag; |
| 187 | flag &= ~(chip->flag << 8); |
Bryan Wu | fad91c8 | 2007-12-04 23:45:14 -0800 | [diff] [blame] | 188 | |
Michael Hennerich | 42c78b2 | 2009-04-06 19:00:51 -0700 | [diff] [blame] | 189 | write_FLAG(drv_data, flag); |
| 190 | } else { |
| 191 | gpio_set_value(chip->cs_gpio, 0); |
| 192 | } |
Bryan Wu | fad91c8 | 2007-12-04 23:45:14 -0800 | [diff] [blame] | 193 | } |
| 194 | |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 195 | static void bfin_spi_cs_deactive(struct driver_data *drv_data, struct chip_data *chip) |
Bryan Wu | fad91c8 | 2007-12-04 23:45:14 -0800 | [diff] [blame] | 196 | { |
Michael Hennerich | 42c78b2 | 2009-04-06 19:00:51 -0700 | [diff] [blame] | 197 | if (likely(chip->chip_select_num)) { |
| 198 | u16 flag = read_FLAG(drv_data); |
Bryan Wu | fad91c8 | 2007-12-04 23:45:14 -0800 | [diff] [blame] | 199 | |
Michael Hennerich | 42c78b2 | 2009-04-06 19:00:51 -0700 | [diff] [blame] | 200 | flag &= ~chip->flag; |
| 201 | flag |= (chip->flag << 8); |
Bryan Wu | fad91c8 | 2007-12-04 23:45:14 -0800 | [diff] [blame] | 202 | |
Michael Hennerich | 42c78b2 | 2009-04-06 19:00:51 -0700 | [diff] [blame] | 203 | write_FLAG(drv_data, flag); |
| 204 | } else { |
| 205 | gpio_set_value(chip->cs_gpio, 1); |
| 206 | } |
Bryan Wu | 62310e5 | 2007-12-04 23:45:20 -0800 | [diff] [blame] | 207 | |
| 208 | /* Move delay here for consistency */ |
| 209 | if (chip->cs_chg_udelay) |
| 210 | udelay(chip->cs_chg_udelay); |
Bryan Wu | fad91c8 | 2007-12-04 23:45:14 -0800 | [diff] [blame] | 211 | } |
| 212 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 213 | /* stop controller and re-config current chip*/ |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 214 | static void bfin_spi_restore_state(struct driver_data *drv_data) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 215 | { |
| 216 | struct chip_data *chip = drv_data->cur_chip; |
| 217 | |
| 218 | /* Clear status and disable clock */ |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 219 | write_STAT(drv_data, BIT_STAT_CLR); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 220 | bfin_spi_disable(drv_data); |
Bryan Wu | 88b4036 | 2007-05-21 18:32:16 +0800 | [diff] [blame] | 221 | dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n"); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 222 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 223 | /* Load the registers */ |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 224 | write_CTRL(drv_data, chip->ctl_reg); |
Bryan Wu | 092e1fd | 2007-12-04 23:45:23 -0800 | [diff] [blame] | 225 | write_BAUD(drv_data, chip->baud); |
Sonic Zhang | cc487e7 | 2007-12-04 23:45:17 -0800 | [diff] [blame] | 226 | |
| 227 | bfin_spi_enable(drv_data); |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 228 | bfin_spi_cs_active(drv_data, chip); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 229 | } |
| 230 | |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 231 | /* used to kick off transfer in rx mode and read unwanted RX data */ |
| 232 | static inline void bfin_spi_dummy_read(struct driver_data *drv_data) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 233 | { |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 234 | (void) read_RDBR(drv_data); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 235 | } |
| 236 | |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 237 | static void bfin_spi_null_writer(struct driver_data *drv_data) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 238 | { |
| 239 | u8 n_bytes = drv_data->n_bytes; |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 240 | u16 tx_val = drv_data->cur_chip->idle_tx_val; |
| 241 | |
| 242 | /* clear RXS (we check for RXS inside the loop) */ |
| 243 | bfin_spi_dummy_read(drv_data); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 244 | |
| 245 | while (drv_data->tx < drv_data->tx_end) { |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 246 | write_TDBR(drv_data, tx_val); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 247 | drv_data->tx += n_bytes; |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 248 | /* wait until transfer finished. |
| 249 | checking SPIF or TXS may not guarantee transfer completion */ |
| 250 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
| 251 | cpu_relax(); |
| 252 | /* discard RX data and clear RXS */ |
| 253 | bfin_spi_dummy_read(drv_data); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 254 | } |
| 255 | } |
| 256 | |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 257 | static void bfin_spi_null_reader(struct driver_data *drv_data) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 258 | { |
| 259 | u8 n_bytes = drv_data->n_bytes; |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 260 | u16 tx_val = drv_data->cur_chip->idle_tx_val; |
| 261 | |
| 262 | /* discard old RX data and clear RXS */ |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 263 | bfin_spi_dummy_read(drv_data); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 264 | |
| 265 | while (drv_data->rx < drv_data->rx_end) { |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 266 | write_TDBR(drv_data, tx_val); |
| 267 | drv_data->rx += n_bytes; |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 268 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
Bryan Wu | d8c0500 | 2007-12-04 23:45:21 -0800 | [diff] [blame] | 269 | cpu_relax(); |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 270 | bfin_spi_dummy_read(drv_data); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 271 | } |
| 272 | } |
| 273 | |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 274 | static void bfin_spi_u8_writer(struct driver_data *drv_data) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 275 | { |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 276 | /* clear RXS (we check for RXS inside the loop) */ |
| 277 | bfin_spi_dummy_read(drv_data); |
Sonic Zhang | cc487e7 | 2007-12-04 23:45:17 -0800 | [diff] [blame] | 278 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 279 | while (drv_data->tx < drv_data->tx_end) { |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 280 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx++))); |
| 281 | /* wait until transfer finished. |
| 282 | checking SPIF or TXS may not guarantee transfer completion */ |
| 283 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
Bryan Wu | d8c0500 | 2007-12-04 23:45:21 -0800 | [diff] [blame] | 284 | cpu_relax(); |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 285 | /* discard RX data and clear RXS */ |
| 286 | bfin_spi_dummy_read(drv_data); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 287 | } |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 288 | } |
| 289 | |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 290 | static void bfin_spi_u8_cs_chg_writer(struct driver_data *drv_data) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 291 | { |
| 292 | struct chip_data *chip = drv_data->cur_chip; |
| 293 | |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 294 | /* clear RXS (we check for RXS inside the loop) */ |
| 295 | bfin_spi_dummy_read(drv_data); |
| 296 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 297 | while (drv_data->tx < drv_data->tx_end) { |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 298 | bfin_spi_cs_active(drv_data, chip); |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 299 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx++))); |
| 300 | /* make sure transfer finished before deactiving CS */ |
| 301 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
Bryan Wu | d8c0500 | 2007-12-04 23:45:21 -0800 | [diff] [blame] | 302 | cpu_relax(); |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 303 | bfin_spi_dummy_read(drv_data); |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 304 | bfin_spi_cs_deactive(drv_data, chip); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 305 | } |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 306 | } |
| 307 | |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 308 | static void bfin_spi_u8_reader(struct driver_data *drv_data) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 309 | { |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 310 | u16 tx_val = drv_data->cur_chip->idle_tx_val; |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 311 | |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 312 | /* discard old RX data and clear RXS */ |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 313 | bfin_spi_dummy_read(drv_data); |
Sonic Zhang | cc487e7 | 2007-12-04 23:45:17 -0800 | [diff] [blame] | 314 | |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 315 | while (drv_data->rx < drv_data->rx_end) { |
| 316 | write_TDBR(drv_data, tx_val); |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 317 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
Bryan Wu | d8c0500 | 2007-12-04 23:45:21 -0800 | [diff] [blame] | 318 | cpu_relax(); |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 319 | *(u8 *) (drv_data->rx++) = read_RDBR(drv_data); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 320 | } |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 321 | } |
| 322 | |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 323 | static void bfin_spi_u8_cs_chg_reader(struct driver_data *drv_data) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 324 | { |
| 325 | struct chip_data *chip = drv_data->cur_chip; |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 326 | u16 tx_val = chip->idle_tx_val; |
| 327 | |
| 328 | /* discard old RX data and clear RXS */ |
| 329 | bfin_spi_dummy_read(drv_data); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 330 | |
Bryan Wu | e26aa01 | 2008-02-06 01:38:18 -0800 | [diff] [blame] | 331 | while (drv_data->rx < drv_data->rx_end) { |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 332 | bfin_spi_cs_active(drv_data, chip); |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 333 | write_TDBR(drv_data, tx_val); |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 334 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
Bryan Wu | d8c0500 | 2007-12-04 23:45:21 -0800 | [diff] [blame] | 335 | cpu_relax(); |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 336 | *(u8 *) (drv_data->rx++) = read_RDBR(drv_data); |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 337 | bfin_spi_cs_deactive(drv_data, chip); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 338 | } |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 339 | } |
| 340 | |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 341 | static void bfin_spi_u8_duplex(struct driver_data *drv_data) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 342 | { |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 343 | /* discard old RX data and clear RXS */ |
| 344 | bfin_spi_dummy_read(drv_data); |
| 345 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 346 | while (drv_data->rx < drv_data->rx_end) { |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 347 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx++))); |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 348 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
Bryan Wu | d8c0500 | 2007-12-04 23:45:21 -0800 | [diff] [blame] | 349 | cpu_relax(); |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 350 | *(u8 *) (drv_data->rx++) = read_RDBR(drv_data); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 351 | } |
| 352 | } |
| 353 | |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 354 | static void bfin_spi_u8_cs_chg_duplex(struct driver_data *drv_data) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 355 | { |
| 356 | struct chip_data *chip = drv_data->cur_chip; |
| 357 | |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 358 | /* discard old RX data and clear RXS */ |
| 359 | bfin_spi_dummy_read(drv_data); |
| 360 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 361 | while (drv_data->rx < drv_data->rx_end) { |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 362 | bfin_spi_cs_active(drv_data, chip); |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 363 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx++))); |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 364 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
Bryan Wu | d8c0500 | 2007-12-04 23:45:21 -0800 | [diff] [blame] | 365 | cpu_relax(); |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 366 | *(u8 *) (drv_data->rx++) = read_RDBR(drv_data); |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 367 | bfin_spi_cs_deactive(drv_data, chip); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 368 | } |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 369 | } |
| 370 | |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 371 | static void bfin_spi_u16_writer(struct driver_data *drv_data) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 372 | { |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 373 | /* clear RXS (we check for RXS inside the loop) */ |
| 374 | bfin_spi_dummy_read(drv_data); |
Bryan Wu | 88b4036 | 2007-05-21 18:32:16 +0800 | [diff] [blame] | 375 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 376 | while (drv_data->tx < drv_data->tx_end) { |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 377 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 378 | drv_data->tx += 2; |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 379 | /* wait until transfer finished. |
| 380 | checking SPIF or TXS may not guarantee transfer completion */ |
| 381 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
| 382 | cpu_relax(); |
| 383 | /* discard RX data and clear RXS */ |
| 384 | bfin_spi_dummy_read(drv_data); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 385 | } |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 386 | } |
| 387 | |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 388 | static void bfin_spi_u16_cs_chg_writer(struct driver_data *drv_data) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 389 | { |
| 390 | struct chip_data *chip = drv_data->cur_chip; |
| 391 | |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 392 | /* clear RXS (we check for RXS inside the loop) */ |
| 393 | bfin_spi_dummy_read(drv_data); |
| 394 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 395 | while (drv_data->tx < drv_data->tx_end) { |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 396 | bfin_spi_cs_active(drv_data, chip); |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 397 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 398 | drv_data->tx += 2; |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 399 | /* make sure transfer finished before deactiving CS */ |
| 400 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
| 401 | cpu_relax(); |
| 402 | bfin_spi_dummy_read(drv_data); |
| 403 | bfin_spi_cs_deactive(drv_data, chip); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 404 | } |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 405 | } |
| 406 | |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 407 | static void bfin_spi_u16_reader(struct driver_data *drv_data) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 408 | { |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 409 | u16 tx_val = drv_data->cur_chip->idle_tx_val; |
Sonic Zhang | cc487e7 | 2007-12-04 23:45:17 -0800 | [diff] [blame] | 410 | |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 411 | /* discard old RX data and clear RXS */ |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 412 | bfin_spi_dummy_read(drv_data); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 413 | |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 414 | while (drv_data->rx < drv_data->rx_end) { |
| 415 | write_TDBR(drv_data, tx_val); |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 416 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
Bryan Wu | d8c0500 | 2007-12-04 23:45:21 -0800 | [diff] [blame] | 417 | cpu_relax(); |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 418 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 419 | drv_data->rx += 2; |
| 420 | } |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 421 | } |
| 422 | |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 423 | static void bfin_spi_u16_cs_chg_reader(struct driver_data *drv_data) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 424 | { |
| 425 | struct chip_data *chip = drv_data->cur_chip; |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 426 | u16 tx_val = chip->idle_tx_val; |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 427 | |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 428 | /* discard old RX data and clear RXS */ |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 429 | bfin_spi_dummy_read(drv_data); |
Sonic Zhang | cc487e7 | 2007-12-04 23:45:17 -0800 | [diff] [blame] | 430 | |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 431 | while (drv_data->rx < drv_data->rx_end) { |
| 432 | bfin_spi_cs_active(drv_data, chip); |
| 433 | write_TDBR(drv_data, tx_val); |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 434 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
Bryan Wu | d8c0500 | 2007-12-04 23:45:21 -0800 | [diff] [blame] | 435 | cpu_relax(); |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 436 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 437 | drv_data->rx += 2; |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 438 | bfin_spi_cs_deactive(drv_data, chip); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 439 | } |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 440 | } |
| 441 | |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 442 | static void bfin_spi_u16_duplex(struct driver_data *drv_data) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 443 | { |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 444 | /* discard old RX data and clear RXS */ |
| 445 | bfin_spi_dummy_read(drv_data); |
| 446 | |
| 447 | while (drv_data->rx < drv_data->rx_end) { |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 448 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 449 | drv_data->tx += 2; |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 450 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
Bryan Wu | d8c0500 | 2007-12-04 23:45:21 -0800 | [diff] [blame] | 451 | cpu_relax(); |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 452 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 453 | drv_data->rx += 2; |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 454 | } |
| 455 | } |
| 456 | |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 457 | static void bfin_spi_u16_cs_chg_duplex(struct driver_data *drv_data) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 458 | { |
| 459 | struct chip_data *chip = drv_data->cur_chip; |
| 460 | |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 461 | /* discard old RX data and clear RXS */ |
| 462 | bfin_spi_dummy_read(drv_data); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 463 | |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 464 | while (drv_data->rx < drv_data->rx_end) { |
| 465 | bfin_spi_cs_active(drv_data, chip); |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 466 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 467 | drv_data->tx += 2; |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 468 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
Bryan Wu | d8c0500 | 2007-12-04 23:45:21 -0800 | [diff] [blame] | 469 | cpu_relax(); |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 470 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 471 | drv_data->rx += 2; |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 472 | bfin_spi_cs_deactive(drv_data, chip); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 473 | } |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 474 | } |
| 475 | |
| 476 | /* test if ther is more transfer to be done */ |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 477 | static void *bfin_spi_next_transfer(struct driver_data *drv_data) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 478 | { |
| 479 | struct spi_message *msg = drv_data->cur_msg; |
| 480 | struct spi_transfer *trans = drv_data->cur_transfer; |
| 481 | |
| 482 | /* Move to next transfer */ |
| 483 | if (trans->transfer_list.next != &msg->transfers) { |
| 484 | drv_data->cur_transfer = |
| 485 | list_entry(trans->transfer_list.next, |
| 486 | struct spi_transfer, transfer_list); |
| 487 | return RUNNING_STATE; |
| 488 | } else |
| 489 | return DONE_STATE; |
| 490 | } |
| 491 | |
| 492 | /* |
| 493 | * caller already set message->status; |
| 494 | * dma and pio irqs are blocked give finished message back |
| 495 | */ |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 496 | static void bfin_spi_giveback(struct driver_data *drv_data) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 497 | { |
Bryan Wu | fad91c8 | 2007-12-04 23:45:14 -0800 | [diff] [blame] | 498 | struct chip_data *chip = drv_data->cur_chip; |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 499 | struct spi_transfer *last_transfer; |
| 500 | unsigned long flags; |
| 501 | struct spi_message *msg; |
| 502 | |
| 503 | spin_lock_irqsave(&drv_data->lock, flags); |
| 504 | msg = drv_data->cur_msg; |
| 505 | drv_data->cur_msg = NULL; |
| 506 | drv_data->cur_transfer = NULL; |
| 507 | drv_data->cur_chip = NULL; |
| 508 | queue_work(drv_data->workqueue, &drv_data->pump_messages); |
| 509 | spin_unlock_irqrestore(&drv_data->lock, flags); |
| 510 | |
| 511 | last_transfer = list_entry(msg->transfers.prev, |
| 512 | struct spi_transfer, transfer_list); |
| 513 | |
| 514 | msg->state = NULL; |
| 515 | |
Bryan Wu | fad91c8 | 2007-12-04 23:45:14 -0800 | [diff] [blame] | 516 | if (!drv_data->cs_change) |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 517 | bfin_spi_cs_deactive(drv_data, chip); |
Bryan Wu | fad91c8 | 2007-12-04 23:45:14 -0800 | [diff] [blame] | 518 | |
Yi Li | b9b2a76 | 2009-04-06 19:00:49 -0700 | [diff] [blame] | 519 | /* Not stop spi in autobuffer mode */ |
| 520 | if (drv_data->tx_dma != 0xFFFF) |
| 521 | bfin_spi_disable(drv_data); |
| 522 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 523 | if (msg->complete) |
| 524 | msg->complete(msg->context); |
| 525 | } |
| 526 | |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 527 | static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 528 | { |
Jeff Garzik | 15aafa2 | 2008-02-06 01:36:20 -0800 | [diff] [blame] | 529 | struct driver_data *drv_data = dev_id; |
Bryan Wu | fad91c8 | 2007-12-04 23:45:14 -0800 | [diff] [blame] | 530 | struct chip_data *chip = drv_data->cur_chip; |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 531 | struct spi_message *msg = drv_data->cur_msg; |
Mike Frysinger | aaaf939 | 2009-04-06 19:00:42 -0700 | [diff] [blame] | 532 | unsigned long timeout; |
Mike Frysinger | d24bd1d | 2009-04-06 19:00:38 -0700 | [diff] [blame] | 533 | unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel); |
Mike Frysinger | 04b95d2 | 2009-04-06 19:00:35 -0700 | [diff] [blame] | 534 | u16 spistat = read_STAT(drv_data); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 535 | |
Mike Frysinger | d24bd1d | 2009-04-06 19:00:38 -0700 | [diff] [blame] | 536 | dev_dbg(&drv_data->pdev->dev, |
| 537 | "in dma_irq_handler dmastat:0x%x spistat:0x%x\n", |
| 538 | dmastat, spistat); |
| 539 | |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 540 | clear_dma_irqstat(drv_data->dma_channel); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 541 | |
Bryan Wu | d6fe89b | 2007-06-11 17:34:17 +0800 | [diff] [blame] | 542 | /* Wait for DMA to complete */ |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 543 | while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN) |
Bryan Wu | d8c0500 | 2007-12-04 23:45:21 -0800 | [diff] [blame] | 544 | cpu_relax(); |
Bryan Wu | d6fe89b | 2007-06-11 17:34:17 +0800 | [diff] [blame] | 545 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 546 | /* |
Bryan Wu | d6fe89b | 2007-06-11 17:34:17 +0800 | [diff] [blame] | 547 | * wait for the last transaction shifted out. HRM states: |
| 548 | * at this point there may still be data in the SPI DMA FIFO waiting |
| 549 | * to be transmitted ... software needs to poll TXS in the SPI_STAT |
| 550 | * register until it goes low for 2 successive reads |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 551 | */ |
| 552 | if (drv_data->tx != NULL) { |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 553 | while ((read_STAT(drv_data) & TXS) || |
| 554 | (read_STAT(drv_data) & TXS)) |
Bryan Wu | d8c0500 | 2007-12-04 23:45:21 -0800 | [diff] [blame] | 555 | cpu_relax(); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 556 | } |
| 557 | |
Mike Frysinger | aaaf939 | 2009-04-06 19:00:42 -0700 | [diff] [blame] | 558 | dev_dbg(&drv_data->pdev->dev, |
| 559 | "in dma_irq_handler dmastat:0x%x spistat:0x%x\n", |
| 560 | dmastat, read_STAT(drv_data)); |
| 561 | |
| 562 | timeout = jiffies + HZ; |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 563 | while (!(read_STAT(drv_data) & SPIF)) |
Mike Frysinger | aaaf939 | 2009-04-06 19:00:42 -0700 | [diff] [blame] | 564 | if (!time_before(jiffies, timeout)) { |
| 565 | dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF"); |
| 566 | break; |
| 567 | } else |
| 568 | cpu_relax(); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 569 | |
Mike Frysinger | 40a2945 | 2009-04-06 19:00:38 -0700 | [diff] [blame] | 570 | if ((dmastat & DMA_ERR) && (spistat & RBSY)) { |
Mike Frysinger | 04b95d2 | 2009-04-06 19:00:35 -0700 | [diff] [blame] | 571 | msg->state = ERROR_STATE; |
| 572 | dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n"); |
| 573 | } else { |
| 574 | msg->actual_length += drv_data->len_in_bytes; |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 575 | |
Mike Frysinger | 04b95d2 | 2009-04-06 19:00:35 -0700 | [diff] [blame] | 576 | if (drv_data->cs_change) |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 577 | bfin_spi_cs_deactive(drv_data, chip); |
Bryan Wu | fad91c8 | 2007-12-04 23:45:14 -0800 | [diff] [blame] | 578 | |
Mike Frysinger | 04b95d2 | 2009-04-06 19:00:35 -0700 | [diff] [blame] | 579 | /* Move to next transfer */ |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 580 | msg->state = bfin_spi_next_transfer(drv_data); |
Mike Frysinger | 04b95d2 | 2009-04-06 19:00:35 -0700 | [diff] [blame] | 581 | } |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 582 | |
| 583 | /* Schedule transfer tasklet */ |
| 584 | tasklet_schedule(&drv_data->pump_transfers); |
| 585 | |
| 586 | /* free the irq handler before next transfer */ |
Bryan Wu | 88b4036 | 2007-05-21 18:32:16 +0800 | [diff] [blame] | 587 | dev_dbg(&drv_data->pdev->dev, |
| 588 | "disable dma channel irq%d\n", |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 589 | drv_data->dma_channel); |
| 590 | dma_disable_irq(drv_data->dma_channel); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 591 | |
| 592 | return IRQ_HANDLED; |
| 593 | } |
| 594 | |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 595 | static void bfin_spi_pump_transfers(unsigned long data) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 596 | { |
| 597 | struct driver_data *drv_data = (struct driver_data *)data; |
| 598 | struct spi_message *message = NULL; |
| 599 | struct spi_transfer *transfer = NULL; |
| 600 | struct spi_transfer *previous = NULL; |
| 601 | struct chip_data *chip = NULL; |
Bryan Wu | 88b4036 | 2007-05-21 18:32:16 +0800 | [diff] [blame] | 602 | u8 width; |
| 603 | u16 cr, dma_width, dma_config; |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 604 | u32 tranf_success = 1; |
Vitja Makarov | 8eeb12e | 2008-05-01 04:35:03 -0700 | [diff] [blame] | 605 | u8 full_duplex = 0; |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 606 | |
| 607 | /* Get current state information */ |
| 608 | message = drv_data->cur_msg; |
| 609 | transfer = drv_data->cur_transfer; |
| 610 | chip = drv_data->cur_chip; |
Bryan Wu | 092e1fd | 2007-12-04 23:45:23 -0800 | [diff] [blame] | 611 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 612 | /* |
| 613 | * if msg is error or done, report it back using complete() callback |
| 614 | */ |
| 615 | |
| 616 | /* Handle for abort */ |
| 617 | if (message->state == ERROR_STATE) { |
Mike Frysinger | d24bd1d | 2009-04-06 19:00:38 -0700 | [diff] [blame] | 618 | dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n"); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 619 | message->status = -EIO; |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 620 | bfin_spi_giveback(drv_data); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 621 | return; |
| 622 | } |
| 623 | |
| 624 | /* Handle end of message */ |
| 625 | if (message->state == DONE_STATE) { |
Mike Frysinger | d24bd1d | 2009-04-06 19:00:38 -0700 | [diff] [blame] | 626 | dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n"); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 627 | message->status = 0; |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 628 | bfin_spi_giveback(drv_data); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 629 | return; |
| 630 | } |
| 631 | |
| 632 | /* Delay if requested at end of transfer */ |
| 633 | if (message->state == RUNNING_STATE) { |
Mike Frysinger | d24bd1d | 2009-04-06 19:00:38 -0700 | [diff] [blame] | 634 | dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n"); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 635 | previous = list_entry(transfer->transfer_list.prev, |
| 636 | struct spi_transfer, transfer_list); |
| 637 | if (previous->delay_usecs) |
| 638 | udelay(previous->delay_usecs); |
| 639 | } |
| 640 | |
| 641 | /* Setup the transfer state based on the type of transfer */ |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 642 | if (bfin_spi_flush(drv_data) == 0) { |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 643 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); |
| 644 | message->status = -EIO; |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 645 | bfin_spi_giveback(drv_data); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 646 | return; |
| 647 | } |
| 648 | |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 649 | if (transfer->len == 0) { |
| 650 | /* Move to next transfer of this msg */ |
| 651 | message->state = bfin_spi_next_transfer(drv_data); |
| 652 | /* Schedule next transfer tasklet */ |
| 653 | tasklet_schedule(&drv_data->pump_transfers); |
| 654 | } |
| 655 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 656 | if (transfer->tx_buf != NULL) { |
| 657 | drv_data->tx = (void *)transfer->tx_buf; |
| 658 | drv_data->tx_end = drv_data->tx + transfer->len; |
Bryan Wu | 88b4036 | 2007-05-21 18:32:16 +0800 | [diff] [blame] | 659 | dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n", |
| 660 | transfer->tx_buf, drv_data->tx_end); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 661 | } else { |
| 662 | drv_data->tx = NULL; |
| 663 | } |
| 664 | |
| 665 | if (transfer->rx_buf != NULL) { |
Vitja Makarov | 8eeb12e | 2008-05-01 04:35:03 -0700 | [diff] [blame] | 666 | full_duplex = transfer->tx_buf != NULL; |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 667 | drv_data->rx = transfer->rx_buf; |
| 668 | drv_data->rx_end = drv_data->rx + transfer->len; |
Bryan Wu | 88b4036 | 2007-05-21 18:32:16 +0800 | [diff] [blame] | 669 | dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n", |
| 670 | transfer->rx_buf, drv_data->rx_end); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 671 | } else { |
| 672 | drv_data->rx = NULL; |
| 673 | } |
| 674 | |
| 675 | drv_data->rx_dma = transfer->rx_dma; |
| 676 | drv_data->tx_dma = transfer->tx_dma; |
| 677 | drv_data->len_in_bytes = transfer->len; |
Bryan Wu | fad91c8 | 2007-12-04 23:45:14 -0800 | [diff] [blame] | 678 | drv_data->cs_change = transfer->cs_change; |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 679 | |
Bryan Wu | 092e1fd | 2007-12-04 23:45:23 -0800 | [diff] [blame] | 680 | /* Bits per word setup */ |
| 681 | switch (transfer->bits_per_word) { |
| 682 | case 8: |
| 683 | drv_data->n_bytes = 1; |
| 684 | width = CFG_SPI_WORDSIZE8; |
| 685 | drv_data->read = chip->cs_change_per_word ? |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 686 | bfin_spi_u8_cs_chg_reader : bfin_spi_u8_reader; |
Bryan Wu | 092e1fd | 2007-12-04 23:45:23 -0800 | [diff] [blame] | 687 | drv_data->write = chip->cs_change_per_word ? |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 688 | bfin_spi_u8_cs_chg_writer : bfin_spi_u8_writer; |
Bryan Wu | 092e1fd | 2007-12-04 23:45:23 -0800 | [diff] [blame] | 689 | drv_data->duplex = chip->cs_change_per_word ? |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 690 | bfin_spi_u8_cs_chg_duplex : bfin_spi_u8_duplex; |
Bryan Wu | 092e1fd | 2007-12-04 23:45:23 -0800 | [diff] [blame] | 691 | break; |
| 692 | |
| 693 | case 16: |
| 694 | drv_data->n_bytes = 2; |
| 695 | width = CFG_SPI_WORDSIZE16; |
| 696 | drv_data->read = chip->cs_change_per_word ? |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 697 | bfin_spi_u16_cs_chg_reader : bfin_spi_u16_reader; |
Bryan Wu | 092e1fd | 2007-12-04 23:45:23 -0800 | [diff] [blame] | 698 | drv_data->write = chip->cs_change_per_word ? |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 699 | bfin_spi_u16_cs_chg_writer : bfin_spi_u16_writer; |
Bryan Wu | 092e1fd | 2007-12-04 23:45:23 -0800 | [diff] [blame] | 700 | drv_data->duplex = chip->cs_change_per_word ? |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 701 | bfin_spi_u16_cs_chg_duplex : bfin_spi_u16_duplex; |
Bryan Wu | 092e1fd | 2007-12-04 23:45:23 -0800 | [diff] [blame] | 702 | break; |
| 703 | |
| 704 | default: |
| 705 | /* No change, the same as default setting */ |
| 706 | drv_data->n_bytes = chip->n_bytes; |
| 707 | width = chip->width; |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 708 | drv_data->write = drv_data->tx ? chip->write : bfin_spi_null_writer; |
| 709 | drv_data->read = drv_data->rx ? chip->read : bfin_spi_null_reader; |
| 710 | drv_data->duplex = chip->duplex ? chip->duplex : bfin_spi_null_writer; |
Bryan Wu | 092e1fd | 2007-12-04 23:45:23 -0800 | [diff] [blame] | 711 | break; |
| 712 | } |
| 713 | cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD)); |
| 714 | cr |= (width << 8); |
| 715 | write_CTRL(drv_data, cr); |
| 716 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 717 | if (width == CFG_SPI_WORDSIZE16) { |
| 718 | drv_data->len = (transfer->len) >> 1; |
| 719 | } else { |
| 720 | drv_data->len = transfer->len; |
| 721 | } |
Mike Frysinger | 4fb98ef | 2008-04-08 17:41:57 -0700 | [diff] [blame] | 722 | dev_dbg(&drv_data->pdev->dev, |
| 723 | "transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n", |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 724 | drv_data->write, chip->write, bfin_spi_null_writer); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 725 | |
| 726 | /* speed and width has been set on per message */ |
| 727 | message->state = RUNNING_STATE; |
| 728 | dma_config = 0; |
| 729 | |
Bryan Wu | 092e1fd | 2007-12-04 23:45:23 -0800 | [diff] [blame] | 730 | /* Speed setup (surely valid because already checked) */ |
| 731 | if (transfer->speed_hz) |
| 732 | write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz)); |
| 733 | else |
| 734 | write_BAUD(drv_data, chip->baud); |
| 735 | |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 736 | write_STAT(drv_data, BIT_STAT_CLR); |
| 737 | cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD)); |
Yi Li | b9b2a76 | 2009-04-06 19:00:49 -0700 | [diff] [blame] | 738 | if (drv_data->cs_change) |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 739 | bfin_spi_cs_active(drv_data, chip); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 740 | |
Bryan Wu | 88b4036 | 2007-05-21 18:32:16 +0800 | [diff] [blame] | 741 | dev_dbg(&drv_data->pdev->dev, |
| 742 | "now pumping a transfer: width is %d, len is %d\n", |
| 743 | width, transfer->len); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 744 | |
| 745 | /* |
Vitja Makarov | 8cf5858 | 2009-04-06 19:00:31 -0700 | [diff] [blame] | 746 | * Try to map dma buffer and do a dma transfer. If successful use, |
| 747 | * different way to r/w according to the enable_dma settings and if |
| 748 | * we are not doing a full duplex transfer (since the hardware does |
| 749 | * not support full duplex DMA transfers). |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 750 | */ |
Vitja Makarov | 8eeb12e | 2008-05-01 04:35:03 -0700 | [diff] [blame] | 751 | if (!full_duplex && drv_data->cur_chip->enable_dma |
| 752 | && drv_data->len > 6) { |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 753 | |
Mike Frysinger | 11d6f59 | 2009-04-06 19:00:41 -0700 | [diff] [blame] | 754 | unsigned long dma_start_addr, flags; |
Mike Frysinger | 7aec356 | 2009-04-06 19:00:36 -0700 | [diff] [blame] | 755 | |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 756 | disable_dma(drv_data->dma_channel); |
| 757 | clear_dma_irqstat(drv_data->dma_channel); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 758 | |
| 759 | /* config dma channel */ |
Bryan Wu | 88b4036 | 2007-05-21 18:32:16 +0800 | [diff] [blame] | 760 | dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n"); |
Mike Frysinger | 7aec356 | 2009-04-06 19:00:36 -0700 | [diff] [blame] | 761 | set_dma_x_count(drv_data->dma_channel, drv_data->len); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 762 | if (width == CFG_SPI_WORDSIZE16) { |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 763 | set_dma_x_modify(drv_data->dma_channel, 2); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 764 | dma_width = WDSIZE_16; |
| 765 | } else { |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 766 | set_dma_x_modify(drv_data->dma_channel, 1); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 767 | dma_width = WDSIZE_8; |
| 768 | } |
| 769 | |
Sonic Zhang | 3f479a6 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 770 | /* poll for SPI completion before start */ |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 771 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
Bryan Wu | d8c0500 | 2007-12-04 23:45:21 -0800 | [diff] [blame] | 772 | cpu_relax(); |
Sonic Zhang | 3f479a6 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 773 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 774 | /* dirty hack for autobuffer DMA mode */ |
| 775 | if (drv_data->tx_dma == 0xFFFF) { |
Bryan Wu | 88b4036 | 2007-05-21 18:32:16 +0800 | [diff] [blame] | 776 | dev_dbg(&drv_data->pdev->dev, |
| 777 | "doing autobuffer DMA out.\n"); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 778 | |
| 779 | /* no irq in autobuffer mode */ |
| 780 | dma_config = |
| 781 | (DMAFLOW_AUTO | RESTART | dma_width | DI_EN); |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 782 | set_dma_config(drv_data->dma_channel, dma_config); |
| 783 | set_dma_start_addr(drv_data->dma_channel, |
Bryan Wu | a32c691 | 2007-12-04 23:45:15 -0800 | [diff] [blame] | 784 | (unsigned long)drv_data->tx); |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 785 | enable_dma(drv_data->dma_channel); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 786 | |
Sonic Zhang | 07612e5 | 2007-12-04 23:45:21 -0800 | [diff] [blame] | 787 | /* start SPI transfer */ |
Mike Frysinger | 11d6f59 | 2009-04-06 19:00:41 -0700 | [diff] [blame] | 788 | write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX); |
Sonic Zhang | 07612e5 | 2007-12-04 23:45:21 -0800 | [diff] [blame] | 789 | |
| 790 | /* just return here, there can only be one transfer |
| 791 | * in this mode |
| 792 | */ |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 793 | message->status = 0; |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 794 | bfin_spi_giveback(drv_data); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 795 | return; |
| 796 | } |
| 797 | |
| 798 | /* In dma mode, rx or tx must be NULL in one transfer */ |
Mike Frysinger | 7aec356 | 2009-04-06 19:00:36 -0700 | [diff] [blame] | 799 | dma_config = (RESTART | dma_width | DI_EN); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 800 | if (drv_data->rx != NULL) { |
| 801 | /* set transfer mode, and enable SPI */ |
Mike Frysinger | d24bd1d | 2009-04-06 19:00:38 -0700 | [diff] [blame] | 802 | dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n", |
| 803 | drv_data->rx, drv_data->len_in_bytes); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 804 | |
Vitja Makarov | 8cf5858 | 2009-04-06 19:00:31 -0700 | [diff] [blame] | 805 | /* invalidate caches, if needed */ |
Jie Zhang | 67834fa | 2009-06-10 06:26:26 +0000 | [diff] [blame] | 806 | if (bfin_addr_dcacheable((unsigned long) drv_data->rx)) |
Vitja Makarov | 8cf5858 | 2009-04-06 19:00:31 -0700 | [diff] [blame] | 807 | invalidate_dcache_range((unsigned long) drv_data->rx, |
| 808 | (unsigned long) (drv_data->rx + |
Mike Frysinger | ace3286 | 2009-04-06 19:00:34 -0700 | [diff] [blame] | 809 | drv_data->len_in_bytes)); |
Vitja Makarov | 8cf5858 | 2009-04-06 19:00:31 -0700 | [diff] [blame] | 810 | |
Mike Frysinger | 7aec356 | 2009-04-06 19:00:36 -0700 | [diff] [blame] | 811 | dma_config |= WNR; |
| 812 | dma_start_addr = (unsigned long)drv_data->rx; |
Mike Frysinger | b31e27a | 2009-04-06 19:00:39 -0700 | [diff] [blame] | 813 | cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT; |
Sonic Zhang | 07612e5 | 2007-12-04 23:45:21 -0800 | [diff] [blame] | 814 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 815 | } else if (drv_data->tx != NULL) { |
Bryan Wu | 88b4036 | 2007-05-21 18:32:16 +0800 | [diff] [blame] | 816 | dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n"); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 817 | |
Vitja Makarov | 8cf5858 | 2009-04-06 19:00:31 -0700 | [diff] [blame] | 818 | /* flush caches, if needed */ |
Jie Zhang | 67834fa | 2009-06-10 06:26:26 +0000 | [diff] [blame] | 819 | if (bfin_addr_dcacheable((unsigned long) drv_data->tx)) |
Vitja Makarov | 8cf5858 | 2009-04-06 19:00:31 -0700 | [diff] [blame] | 820 | flush_dcache_range((unsigned long) drv_data->tx, |
| 821 | (unsigned long) (drv_data->tx + |
Mike Frysinger | ace3286 | 2009-04-06 19:00:34 -0700 | [diff] [blame] | 822 | drv_data->len_in_bytes)); |
Vitja Makarov | 8cf5858 | 2009-04-06 19:00:31 -0700 | [diff] [blame] | 823 | |
Mike Frysinger | 7aec356 | 2009-04-06 19:00:36 -0700 | [diff] [blame] | 824 | dma_start_addr = (unsigned long)drv_data->tx; |
Mike Frysinger | b31e27a | 2009-04-06 19:00:39 -0700 | [diff] [blame] | 825 | cr |= BIT_CTL_TIMOD_DMA_TX; |
Sonic Zhang | 07612e5 | 2007-12-04 23:45:21 -0800 | [diff] [blame] | 826 | |
Mike Frysinger | 7aec356 | 2009-04-06 19:00:36 -0700 | [diff] [blame] | 827 | } else |
| 828 | BUG(); |
| 829 | |
Mike Frysinger | 11d6f59 | 2009-04-06 19:00:41 -0700 | [diff] [blame] | 830 | /* oh man, here there be monsters ... and i dont mean the |
| 831 | * fluffy cute ones from pixar, i mean the kind that'll eat |
| 832 | * your data, kick your dog, and love it all. do *not* try |
| 833 | * and change these lines unless you (1) heavily test DMA |
| 834 | * with SPI flashes on a loaded system (e.g. ping floods), |
| 835 | * (2) know just how broken the DMA engine interaction with |
| 836 | * the SPI peripheral is, and (3) have someone else to blame |
| 837 | * when you screw it all up anyways. |
| 838 | */ |
Mike Frysinger | 7aec356 | 2009-04-06 19:00:36 -0700 | [diff] [blame] | 839 | set_dma_start_addr(drv_data->dma_channel, dma_start_addr); |
Mike Frysinger | 11d6f59 | 2009-04-06 19:00:41 -0700 | [diff] [blame] | 840 | set_dma_config(drv_data->dma_channel, dma_config); |
| 841 | local_irq_save(flags); |
Mike Frysinger | a963ea8 | 2009-04-06 19:00:43 -0700 | [diff] [blame] | 842 | SSYNC(); |
Mike Frysinger | 11d6f59 | 2009-04-06 19:00:41 -0700 | [diff] [blame] | 843 | write_CTRL(drv_data, cr); |
Mike Frysinger | a963ea8 | 2009-04-06 19:00:43 -0700 | [diff] [blame] | 844 | enable_dma(drv_data->dma_channel); |
Mike Frysinger | 11d6f59 | 2009-04-06 19:00:41 -0700 | [diff] [blame] | 845 | dma_enable_irq(drv_data->dma_channel); |
| 846 | local_irq_restore(flags); |
Mike Frysinger | 7aec356 | 2009-04-06 19:00:36 -0700 | [diff] [blame] | 847 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 848 | } else { |
| 849 | /* IO mode write then read */ |
Bryan Wu | 88b4036 | 2007-05-21 18:32:16 +0800 | [diff] [blame] | 850 | dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n"); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 851 | |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 852 | /* we always use SPI_WRITE mode. SPI_READ mode |
| 853 | seems to have problems with setting up the |
| 854 | output value in TDBR prior to the transfer. */ |
| 855 | write_CTRL(drv_data, (cr | CFG_SPI_WRITE)); |
| 856 | |
Vitja Makarov | 8eeb12e | 2008-05-01 04:35:03 -0700 | [diff] [blame] | 857 | if (full_duplex) { |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 858 | /* full duplex mode */ |
| 859 | BUG_ON((drv_data->tx_end - drv_data->tx) != |
| 860 | (drv_data->rx_end - drv_data->rx)); |
Bryan Wu | 88b4036 | 2007-05-21 18:32:16 +0800 | [diff] [blame] | 861 | dev_dbg(&drv_data->pdev->dev, |
| 862 | "IO duplex: cr is 0x%x\n", cr); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 863 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 864 | drv_data->duplex(drv_data); |
| 865 | |
| 866 | if (drv_data->tx != drv_data->tx_end) |
| 867 | tranf_success = 0; |
| 868 | } else if (drv_data->tx != NULL) { |
| 869 | /* write only half duplex */ |
Bryan Wu | 131b17d | 2007-12-04 23:45:12 -0800 | [diff] [blame] | 870 | dev_dbg(&drv_data->pdev->dev, |
Bryan Wu | 88b4036 | 2007-05-21 18:32:16 +0800 | [diff] [blame] | 871 | "IO write: cr is 0x%x\n", cr); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 872 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 873 | drv_data->write(drv_data); |
| 874 | |
| 875 | if (drv_data->tx != drv_data->tx_end) |
| 876 | tranf_success = 0; |
| 877 | } else if (drv_data->rx != NULL) { |
| 878 | /* read only half duplex */ |
Bryan Wu | 131b17d | 2007-12-04 23:45:12 -0800 | [diff] [blame] | 879 | dev_dbg(&drv_data->pdev->dev, |
Bryan Wu | 88b4036 | 2007-05-21 18:32:16 +0800 | [diff] [blame] | 880 | "IO read: cr is 0x%x\n", cr); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 881 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 882 | drv_data->read(drv_data); |
| 883 | if (drv_data->rx != drv_data->rx_end) |
| 884 | tranf_success = 0; |
| 885 | } |
| 886 | |
| 887 | if (!tranf_success) { |
Bryan Wu | 131b17d | 2007-12-04 23:45:12 -0800 | [diff] [blame] | 888 | dev_dbg(&drv_data->pdev->dev, |
Bryan Wu | 88b4036 | 2007-05-21 18:32:16 +0800 | [diff] [blame] | 889 | "IO write error!\n"); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 890 | message->state = ERROR_STATE; |
| 891 | } else { |
| 892 | /* Update total byte transfered */ |
Mike Frysinger | ace3286 | 2009-04-06 19:00:34 -0700 | [diff] [blame] | 893 | message->actual_length += drv_data->len_in_bytes; |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 894 | /* Move to next transfer of this msg */ |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 895 | message->state = bfin_spi_next_transfer(drv_data); |
Yi Li | b9b2a76 | 2009-04-06 19:00:49 -0700 | [diff] [blame] | 896 | if (drv_data->cs_change) |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 897 | bfin_spi_cs_deactive(drv_data, chip); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 898 | } |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 899 | /* Schedule next transfer tasklet */ |
| 900 | tasklet_schedule(&drv_data->pump_transfers); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 901 | } |
| 902 | } |
| 903 | |
| 904 | /* pop a msg from queue and kick off real transfer */ |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 905 | static void bfin_spi_pump_messages(struct work_struct *work) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 906 | { |
Bryan Wu | 131b17d | 2007-12-04 23:45:12 -0800 | [diff] [blame] | 907 | struct driver_data *drv_data; |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 908 | unsigned long flags; |
| 909 | |
Bryan Wu | 131b17d | 2007-12-04 23:45:12 -0800 | [diff] [blame] | 910 | drv_data = container_of(work, struct driver_data, pump_messages); |
| 911 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 912 | /* Lock queue and check for queue work */ |
| 913 | spin_lock_irqsave(&drv_data->lock, flags); |
| 914 | if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) { |
| 915 | /* pumper kicked off but no work to do */ |
| 916 | drv_data->busy = 0; |
| 917 | spin_unlock_irqrestore(&drv_data->lock, flags); |
| 918 | return; |
| 919 | } |
| 920 | |
| 921 | /* Make sure we are not already running a message */ |
| 922 | if (drv_data->cur_msg) { |
| 923 | spin_unlock_irqrestore(&drv_data->lock, flags); |
| 924 | return; |
| 925 | } |
| 926 | |
| 927 | /* Extract head of queue */ |
| 928 | drv_data->cur_msg = list_entry(drv_data->queue.next, |
| 929 | struct spi_message, queue); |
Bryan Wu | 5fec5b5 | 2007-12-04 23:45:13 -0800 | [diff] [blame] | 930 | |
| 931 | /* Setup the SSP using the per chip configuration */ |
| 932 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 933 | bfin_spi_restore_state(drv_data); |
Bryan Wu | 5fec5b5 | 2007-12-04 23:45:13 -0800 | [diff] [blame] | 934 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 935 | list_del_init(&drv_data->cur_msg->queue); |
| 936 | |
| 937 | /* Initial message state */ |
| 938 | drv_data->cur_msg->state = START_STATE; |
| 939 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, |
| 940 | struct spi_transfer, transfer_list); |
| 941 | |
Bryan Wu | 5fec5b5 | 2007-12-04 23:45:13 -0800 | [diff] [blame] | 942 | dev_dbg(&drv_data->pdev->dev, "got a message to pump, " |
| 943 | "state is set to: baud %d, flag 0x%x, ctl 0x%x\n", |
| 944 | drv_data->cur_chip->baud, drv_data->cur_chip->flag, |
| 945 | drv_data->cur_chip->ctl_reg); |
Bryan Wu | 131b17d | 2007-12-04 23:45:12 -0800 | [diff] [blame] | 946 | |
| 947 | dev_dbg(&drv_data->pdev->dev, |
Bryan Wu | 88b4036 | 2007-05-21 18:32:16 +0800 | [diff] [blame] | 948 | "the first transfer len is %d\n", |
| 949 | drv_data->cur_transfer->len); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 950 | |
| 951 | /* Mark as busy and launch transfers */ |
| 952 | tasklet_schedule(&drv_data->pump_transfers); |
| 953 | |
| 954 | drv_data->busy = 1; |
| 955 | spin_unlock_irqrestore(&drv_data->lock, flags); |
| 956 | } |
| 957 | |
| 958 | /* |
| 959 | * got a msg to transfer, queue it in drv_data->queue. |
| 960 | * And kick off message pumper |
| 961 | */ |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 962 | static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 963 | { |
| 964 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); |
| 965 | unsigned long flags; |
| 966 | |
| 967 | spin_lock_irqsave(&drv_data->lock, flags); |
| 968 | |
| 969 | if (drv_data->run == QUEUE_STOPPED) { |
| 970 | spin_unlock_irqrestore(&drv_data->lock, flags); |
| 971 | return -ESHUTDOWN; |
| 972 | } |
| 973 | |
| 974 | msg->actual_length = 0; |
| 975 | msg->status = -EINPROGRESS; |
| 976 | msg->state = START_STATE; |
| 977 | |
Bryan Wu | 88b4036 | 2007-05-21 18:32:16 +0800 | [diff] [blame] | 978 | dev_dbg(&spi->dev, "adding an msg in transfer() \n"); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 979 | list_add_tail(&msg->queue, &drv_data->queue); |
| 980 | |
| 981 | if (drv_data->run == QUEUE_RUNNING && !drv_data->busy) |
| 982 | queue_work(drv_data->workqueue, &drv_data->pump_messages); |
| 983 | |
| 984 | spin_unlock_irqrestore(&drv_data->lock, flags); |
| 985 | |
| 986 | return 0; |
| 987 | } |
| 988 | |
Sonic Zhang | 12e17c4 | 2007-12-04 23:45:16 -0800 | [diff] [blame] | 989 | #define MAX_SPI_SSEL 7 |
| 990 | |
Mike Frysinger | 4160bde | 2009-04-06 19:00:40 -0700 | [diff] [blame] | 991 | static u16 ssel[][MAX_SPI_SSEL] = { |
Sonic Zhang | 12e17c4 | 2007-12-04 23:45:16 -0800 | [diff] [blame] | 992 | {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3, |
| 993 | P_SPI0_SSEL4, P_SPI0_SSEL5, |
| 994 | P_SPI0_SSEL6, P_SPI0_SSEL7}, |
| 995 | |
| 996 | {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3, |
| 997 | P_SPI1_SSEL4, P_SPI1_SSEL5, |
| 998 | P_SPI1_SSEL6, P_SPI1_SSEL7}, |
| 999 | |
| 1000 | {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3, |
| 1001 | P_SPI2_SSEL4, P_SPI2_SSEL5, |
| 1002 | P_SPI2_SSEL6, P_SPI2_SSEL7}, |
| 1003 | }; |
| 1004 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1005 | /* first setup for new devices */ |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1006 | static int bfin_spi_setup(struct spi_device *spi) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1007 | { |
| 1008 | struct bfin5xx_spi_chip *chip_info = NULL; |
| 1009 | struct chip_data *chip; |
| 1010 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); |
Michael Hennerich | 42c78b2 | 2009-04-06 19:00:51 -0700 | [diff] [blame] | 1011 | int ret; |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1012 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1013 | if (spi->bits_per_word != 8 && spi->bits_per_word != 16) |
| 1014 | return -EINVAL; |
| 1015 | |
| 1016 | /* Only alloc (or use chip_info) on first setup */ |
| 1017 | chip = spi_get_ctldata(spi); |
| 1018 | if (chip == NULL) { |
| 1019 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
| 1020 | if (!chip) |
| 1021 | return -ENOMEM; |
| 1022 | |
| 1023 | chip->enable_dma = 0; |
| 1024 | chip_info = spi->controller_data; |
| 1025 | } |
| 1026 | |
| 1027 | /* chip_info isn't always needed */ |
| 1028 | if (chip_info) { |
Mike Frysinger | 2ed3551 | 2007-12-04 23:45:14 -0800 | [diff] [blame] | 1029 | /* Make sure people stop trying to set fields via ctl_reg |
| 1030 | * when they should actually be using common SPI framework. |
| 1031 | * Currently we let through: WOM EMISO PSSE GM SZ TIMOD. |
| 1032 | * Not sure if a user actually needs/uses any of these, |
| 1033 | * but let's assume (for now) they do. |
| 1034 | */ |
| 1035 | if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) { |
| 1036 | dev_err(&spi->dev, "do not set bits in ctl_reg " |
| 1037 | "that the SPI framework manages\n"); |
| 1038 | return -EINVAL; |
| 1039 | } |
| 1040 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1041 | chip->enable_dma = chip_info->enable_dma != 0 |
| 1042 | && drv_data->master_info->enable_dma; |
| 1043 | chip->ctl_reg = chip_info->ctl_reg; |
| 1044 | chip->bits_per_word = chip_info->bits_per_word; |
| 1045 | chip->cs_change_per_word = chip_info->cs_change_per_word; |
| 1046 | chip->cs_chg_udelay = chip_info->cs_chg_udelay; |
Michael Hennerich | 42c78b2 | 2009-04-06 19:00:51 -0700 | [diff] [blame] | 1047 | chip->cs_gpio = chip_info->cs_gpio; |
Wolfgang Muees | 93b61bd | 2009-04-06 19:00:53 -0700 | [diff] [blame] | 1048 | chip->idle_tx_val = chip_info->idle_tx_val; |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1049 | } |
| 1050 | |
| 1051 | /* translate common spi framework into our register */ |
| 1052 | if (spi->mode & SPI_CPOL) |
| 1053 | chip->ctl_reg |= CPOL; |
| 1054 | if (spi->mode & SPI_CPHA) |
| 1055 | chip->ctl_reg |= CPHA; |
| 1056 | if (spi->mode & SPI_LSB_FIRST) |
| 1057 | chip->ctl_reg |= LSBF; |
| 1058 | /* we dont support running in slave mode (yet?) */ |
| 1059 | chip->ctl_reg |= MSTR; |
| 1060 | |
| 1061 | /* |
| 1062 | * if any one SPI chip is registered and wants DMA, request the |
| 1063 | * DMA channel for it |
| 1064 | */ |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 1065 | if (chip->enable_dma && !drv_data->dma_requested) { |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1066 | /* register dma irq handler */ |
Mike Frysinger | 59bfcc6 | 2009-04-06 19:00:37 -0700 | [diff] [blame] | 1067 | if (request_dma(drv_data->dma_channel, "BFIN_SPI_DMA") < 0) { |
Bryan Wu | 88b4036 | 2007-05-21 18:32:16 +0800 | [diff] [blame] | 1068 | dev_dbg(&spi->dev, |
| 1069 | "Unable to request BlackFin SPI DMA channel\n"); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1070 | return -ENODEV; |
| 1071 | } |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 1072 | if (set_dma_callback(drv_data->dma_channel, |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1073 | bfin_spi_dma_irq_handler, drv_data) < 0) { |
Bryan Wu | 88b4036 | 2007-05-21 18:32:16 +0800 | [diff] [blame] | 1074 | dev_dbg(&spi->dev, "Unable to set dma callback\n"); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1075 | return -EPERM; |
| 1076 | } |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 1077 | dma_disable_irq(drv_data->dma_channel); |
| 1078 | drv_data->dma_requested = 1; |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1079 | } |
| 1080 | |
| 1081 | /* |
| 1082 | * Notice: for blackfin, the speed_hz is the value of register |
| 1083 | * SPI_BAUD, not the real baudrate |
| 1084 | */ |
| 1085 | chip->baud = hz_to_spi_baud(spi->max_speed_hz); |
Yi Li | 2cf3683 | 2009-04-06 19:00:44 -0700 | [diff] [blame] | 1086 | chip->flag = 1 << (spi->chip_select); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1087 | chip->chip_select_num = spi->chip_select; |
| 1088 | |
Michael Hennerich | 42c78b2 | 2009-04-06 19:00:51 -0700 | [diff] [blame] | 1089 | if (chip->chip_select_num == 0) { |
| 1090 | ret = gpio_request(chip->cs_gpio, spi->modalias); |
| 1091 | if (ret) { |
| 1092 | if (drv_data->dma_requested) |
| 1093 | free_dma(drv_data->dma_channel); |
| 1094 | return ret; |
| 1095 | } |
| 1096 | gpio_direction_output(chip->cs_gpio, 1); |
| 1097 | } |
| 1098 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1099 | switch (chip->bits_per_word) { |
| 1100 | case 8: |
| 1101 | chip->n_bytes = 1; |
| 1102 | chip->width = CFG_SPI_WORDSIZE8; |
| 1103 | chip->read = chip->cs_change_per_word ? |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1104 | bfin_spi_u8_cs_chg_reader : bfin_spi_u8_reader; |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1105 | chip->write = chip->cs_change_per_word ? |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1106 | bfin_spi_u8_cs_chg_writer : bfin_spi_u8_writer; |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1107 | chip->duplex = chip->cs_change_per_word ? |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1108 | bfin_spi_u8_cs_chg_duplex : bfin_spi_u8_duplex; |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1109 | break; |
| 1110 | |
| 1111 | case 16: |
| 1112 | chip->n_bytes = 2; |
| 1113 | chip->width = CFG_SPI_WORDSIZE16; |
| 1114 | chip->read = chip->cs_change_per_word ? |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1115 | bfin_spi_u16_cs_chg_reader : bfin_spi_u16_reader; |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1116 | chip->write = chip->cs_change_per_word ? |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1117 | bfin_spi_u16_cs_chg_writer : bfin_spi_u16_writer; |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1118 | chip->duplex = chip->cs_change_per_word ? |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1119 | bfin_spi_u16_cs_chg_duplex : bfin_spi_u16_duplex; |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1120 | break; |
| 1121 | |
| 1122 | default: |
| 1123 | dev_err(&spi->dev, "%d bits_per_word is not supported\n", |
| 1124 | chip->bits_per_word); |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1125 | if (chip_info) |
| 1126 | kfree(chip); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1127 | return -ENODEV; |
| 1128 | } |
| 1129 | |
Joe Perches | 898eb71 | 2007-10-18 03:06:30 -0700 | [diff] [blame] | 1130 | dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n", |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1131 | spi->modalias, chip->width, chip->enable_dma); |
Bryan Wu | 88b4036 | 2007-05-21 18:32:16 +0800 | [diff] [blame] | 1132 | dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n", |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1133 | chip->ctl_reg, chip->flag); |
| 1134 | |
| 1135 | spi_set_ctldata(spi, chip); |
| 1136 | |
Sonic Zhang | 12e17c4 | 2007-12-04 23:45:16 -0800 | [diff] [blame] | 1137 | dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num); |
| 1138 | if ((chip->chip_select_num > 0) |
| 1139 | && (chip->chip_select_num <= spi->master->num_chipselect)) |
| 1140 | peripheral_request(ssel[spi->master->bus_num] |
Bryan Wu | aab0d83 | 2008-02-06 01:38:17 -0800 | [diff] [blame] | 1141 | [chip->chip_select_num-1], spi->modalias); |
Sonic Zhang | 12e17c4 | 2007-12-04 23:45:16 -0800 | [diff] [blame] | 1142 | |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1143 | bfin_spi_cs_deactive(drv_data, chip); |
Sonic Zhang | 07612e5 | 2007-12-04 23:45:21 -0800 | [diff] [blame] | 1144 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1145 | return 0; |
| 1146 | } |
| 1147 | |
| 1148 | /* |
| 1149 | * callback for spi framework. |
| 1150 | * clean driver specific data |
| 1151 | */ |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1152 | static void bfin_spi_cleanup(struct spi_device *spi) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1153 | { |
Mike Frysinger | 27bb9e7 | 2007-06-11 15:31:30 +0800 | [diff] [blame] | 1154 | struct chip_data *chip = spi_get_ctldata(spi); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1155 | |
Mike Frysinger | e7d02e3 | 2009-04-06 19:00:51 -0700 | [diff] [blame] | 1156 | if (!chip) |
| 1157 | return; |
| 1158 | |
Sonic Zhang | 12e17c4 | 2007-12-04 23:45:16 -0800 | [diff] [blame] | 1159 | if ((chip->chip_select_num > 0) |
| 1160 | && (chip->chip_select_num <= spi->master->num_chipselect)) |
| 1161 | peripheral_free(ssel[spi->master->bus_num] |
| 1162 | [chip->chip_select_num-1]); |
| 1163 | |
Michael Hennerich | 42c78b2 | 2009-04-06 19:00:51 -0700 | [diff] [blame] | 1164 | if (chip->chip_select_num == 0) |
| 1165 | gpio_free(chip->cs_gpio); |
| 1166 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1167 | kfree(chip); |
| 1168 | } |
| 1169 | |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1170 | static inline int bfin_spi_init_queue(struct driver_data *drv_data) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1171 | { |
| 1172 | INIT_LIST_HEAD(&drv_data->queue); |
| 1173 | spin_lock_init(&drv_data->lock); |
| 1174 | |
| 1175 | drv_data->run = QUEUE_STOPPED; |
| 1176 | drv_data->busy = 0; |
| 1177 | |
| 1178 | /* init transfer tasklet */ |
| 1179 | tasklet_init(&drv_data->pump_transfers, |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1180 | bfin_spi_pump_transfers, (unsigned long)drv_data); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1181 | |
| 1182 | /* init messages workqueue */ |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1183 | INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages); |
Kay Sievers | 6c7377a | 2009-03-24 16:38:21 -0700 | [diff] [blame] | 1184 | drv_data->workqueue = create_singlethread_workqueue( |
| 1185 | dev_name(drv_data->master->dev.parent)); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1186 | if (drv_data->workqueue == NULL) |
| 1187 | return -EBUSY; |
| 1188 | |
| 1189 | return 0; |
| 1190 | } |
| 1191 | |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1192 | static inline int bfin_spi_start_queue(struct driver_data *drv_data) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1193 | { |
| 1194 | unsigned long flags; |
| 1195 | |
| 1196 | spin_lock_irqsave(&drv_data->lock, flags); |
| 1197 | |
| 1198 | if (drv_data->run == QUEUE_RUNNING || drv_data->busy) { |
| 1199 | spin_unlock_irqrestore(&drv_data->lock, flags); |
| 1200 | return -EBUSY; |
| 1201 | } |
| 1202 | |
| 1203 | drv_data->run = QUEUE_RUNNING; |
| 1204 | drv_data->cur_msg = NULL; |
| 1205 | drv_data->cur_transfer = NULL; |
| 1206 | drv_data->cur_chip = NULL; |
| 1207 | spin_unlock_irqrestore(&drv_data->lock, flags); |
| 1208 | |
| 1209 | queue_work(drv_data->workqueue, &drv_data->pump_messages); |
| 1210 | |
| 1211 | return 0; |
| 1212 | } |
| 1213 | |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1214 | static inline int bfin_spi_stop_queue(struct driver_data *drv_data) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1215 | { |
| 1216 | unsigned long flags; |
| 1217 | unsigned limit = 500; |
| 1218 | int status = 0; |
| 1219 | |
| 1220 | spin_lock_irqsave(&drv_data->lock, flags); |
| 1221 | |
| 1222 | /* |
| 1223 | * This is a bit lame, but is optimized for the common execution path. |
| 1224 | * A wait_queue on the drv_data->busy could be used, but then the common |
| 1225 | * execution path (pump_messages) would be required to call wake_up or |
| 1226 | * friends on every SPI message. Do this instead |
| 1227 | */ |
| 1228 | drv_data->run = QUEUE_STOPPED; |
| 1229 | while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) { |
| 1230 | spin_unlock_irqrestore(&drv_data->lock, flags); |
| 1231 | msleep(10); |
| 1232 | spin_lock_irqsave(&drv_data->lock, flags); |
| 1233 | } |
| 1234 | |
| 1235 | if (!list_empty(&drv_data->queue) || drv_data->busy) |
| 1236 | status = -EBUSY; |
| 1237 | |
| 1238 | spin_unlock_irqrestore(&drv_data->lock, flags); |
| 1239 | |
| 1240 | return status; |
| 1241 | } |
| 1242 | |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1243 | static inline int bfin_spi_destroy_queue(struct driver_data *drv_data) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1244 | { |
| 1245 | int status; |
| 1246 | |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1247 | status = bfin_spi_stop_queue(drv_data); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1248 | if (status != 0) |
| 1249 | return status; |
| 1250 | |
| 1251 | destroy_workqueue(drv_data->workqueue); |
| 1252 | |
| 1253 | return 0; |
| 1254 | } |
| 1255 | |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1256 | static int __init bfin_spi_probe(struct platform_device *pdev) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1257 | { |
| 1258 | struct device *dev = &pdev->dev; |
| 1259 | struct bfin5xx_spi_master *platform_info; |
| 1260 | struct spi_master *master; |
| 1261 | struct driver_data *drv_data = 0; |
Bryan Wu | a32c691 | 2007-12-04 23:45:15 -0800 | [diff] [blame] | 1262 | struct resource *res; |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1263 | int status = 0; |
| 1264 | |
| 1265 | platform_info = dev->platform_data; |
| 1266 | |
| 1267 | /* Allocate master with space for drv_data */ |
| 1268 | master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); |
| 1269 | if (!master) { |
| 1270 | dev_err(&pdev->dev, "can not alloc spi_master\n"); |
| 1271 | return -ENOMEM; |
| 1272 | } |
Bryan Wu | 131b17d | 2007-12-04 23:45:12 -0800 | [diff] [blame] | 1273 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1274 | drv_data = spi_master_get_devdata(master); |
| 1275 | drv_data->master = master; |
| 1276 | drv_data->master_info = platform_info; |
| 1277 | drv_data->pdev = pdev; |
Bryan Wu | 003d922 | 2007-12-04 23:45:22 -0800 | [diff] [blame] | 1278 | drv_data->pin_req = platform_info->pin_req; |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1279 | |
David Brownell | e7db06b | 2009-06-17 16:26:04 -0700 | [diff] [blame] | 1280 | /* the spi->mode bits supported by this driver: */ |
| 1281 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; |
| 1282 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1283 | master->bus_num = pdev->id; |
| 1284 | master->num_chipselect = platform_info->num_chipselect; |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1285 | master->cleanup = bfin_spi_cleanup; |
| 1286 | master->setup = bfin_spi_setup; |
| 1287 | master->transfer = bfin_spi_transfer; |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1288 | |
Bryan Wu | a32c691 | 2007-12-04 23:45:15 -0800 | [diff] [blame] | 1289 | /* Find and map our resources */ |
| 1290 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1291 | if (res == NULL) { |
| 1292 | dev_err(dev, "Cannot get IORESOURCE_MEM\n"); |
| 1293 | status = -ENOENT; |
| 1294 | goto out_error_get_res; |
| 1295 | } |
| 1296 | |
hartleys | 74947b8 | 2009-12-14 22:33:43 +0000 | [diff] [blame] | 1297 | drv_data->regs_base = ioremap(res->start, resource_size(res)); |
Bryan Wu | f452126 | 2007-12-04 23:45:22 -0800 | [diff] [blame] | 1298 | if (drv_data->regs_base == NULL) { |
Bryan Wu | a32c691 | 2007-12-04 23:45:15 -0800 | [diff] [blame] | 1299 | dev_err(dev, "Cannot map IO\n"); |
| 1300 | status = -ENXIO; |
| 1301 | goto out_error_ioremap; |
| 1302 | } |
| 1303 | |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 1304 | drv_data->dma_channel = platform_get_irq(pdev, 0); |
| 1305 | if (drv_data->dma_channel < 0) { |
Bryan Wu | a32c691 | 2007-12-04 23:45:15 -0800 | [diff] [blame] | 1306 | dev_err(dev, "No DMA channel specified\n"); |
| 1307 | status = -ENOENT; |
| 1308 | goto out_error_no_dma_ch; |
| 1309 | } |
| 1310 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1311 | /* Initial and start queue */ |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1312 | status = bfin_spi_init_queue(drv_data); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1313 | if (status != 0) { |
Bryan Wu | a32c691 | 2007-12-04 23:45:15 -0800 | [diff] [blame] | 1314 | dev_err(dev, "problem initializing queue\n"); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1315 | goto out_error_queue_alloc; |
| 1316 | } |
Bryan Wu | a32c691 | 2007-12-04 23:45:15 -0800 | [diff] [blame] | 1317 | |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1318 | status = bfin_spi_start_queue(drv_data); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1319 | if (status != 0) { |
Bryan Wu | a32c691 | 2007-12-04 23:45:15 -0800 | [diff] [blame] | 1320 | dev_err(dev, "problem starting queue\n"); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1321 | goto out_error_queue_alloc; |
| 1322 | } |
| 1323 | |
Vitja Makarov | f9e522c | 2008-04-08 17:41:57 -0700 | [diff] [blame] | 1324 | status = peripheral_request_list(drv_data->pin_req, DRV_NAME); |
| 1325 | if (status != 0) { |
| 1326 | dev_err(&pdev->dev, ": Requesting Peripherals failed\n"); |
| 1327 | goto out_error_queue_alloc; |
| 1328 | } |
| 1329 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1330 | /* Register with the SPI framework */ |
| 1331 | platform_set_drvdata(pdev, drv_data); |
| 1332 | status = spi_register_master(master); |
| 1333 | if (status != 0) { |
Bryan Wu | a32c691 | 2007-12-04 23:45:15 -0800 | [diff] [blame] | 1334 | dev_err(dev, "problem registering spi master\n"); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1335 | goto out_error_queue_alloc; |
| 1336 | } |
Bryan Wu | a32c691 | 2007-12-04 23:45:15 -0800 | [diff] [blame] | 1337 | |
Bryan Wu | f452126 | 2007-12-04 23:45:22 -0800 | [diff] [blame] | 1338 | dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n", |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 1339 | DRV_DESC, DRV_VERSION, drv_data->regs_base, |
| 1340 | drv_data->dma_channel); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1341 | return status; |
| 1342 | |
Michael Hennerich | cc2f81a | 2007-12-04 23:45:13 -0800 | [diff] [blame] | 1343 | out_error_queue_alloc: |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1344 | bfin_spi_destroy_queue(drv_data); |
Bryan Wu | a32c691 | 2007-12-04 23:45:15 -0800 | [diff] [blame] | 1345 | out_error_no_dma_ch: |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 1346 | iounmap((void *) drv_data->regs_base); |
Bryan Wu | a32c691 | 2007-12-04 23:45:15 -0800 | [diff] [blame] | 1347 | out_error_ioremap: |
| 1348 | out_error_get_res: |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1349 | spi_master_put(master); |
Michael Hennerich | cc2f81a | 2007-12-04 23:45:13 -0800 | [diff] [blame] | 1350 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1351 | return status; |
| 1352 | } |
| 1353 | |
| 1354 | /* stop hardware and remove the driver */ |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1355 | static int __devexit bfin_spi_remove(struct platform_device *pdev) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1356 | { |
| 1357 | struct driver_data *drv_data = platform_get_drvdata(pdev); |
| 1358 | int status = 0; |
| 1359 | |
| 1360 | if (!drv_data) |
| 1361 | return 0; |
| 1362 | |
| 1363 | /* Remove the queue */ |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1364 | status = bfin_spi_destroy_queue(drv_data); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1365 | if (status != 0) |
| 1366 | return status; |
| 1367 | |
| 1368 | /* Disable the SSP at the peripheral and SOC level */ |
| 1369 | bfin_spi_disable(drv_data); |
| 1370 | |
| 1371 | /* Release DMA */ |
| 1372 | if (drv_data->master_info->enable_dma) { |
Bryan Wu | bb90eb0 | 2007-12-04 23:45:18 -0800 | [diff] [blame] | 1373 | if (dma_channel_active(drv_data->dma_channel)) |
| 1374 | free_dma(drv_data->dma_channel); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1375 | } |
| 1376 | |
| 1377 | /* Disconnect from the SPI framework */ |
| 1378 | spi_unregister_master(drv_data->master); |
| 1379 | |
Bryan Wu | 003d922 | 2007-12-04 23:45:22 -0800 | [diff] [blame] | 1380 | peripheral_free_list(drv_data->pin_req); |
Michael Hennerich | cc2f81a | 2007-12-04 23:45:13 -0800 | [diff] [blame] | 1381 | |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1382 | /* Prevent double remove */ |
| 1383 | platform_set_drvdata(pdev, NULL); |
| 1384 | |
| 1385 | return 0; |
| 1386 | } |
| 1387 | |
| 1388 | #ifdef CONFIG_PM |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1389 | static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1390 | { |
| 1391 | struct driver_data *drv_data = platform_get_drvdata(pdev); |
| 1392 | int status = 0; |
| 1393 | |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1394 | status = bfin_spi_stop_queue(drv_data); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1395 | if (status != 0) |
| 1396 | return status; |
| 1397 | |
| 1398 | /* stop hardware */ |
| 1399 | bfin_spi_disable(drv_data); |
| 1400 | |
| 1401 | return 0; |
| 1402 | } |
| 1403 | |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1404 | static int bfin_spi_resume(struct platform_device *pdev) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1405 | { |
| 1406 | struct driver_data *drv_data = platform_get_drvdata(pdev); |
| 1407 | int status = 0; |
| 1408 | |
| 1409 | /* Enable the SPI interface */ |
| 1410 | bfin_spi_enable(drv_data); |
| 1411 | |
| 1412 | /* Start the queue running */ |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1413 | status = bfin_spi_start_queue(drv_data); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1414 | if (status != 0) { |
| 1415 | dev_err(&pdev->dev, "problem starting queue (%d)\n", status); |
| 1416 | return status; |
| 1417 | } |
| 1418 | |
| 1419 | return 0; |
| 1420 | } |
| 1421 | #else |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1422 | #define bfin_spi_suspend NULL |
| 1423 | #define bfin_spi_resume NULL |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1424 | #endif /* CONFIG_PM */ |
| 1425 | |
Kay Sievers | 7e38c3c | 2008-04-10 21:29:20 -0700 | [diff] [blame] | 1426 | MODULE_ALIAS("platform:bfin-spi"); |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1427 | static struct platform_driver bfin_spi_driver = { |
David Brownell | fc3ba95 | 2007-08-30 23:56:24 -0700 | [diff] [blame] | 1428 | .driver = { |
Bryan Wu | a32c691 | 2007-12-04 23:45:15 -0800 | [diff] [blame] | 1429 | .name = DRV_NAME, |
Bryan Wu | 88b4036 | 2007-05-21 18:32:16 +0800 | [diff] [blame] | 1430 | .owner = THIS_MODULE, |
| 1431 | }, |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1432 | .suspend = bfin_spi_suspend, |
| 1433 | .resume = bfin_spi_resume, |
| 1434 | .remove = __devexit_p(bfin_spi_remove), |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1435 | }; |
| 1436 | |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1437 | static int __init bfin_spi_init(void) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1438 | { |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1439 | return platform_driver_probe(&bfin_spi_driver, bfin_spi_probe); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1440 | } |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1441 | module_init(bfin_spi_init); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1442 | |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1443 | static void __exit bfin_spi_exit(void) |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1444 | { |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1445 | platform_driver_unregister(&bfin_spi_driver); |
Wu, Bryan | a5f6abd | 2007-05-06 14:50:34 -0700 | [diff] [blame] | 1446 | } |
Mike Frysinger | 138f97c | 2009-04-06 19:00:50 -0700 | [diff] [blame] | 1447 | module_exit(bfin_spi_exit); |