Steve Hodgson | f0d37f4 | 2009-11-29 15:15:07 +0000 | [diff] [blame] | 1 | /**************************************************************************** |
| 2 | * Driver for Solarflare Solarstorm network controllers and boards |
Ben Hutchings | 0a6f40c | 2011-02-25 00:01:34 +0000 | [diff] [blame] | 3 | * Copyright 2009-2011 Solarflare Communications Inc. |
Steve Hodgson | f0d37f4 | 2009-11-29 15:15:07 +0000 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License version 2 as published |
| 7 | * by the Free Software Foundation, incorporated herein by reference. |
| 8 | */ |
| 9 | |
| 10 | |
| 11 | #ifndef MCDI_PCOL_H |
| 12 | #define MCDI_PCOL_H |
| 13 | |
| 14 | /* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */ |
| 15 | /* Power-on reset state */ |
| 16 | #define MC_FW_STATE_POR (1) |
| 17 | /* If this is set in MC_RESET_STATE_REG then it should be |
| 18 | * possible to jump into IMEM without loading code from flash. */ |
| 19 | #define MC_FW_WARM_BOOT_OK (2) |
| 20 | /* The MC main image has started to boot. */ |
| 21 | #define MC_FW_STATE_BOOTING (4) |
| 22 | /* The Scheduler has started. */ |
| 23 | #define MC_FW_STATE_SCHED (8) |
| 24 | |
| 25 | /* Values to be written to the per-port status dword in shared |
| 26 | * memory on reboot and assert */ |
| 27 | #define MC_STATUS_DWORD_REBOOT (0xb007b007) |
| 28 | #define MC_STATUS_DWORD_ASSERT (0xdeaddead) |
| 29 | |
| 30 | /* The current version of the MCDI protocol. |
| 31 | * |
| 32 | * Note that the ROM burnt into the card only talks V0, so at the very |
| 33 | * least every driver must support version 0 and MCDI_PCOL_VERSION |
| 34 | */ |
| 35 | #define MCDI_PCOL_VERSION 1 |
| 36 | |
| 37 | /** |
| 38 | * MCDI version 1 |
| 39 | * |
| 40 | * Each MCDI request starts with an MCDI_HEADER, which is a 32byte |
| 41 | * structure, filled in by the client. |
| 42 | * |
| 43 | * 0 7 8 16 20 22 23 24 31 |
| 44 | * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS | |
| 45 | * | | | |
| 46 | * | | \--- Response |
| 47 | * | \------- Error |
| 48 | * \------------------------------ Resync (always set) |
| 49 | * |
| 50 | * The client writes it's request into MC shared memory, and rings the |
| 51 | * doorbell. Each request is completed by either by the MC writting |
| 52 | * back into shared memory, or by writting out an event. |
| 53 | * |
| 54 | * All MCDI commands support completion by shared memory response. Each |
| 55 | * request may also contain additional data (accounted for by HEADER.LEN), |
| 56 | * and some response's may also contain additional data (again, accounted |
| 57 | * for by HEADER.LEN). |
| 58 | * |
| 59 | * Some MCDI commands support completion by event, in which any associated |
| 60 | * response data is included in the event. |
| 61 | * |
| 62 | * The protocol requires one response to be delivered for every request, a |
| 63 | * request should not be sent unless the response for the previous request |
| 64 | * has been received (either by polling shared memory, or by receiving |
| 65 | * an event). |
| 66 | */ |
| 67 | |
| 68 | /** Request/Response structure */ |
| 69 | #define MCDI_HEADER_OFST 0 |
| 70 | #define MCDI_HEADER_CODE_LBN 0 |
| 71 | #define MCDI_HEADER_CODE_WIDTH 7 |
| 72 | #define MCDI_HEADER_RESYNC_LBN 7 |
| 73 | #define MCDI_HEADER_RESYNC_WIDTH 1 |
| 74 | #define MCDI_HEADER_DATALEN_LBN 8 |
| 75 | #define MCDI_HEADER_DATALEN_WIDTH 8 |
| 76 | #define MCDI_HEADER_SEQ_LBN 16 |
| 77 | #define MCDI_HEADER_RSVD_LBN 20 |
| 78 | #define MCDI_HEADER_RSVD_WIDTH 2 |
| 79 | #define MCDI_HEADER_SEQ_WIDTH 4 |
| 80 | #define MCDI_HEADER_ERROR_LBN 22 |
| 81 | #define MCDI_HEADER_ERROR_WIDTH 1 |
| 82 | #define MCDI_HEADER_RESPONSE_LBN 23 |
| 83 | #define MCDI_HEADER_RESPONSE_WIDTH 1 |
| 84 | #define MCDI_HEADER_XFLAGS_LBN 24 |
| 85 | #define MCDI_HEADER_XFLAGS_WIDTH 8 |
| 86 | /* Request response using event */ |
| 87 | #define MCDI_HEADER_XFLAGS_EVREQ 0x01 |
| 88 | |
| 89 | /* Maximum number of payload bytes */ |
| 90 | #define MCDI_CTL_SDU_LEN_MAX 0xfc |
| 91 | |
| 92 | /* The MC can generate events for two reasons: |
| 93 | * - To complete a shared memory request if XFLAGS_EVREQ was set |
| 94 | * - As a notification (link state, i2c event), controlled |
| 95 | * via MC_CMD_LOG_CTRL |
| 96 | * |
| 97 | * Both events share a common structure: |
| 98 | * |
| 99 | * 0 32 33 36 44 52 60 |
| 100 | * | Data | Cont | Level | Src | Code | Rsvd | |
| 101 | * | |
| 102 | * \ There is another event pending in this notification |
| 103 | * |
| 104 | * If Code==CMDDONE, then the fields are further interpreted as: |
| 105 | * |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 106 | * - LEVEL==INFO Command succeeded |
Steve Hodgson | f0d37f4 | 2009-11-29 15:15:07 +0000 | [diff] [blame] | 107 | * - LEVEL==ERR Command failed |
| 108 | * |
| 109 | * 0 8 16 24 32 |
| 110 | * | Seq | Datalen | Errno | Rsvd | |
| 111 | * |
| 112 | * These fields are taken directly out of the standard MCDI header, i.e., |
| 113 | * LEVEL==ERR, Datalen == 0 => Reboot |
| 114 | * |
| 115 | * Events can be squirted out of the UART (using LOG_CTRL) without a |
| 116 | * MCDI header. An event can be distinguished from a MCDI response by |
| 117 | * examining the first byte which is 0xc0. This corresponds to the |
| 118 | * non-existent MCDI command MC_CMD_DEBUG_LOG. |
| 119 | * |
| 120 | * 0 7 8 |
| 121 | * | command | Resync | = 0xc0 |
| 122 | * |
| 123 | * Since the event is written in big-endian byte order, this works |
| 124 | * providing bits 56-63 of the event are 0xc0. |
| 125 | * |
| 126 | * 56 60 63 |
| 127 | * | Rsvd | Code | = 0xc0 |
| 128 | * |
| 129 | * Which means for convenience the event code is 0xc for all MC |
| 130 | * generated events. |
| 131 | */ |
| 132 | #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc |
| 133 | |
| 134 | #define MCDI_EVENT_DATA_LBN 0 |
| 135 | #define MCDI_EVENT_DATA_WIDTH 32 |
| 136 | #define MCDI_EVENT_CONT_LBN 32 |
| 137 | #define MCDI_EVENT_CONT_WIDTH 1 |
| 138 | #define MCDI_EVENT_LEVEL_LBN 33 |
| 139 | #define MCDI_EVENT_LEVEL_WIDTH 3 |
| 140 | #define MCDI_EVENT_LEVEL_INFO (0) |
| 141 | #define MCDI_EVENT_LEVEL_WARN (1) |
| 142 | #define MCDI_EVENT_LEVEL_ERR (2) |
| 143 | #define MCDI_EVENT_LEVEL_FATAL (3) |
| 144 | #define MCDI_EVENT_SRC_LBN 36 |
| 145 | #define MCDI_EVENT_SRC_WIDTH 8 |
| 146 | #define MCDI_EVENT_CODE_LBN 44 |
| 147 | #define MCDI_EVENT_CODE_WIDTH 8 |
| 148 | #define MCDI_EVENT_CODE_BADSSERT (1) |
| 149 | #define MCDI_EVENT_CODE_PMNOTICE (2) |
| 150 | #define MCDI_EVENT_CODE_CMDDONE (3) |
| 151 | #define MCDI_EVENT_CMDDONE_SEQ_LBN 0 |
| 152 | #define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8 |
| 153 | #define MCDI_EVENT_CMDDONE_DATALEN_LBN 8 |
| 154 | #define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8 |
| 155 | #define MCDI_EVENT_CMDDONE_ERRNO_LBN 16 |
| 156 | #define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8 |
| 157 | #define MCDI_EVENT_CODE_LINKCHANGE (4) |
| 158 | #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0 |
| 159 | #define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16 |
| 160 | #define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16 |
| 161 | #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4 |
| 162 | #define MCDI_EVENT_LINKCHANGE_SPEED_100M 1 |
| 163 | #define MCDI_EVENT_LINKCHANGE_SPEED_1G 2 |
| 164 | #define MCDI_EVENT_LINKCHANGE_SPEED_10G 3 |
| 165 | #define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20 |
| 166 | #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4 |
| 167 | #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24 |
| 168 | #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8 |
| 169 | #define MCDI_EVENT_CODE_SENSOREVT (5) |
| 170 | #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0 |
| 171 | #define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8 |
| 172 | #define MCDI_EVENT_SENSOREVT_STATE_LBN 8 |
| 173 | #define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8 |
| 174 | #define MCDI_EVENT_SENSOREVT_VALUE_LBN 16 |
| 175 | #define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16 |
| 176 | #define MCDI_EVENT_CODE_SCHEDERR (6) |
| 177 | #define MCDI_EVENT_CODE_REBOOT (7) |
| 178 | #define MCDI_EVENT_CODE_MAC_STATS_DMA (8) |
| 179 | #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0 |
| 180 | #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32 |
| 181 | |
| 182 | /* Non-existent command target */ |
| 183 | #define MC_CMD_ERR_ENOENT 2 |
| 184 | /* assert() has killed the MC */ |
| 185 | #define MC_CMD_ERR_EINTR 4 |
| 186 | /* Caller does not hold required locks */ |
| 187 | #define MC_CMD_ERR_EACCES 13 |
| 188 | /* Resource is currently unavailable (e.g. lock contention) */ |
| 189 | #define MC_CMD_ERR_EBUSY 16 |
| 190 | /* Invalid argument to target */ |
| 191 | #define MC_CMD_ERR_EINVAL 22 |
| 192 | /* Non-recursive resource is already acquired */ |
| 193 | #define MC_CMD_ERR_EDEADLK 35 |
| 194 | /* Operation not implemented */ |
| 195 | #define MC_CMD_ERR_ENOSYS 38 |
| 196 | /* Operation timed out */ |
| 197 | #define MC_CMD_ERR_ETIME 62 |
| 198 | |
| 199 | #define MC_CMD_ERR_CODE_OFST 0 |
| 200 | |
| 201 | |
| 202 | /* MC_CMD_READ32: (debug, variadic out) |
| 203 | * Read multiple 32byte words from MC memory |
| 204 | */ |
| 205 | #define MC_CMD_READ32 0x01 |
| 206 | #define MC_CMD_READ32_IN_LEN 8 |
| 207 | #define MC_CMD_READ32_IN_ADDR_OFST 0 |
| 208 | #define MC_CMD_READ32_IN_NUMWORDS_OFST 4 |
| 209 | #define MC_CMD_READ32_OUT_LEN(_numwords) \ |
| 210 | (4 * (_numwords)) |
| 211 | #define MC_CMD_READ32_OUT_BUFFER_OFST 0 |
| 212 | |
| 213 | /* MC_CMD_WRITE32: (debug, variadic in) |
| 214 | * Write multiple 32byte words to MC memory |
| 215 | */ |
| 216 | #define MC_CMD_WRITE32 0x02 |
| 217 | #define MC_CMD_WRITE32_IN_LEN(_numwords) (((_numwords) * 4) + 4) |
| 218 | #define MC_CMD_WRITE32_IN_ADDR_OFST 0 |
| 219 | #define MC_CMD_WRITE32_IN_BUFFER_OFST 4 |
| 220 | #define MC_CMD_WRITE32_OUT_LEN 0 |
| 221 | |
| 222 | /* MC_CMD_COPYCODE: (debug) |
| 223 | * Copy MC code between two locations and jump |
| 224 | */ |
| 225 | #define MC_CMD_COPYCODE 0x03 |
| 226 | #define MC_CMD_COPYCODE_IN_LEN 16 |
| 227 | #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0 |
| 228 | #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4 |
| 229 | #define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8 |
| 230 | #define MC_CMD_COPYCODE_IN_JUMP_OFST 12 |
| 231 | /* Control should return to the caller rather than jumping */ |
| 232 | #define MC_CMD_COPYCODE_JUMP_NONE 1 |
| 233 | #define MC_CMD_COPYCODE_OUT_LEN 0 |
| 234 | |
| 235 | /* MC_CMD_SET_FUNC: (debug) |
| 236 | * Select function for function-specific commands. |
| 237 | */ |
| 238 | #define MC_CMD_SET_FUNC 0x04 |
| 239 | #define MC_CMD_SET_FUNC_IN_LEN 4 |
| 240 | #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0 |
| 241 | #define MC_CMD_SET_FUNC_OUT_LEN 0 |
| 242 | |
| 243 | /* MC_CMD_GET_BOOT_STATUS: |
| 244 | * Get the instruction address from which the MC booted. |
| 245 | */ |
| 246 | #define MC_CMD_GET_BOOT_STATUS 0x05 |
| 247 | #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0 |
| 248 | #define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8 |
| 249 | #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0 |
| 250 | #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4 |
| 251 | /* Reboot caused by watchdog */ |
| 252 | #define MC_CMD_GET_BOOT_STATUS_FLAGS_WATCHDOG_LBN (0) |
| 253 | #define MC_CMD_GET_BOOT_STATUS_FLAGS_WATCHDOG_WIDTH (1) |
| 254 | /* MC booted from primary flash partition */ |
| 255 | #define MC_CMD_GET_BOOT_STATUS_FLAGS_PRIMARY_LBN (1) |
| 256 | #define MC_CMD_GET_BOOT_STATUS_FLAGS_PRIMARY_WIDTH (1) |
| 257 | /* MC booted from backup flash partition */ |
| 258 | #define MC_CMD_GET_BOOT_STATUS_FLAGS_BACKUP_LBN (2) |
| 259 | #define MC_CMD_GET_BOOT_STATUS_FLAGS_BACKUP_WIDTH (1) |
| 260 | |
| 261 | /* MC_CMD_GET_ASSERTS: (debug, variadic out) |
| 262 | * Get (and optionally clear) the current assertion status. |
| 263 | * |
| 264 | * Only OUT.GLOBAL_FLAGS is guaranteed to exist in the completion |
| 265 | * payload. The other fields will only be present if |
| 266 | * OUT.GLOBAL_FLAGS != NO_FAILS |
| 267 | */ |
| 268 | #define MC_CMD_GET_ASSERTS 0x06 |
| 269 | #define MC_CMD_GET_ASSERTS_IN_LEN 4 |
| 270 | #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0 |
| 271 | #define MC_CMD_GET_ASSERTS_OUT_LEN 140 |
| 272 | /* Assertion status flag */ |
| 273 | #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0 |
| 274 | /*! No assertions have failed. */ |
| 275 | #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 1 |
| 276 | /*! A system-level assertion has failed. */ |
| 277 | #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 2 |
| 278 | /*! A thread-level assertion has failed. */ |
| 279 | #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 3 |
| 280 | /*! The system was reset by the watchdog. */ |
| 281 | #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 4 |
| 282 | /* Failing PC value */ |
| 283 | #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4 |
| 284 | /* Saved GP regs */ |
| 285 | #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8 |
| 286 | #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_LEN 124 |
| 287 | /* Failing thread address */ |
| 288 | #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132 |
| 289 | |
| 290 | /* MC_CMD_LOG_CTRL: |
| 291 | * Determine the output stream for various events and messages |
| 292 | */ |
| 293 | #define MC_CMD_LOG_CTRL 0x07 |
| 294 | #define MC_CMD_LOG_CTRL_IN_LEN 8 |
| 295 | #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0 |
| 296 | #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART (1) |
| 297 | #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ (2) |
| 298 | #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4 |
| 299 | #define MC_CMD_LOG_CTRL_OUT_LEN 0 |
| 300 | |
| 301 | /* MC_CMD_GET_VERSION: |
| 302 | * Get version information about the MC firmware |
| 303 | */ |
| 304 | #define MC_CMD_GET_VERSION 0x08 |
| 305 | #define MC_CMD_GET_VERSION_IN_LEN 0 |
| 306 | #define MC_CMD_GET_VERSION_V0_OUT_LEN 4 |
| 307 | #define MC_CMD_GET_VERSION_V1_OUT_LEN 32 |
| 308 | #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 |
| 309 | /* Reserved version number to indicate "any" version. */ |
| 310 | #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff |
| 311 | /* The version response of a boot ROM awaiting rescue */ |
| 312 | #define MC_CMD_GET_VERSION_OUT_FIRMWARE_BOOTROM 0xb0070000 |
| 313 | #define MC_CMD_GET_VERSION_V1_OUT_PCOL_OFST 4 |
| 314 | /* 128bit mask of functions supported by the current firmware */ |
| 315 | #define MC_CMD_GET_VERSION_V1_OUT_SUPPORTED_FUNCS_OFST 8 |
| 316 | /* The command set exported by the boot ROM (MCDI v0) */ |
| 317 | #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \ |
| 318 | (1 << MC_CMD_READ32) | \ |
| 319 | (1 << MC_CMD_WRITE32) | \ |
| 320 | (1 << MC_CMD_COPYCODE) | \ |
| 321 | (1 << MC_CMD_GET_VERSION), \ |
| 322 | 0, 0, 0 } |
| 323 | #define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24 |
| 324 | |
| 325 | /* Vectors in the boot ROM */ |
| 326 | /* Point to the copycode entry point. */ |
| 327 | #define MC_BOOTROM_COPYCODE_VEC (0x7f4) |
| 328 | /* Points to the recovery mode entry point. */ |
| 329 | #define MC_BOOTROM_NOFLASH_VEC (0x7f8) |
| 330 | |
| 331 | /* Test execution limits */ |
| 332 | #define MC_TESTEXEC_VARIANT_COUNT 16 |
| 333 | #define MC_TESTEXEC_RESULT_COUNT 7 |
| 334 | |
| 335 | /* MC_CMD_SET_TESTVARS: (debug, variadic in) |
| 336 | * Write variant words for test. |
| 337 | * |
| 338 | * The user supplies a bitmap of the variants they wish to set. |
| 339 | * They must ensure that IN.LEN >= 4 + 4 * ffs(BITMAP) |
| 340 | */ |
| 341 | #define MC_CMD_SET_TESTVARS 0x09 |
| 342 | #define MC_CMD_SET_TESTVARS_IN_LEN(_numwords) \ |
| 343 | (4 + 4*(_numwords)) |
| 344 | #define MC_CMD_SET_TESTVARS_IN_ARGS_BITMAP_OFST 0 |
| 345 | /* Up to MC_TESTEXEC_VARIANT_COUNT of 32byte words start here */ |
| 346 | #define MC_CMD_SET_TESTVARS_IN_ARGS_BUFFER_OFST 4 |
| 347 | #define MC_CMD_SET_TESTVARS_OUT_LEN 0 |
| 348 | |
| 349 | /* MC_CMD_GET_TESTRCS: (debug, variadic out) |
| 350 | * Return result words from test. |
| 351 | */ |
| 352 | #define MC_CMD_GET_TESTRCS 0x0a |
| 353 | #define MC_CMD_GET_TESTRCS_IN_LEN 4 |
| 354 | #define MC_CMD_GET_TESTRCS_IN_NUMWORDS_OFST 0 |
| 355 | #define MC_CMD_GET_TESTRCS_OUT_LEN(_numwords) \ |
| 356 | (4 * (_numwords)) |
| 357 | #define MC_CMD_GET_TESTRCS_OUT_BUFFER_OFST 0 |
| 358 | |
| 359 | /* MC_CMD_RUN_TEST: (debug) |
| 360 | * Run the test exported by this firmware image |
| 361 | */ |
| 362 | #define MC_CMD_RUN_TEST 0x0b |
| 363 | #define MC_CMD_RUN_TEST_IN_LEN 0 |
| 364 | #define MC_CMD_RUN_TEST_OUT_LEN 0 |
| 365 | |
| 366 | /* MC_CMD_CSR_READ32: (debug, variadic out) |
| 367 | * Read 32bit words from the indirect memory map |
| 368 | */ |
| 369 | #define MC_CMD_CSR_READ32 0x0c |
| 370 | #define MC_CMD_CSR_READ32_IN_LEN 12 |
| 371 | #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0 |
| 372 | #define MC_CMD_CSR_READ32_IN_STEP_OFST 4 |
| 373 | #define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8 |
| 374 | #define MC_CMD_CSR_READ32_OUT_LEN(_numwords) \ |
| 375 | (((_numwords) * 4) + 4) |
| 376 | /* IN.NUMWORDS of 32bit words start here */ |
| 377 | #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0 |
| 378 | #define MC_CMD_CSR_READ32_OUT_IREG_STATUS_OFST(_numwords) \ |
| 379 | ((_numwords) * 4) |
| 380 | |
| 381 | /* MC_CMD_CSR_WRITE32: (debug, variadic in) |
| 382 | * Write 32bit dwords to the indirect memory map |
| 383 | */ |
| 384 | #define MC_CMD_CSR_WRITE32 0x0d |
| 385 | #define MC_CMD_CSR_WRITE32_IN_LEN(_numwords) \ |
| 386 | (((_numwords) * 4) + 8) |
| 387 | #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0 |
| 388 | #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4 |
| 389 | /* Multiple 32bit words of data to write start here */ |
| 390 | #define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8 |
| 391 | #define MC_CMD_CSR_WRITE32_OUT_LEN 4 |
| 392 | #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0 |
| 393 | |
| 394 | /* MC_CMD_JTAG_WORK: (debug, fpga only) |
| 395 | * Process JTAG work buffer for RBF acceleration. |
| 396 | * |
| 397 | * Host: bit count, (up to) 32 words of data to clock out to JTAG |
| 398 | * (bits 1,0=TMS,TDO for first bit; bits 3,2=TMS,TDO for second bit, etc.) |
| 399 | * MC: bit count, (up to) 32 words of data clocked in from JTAG |
| 400 | * (bit 0=TDI for first bit, bit 1=TDI for second bit, etc.; [31:16] unused) |
| 401 | */ |
| 402 | #define MC_CMD_JTAG_WORK 0x0e |
| 403 | |
| 404 | /* MC_CMD_STACKINFO: (debug, variadic out) |
| 405 | * Get stack information |
| 406 | * |
| 407 | * Host: nothing |
| 408 | * MC: (thread ptr, stack size, free space) for each thread in system |
| 409 | */ |
| 410 | #define MC_CMD_STACKINFO 0x0f |
| 411 | |
| 412 | /* MC_CMD_MDIO_READ: |
| 413 | * MDIO register read |
| 414 | */ |
| 415 | #define MC_CMD_MDIO_READ 0x10 |
| 416 | #define MC_CMD_MDIO_READ_IN_LEN 16 |
| 417 | #define MC_CMD_MDIO_READ_IN_BUS_OFST 0 |
| 418 | #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4 |
| 419 | #define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8 |
| 420 | #define MC_CMD_MDIO_READ_IN_ADDR_OFST 12 |
| 421 | #define MC_CMD_MDIO_READ_OUT_LEN 8 |
| 422 | #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0 |
| 423 | #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4 |
| 424 | |
| 425 | /* MC_CMD_MDIO_WRITE: |
| 426 | * MDIO register write |
| 427 | */ |
| 428 | #define MC_CMD_MDIO_WRITE 0x11 |
| 429 | #define MC_CMD_MDIO_WRITE_IN_LEN 20 |
| 430 | #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0 |
| 431 | #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4 |
| 432 | #define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8 |
| 433 | #define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12 |
| 434 | #define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16 |
| 435 | #define MC_CMD_MDIO_WRITE_OUT_LEN 4 |
| 436 | #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0 |
| 437 | |
| 438 | /* By default all the MCDI MDIO operations perform clause45 mode. |
| 439 | * If you want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. |
| 440 | */ |
| 441 | #define MC_CMD_MDIO_CLAUSE22 32 |
| 442 | |
| 443 | /* There are two MDIO buses: one for the internal PHY, and one for external |
| 444 | * devices. |
| 445 | */ |
| 446 | #define MC_CMD_MDIO_BUS_INTERNAL 0 |
| 447 | #define MC_CMD_MDIO_BUS_EXTERNAL 1 |
| 448 | |
| 449 | /* The MDIO commands return the raw status bits from the MDIO block. A "good" |
| 450 | * transaction should have the DONE bit set and all other bits clear. |
| 451 | */ |
| 452 | #define MC_CMD_MDIO_STATUS_GOOD 0x08 |
| 453 | |
| 454 | |
| 455 | /* MC_CMD_DBI_WRITE: (debug) |
| 456 | * Write DBI register(s) |
| 457 | * |
| 458 | * Host: address, byte-enables (and VF selection, and cs2 flag), |
| 459 | * value [,address ...] |
| 460 | * MC: nothing |
| 461 | */ |
| 462 | #define MC_CMD_DBI_WRITE 0x12 |
| 463 | #define MC_CMD_DBI_WRITE_IN_LEN(_numwords) \ |
| 464 | (12 * (_numwords)) |
| 465 | #define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(_word) \ |
| 466 | (((_word) * 12) + 0) |
| 467 | #define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(_word) \ |
| 468 | (((_word) * 12) + 4) |
| 469 | #define MC_CMD_DBI_WRITE_IN_VALUE_OFST(_word) \ |
| 470 | (((_word) * 12) + 8) |
| 471 | #define MC_CMD_DBI_WRITE_OUT_LEN 0 |
| 472 | |
| 473 | /* MC_CMD_DBI_READ: (debug) |
| 474 | * Read DBI register(s) |
| 475 | * |
| 476 | * Host: address, [,address ...] |
| 477 | * MC: value [,value ...] |
| 478 | * (note: this does not support reading from VFs, but is retained for backwards |
| 479 | * compatibility; see MC_CMD_DBI_READX below) |
| 480 | */ |
| 481 | #define MC_CMD_DBI_READ 0x13 |
| 482 | #define MC_CMD_DBI_READ_IN_LEN(_numwords) \ |
| 483 | (4 * (_numwords)) |
| 484 | #define MC_CMD_DBI_READ_OUT_LEN(_numwords) \ |
| 485 | (4 * (_numwords)) |
| 486 | |
| 487 | /* MC_CMD_PORT_READ32: (debug) |
| 488 | * Read a 32-bit register from the indirect port register map. |
| 489 | * |
| 490 | * The port to access is implied by the Shared memory channel used. |
| 491 | */ |
| 492 | #define MC_CMD_PORT_READ32 0x14 |
| 493 | #define MC_CMD_PORT_READ32_IN_LEN 4 |
| 494 | #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0 |
| 495 | #define MC_CMD_PORT_READ32_OUT_LEN 8 |
| 496 | #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0 |
| 497 | #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4 |
| 498 | |
| 499 | /* MC_CMD_PORT_WRITE32: (debug) |
| 500 | * Write a 32-bit register to the indirect port register map. |
| 501 | * |
| 502 | * The port to access is implied by the Shared memory channel used. |
| 503 | */ |
| 504 | #define MC_CMD_PORT_WRITE32 0x15 |
| 505 | #define MC_CMD_PORT_WRITE32_IN_LEN 8 |
| 506 | #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0 |
| 507 | #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4 |
| 508 | #define MC_CMD_PORT_WRITE32_OUT_LEN 4 |
| 509 | #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0 |
| 510 | |
| 511 | /* MC_CMD_PORT_READ128: (debug) |
| 512 | * Read a 128-bit register from indirect port register map |
| 513 | * |
| 514 | * The port to access is implied by the Shared memory channel used. |
| 515 | */ |
| 516 | #define MC_CMD_PORT_READ128 0x16 |
| 517 | #define MC_CMD_PORT_READ128_IN_LEN 4 |
| 518 | #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0 |
| 519 | #define MC_CMD_PORT_READ128_OUT_LEN 20 |
| 520 | #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0 |
| 521 | #define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16 |
| 522 | |
| 523 | /* MC_CMD_PORT_WRITE128: (debug) |
| 524 | * Write a 128-bit register to indirect port register map. |
| 525 | * |
| 526 | * The port to access is implied by the Shared memory channel used. |
| 527 | */ |
| 528 | #define MC_CMD_PORT_WRITE128 0x17 |
| 529 | #define MC_CMD_PORT_WRITE128_IN_LEN 20 |
| 530 | #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0 |
| 531 | #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4 |
| 532 | #define MC_CMD_PORT_WRITE128_OUT_LEN 4 |
| 533 | #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0 |
| 534 | |
| 535 | /* MC_CMD_GET_BOARD_CFG: |
| 536 | * Returns the MC firmware configuration structure |
| 537 | * |
| 538 | * The FW_SUBTYPE_LIST contains a 16-bit value for each of the 12 types of |
| 539 | * NVRAM area. The values are defined in the firmware/mc/platform/<xxx>.c file |
| 540 | * for a specific board type, but otherwise have no meaning to the MC; they |
| 541 | * are used by the driver to manage selection of appropriate firmware updates. |
| 542 | */ |
| 543 | #define MC_CMD_GET_BOARD_CFG 0x18 |
| 544 | #define MC_CMD_GET_BOARD_CFG_IN_LEN 0 |
| 545 | #define MC_CMD_GET_BOARD_CFG_OUT_LEN 96 |
| 546 | #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0 |
| 547 | #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4 |
| 548 | #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32 |
| 549 | #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36 |
| 550 | #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40 |
| 551 | #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44 |
| 552 | #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6 |
| 553 | #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50 |
| 554 | #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6 |
| 555 | #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56 |
| 556 | #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60 |
| 557 | #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64 |
| 558 | #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68 |
| 559 | #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72 |
| 560 | #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 24 |
| 561 | |
| 562 | /* MC_CMD_DBI_READX: (debug) |
| 563 | * Read DBI register(s) -- extended functionality |
| 564 | * |
| 565 | * Host: vf selection, address, [,vf selection ...] |
| 566 | * MC: value [,value ...] |
| 567 | */ |
| 568 | #define MC_CMD_DBI_READX 0x19 |
| 569 | #define MC_CMD_DBI_READX_IN_LEN(_numwords) \ |
| 570 | (8*(_numwords)) |
| 571 | #define MC_CMD_DBI_READX_OUT_LEN(_numwords) \ |
| 572 | (4*(_numwords)) |
| 573 | |
| 574 | /* MC_CMD_SET_RAND_SEED: |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 575 | * Set the 16byte seed for the MC pseudo-random generator |
Steve Hodgson | f0d37f4 | 2009-11-29 15:15:07 +0000 | [diff] [blame] | 576 | */ |
| 577 | #define MC_CMD_SET_RAND_SEED 0x1a |
| 578 | #define MC_CMD_SET_RAND_SEED_IN_LEN 16 |
| 579 | #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0 |
| 580 | #define MC_CMD_SET_RAND_SEED_OUT_LEN 0 |
| 581 | |
| 582 | /* MC_CMD_LTSSM_HIST: (debug) |
| 583 | * Retrieve the history of the LTSSM, if the build supports it. |
| 584 | * |
| 585 | * Host: nothing |
| 586 | * MC: variable number of LTSSM values, as bytes |
| 587 | * The history is read-to-clear. |
| 588 | */ |
| 589 | #define MC_CMD_LTSSM_HIST 0x1b |
| 590 | |
| 591 | /* MC_CMD_DRV_ATTACH: |
| 592 | * Inform MCPU that this port is managed on the host (i.e. driver active) |
| 593 | */ |
| 594 | #define MC_CMD_DRV_ATTACH 0x1c |
| 595 | #define MC_CMD_DRV_ATTACH_IN_LEN 8 |
| 596 | #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0 |
| 597 | #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4 |
| 598 | #define MC_CMD_DRV_ATTACH_OUT_LEN 4 |
| 599 | #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0 |
| 600 | |
| 601 | /* MC_CMD_NCSI_PROD: (debug) |
| 602 | * Trigger an NC-SI event (and possibly an AEN in response) |
| 603 | */ |
| 604 | #define MC_CMD_NCSI_PROD 0x1d |
| 605 | #define MC_CMD_NCSI_PROD_IN_LEN 4 |
| 606 | #define MC_CMD_NCSI_PROD_IN_EVENTS_OFST 0 |
| 607 | #define MC_CMD_NCSI_PROD_LINKCHANGE_LBN 0 |
| 608 | #define MC_CMD_NCSI_PROD_LINKCHANGE_WIDTH 1 |
| 609 | #define MC_CMD_NCSI_PROD_RESET_LBN 1 |
| 610 | #define MC_CMD_NCSI_PROD_RESET_WIDTH 1 |
| 611 | #define MC_CMD_NCSI_PROD_DRVATTACH_LBN 2 |
| 612 | #define MC_CMD_NCSI_PROD_DRVATTACH_WIDTH 1 |
| 613 | #define MC_CMD_NCSI_PROD_OUT_LEN 0 |
| 614 | |
| 615 | /* Enumeration */ |
| 616 | #define MC_CMD_NCSI_PROD_LINKCHANGE 0 |
| 617 | #define MC_CMD_NCSI_PROD_RESET 1 |
| 618 | #define MC_CMD_NCSI_PROD_DRVATTACH 2 |
| 619 | |
| 620 | /* MC_CMD_DEVEL: (debug) |
| 621 | * Reserved for development |
| 622 | */ |
| 623 | #define MC_CMD_DEVEL 0x1e |
| 624 | |
| 625 | /* MC_CMD_SHMUART: (debug) |
| 626 | * Route UART output to circular buffer in shared memory instead. |
| 627 | */ |
| 628 | #define MC_CMD_SHMUART 0x1f |
| 629 | #define MC_CMD_SHMUART_IN_FLAG_OFST 0 |
| 630 | #define MC_CMD_SHMUART_IN_LEN 4 |
| 631 | #define MC_CMD_SHMUART_OUT_LEN 0 |
| 632 | |
| 633 | /* MC_CMD_PORT_RESET: |
| 634 | * Generic per-port reset. There is no equivalent for per-board reset. |
| 635 | * |
| 636 | * Locks required: None |
| 637 | * Return code: 0, ETIME |
| 638 | */ |
| 639 | #define MC_CMD_PORT_RESET 0x20 |
| 640 | #define MC_CMD_PORT_RESET_IN_LEN 0 |
| 641 | #define MC_CMD_PORT_RESET_OUT_LEN 0 |
| 642 | |
| 643 | /* MC_CMD_RESOURCE_LOCK: |
| 644 | * Generic resource lock/unlock interface. |
| 645 | * |
| 646 | * Locks required: None |
| 647 | * Return code: 0, |
| 648 | * EBUSY (if trylock is contended by other port), |
| 649 | * EDEADLK (if trylock is already acquired by this port) |
| 650 | * EINVAL (if unlock doesn't own the lock) |
| 651 | */ |
| 652 | #define MC_CMD_RESOURCE_LOCK 0x21 |
| 653 | #define MC_CMD_RESOURCE_LOCK_IN_LEN 8 |
| 654 | #define MC_CMD_RESOURCE_LOCK_IN_ACTION_OFST 0 |
| 655 | #define MC_CMD_RESOURCE_LOCK_ACTION_TRYLOCK 1 |
| 656 | #define MC_CMD_RESOURCE_LOCK_ACTION_UNLOCK 0 |
| 657 | #define MC_CMD_RESOURCE_LOCK_IN_RESOURCE_OFST 4 |
| 658 | #define MC_CMD_RESOURCE_LOCK_I2C 2 |
| 659 | #define MC_CMD_RESOURCE_LOCK_PHY 3 |
| 660 | #define MC_CMD_RESOURCE_LOCK_OUT_LEN 0 |
| 661 | |
| 662 | /* MC_CMD_SPI_COMMAND: (variadic in, variadic out) |
| 663 | * Read/Write to/from the SPI device. |
| 664 | * |
| 665 | * Locks required: SPI_LOCK |
| 666 | * Return code: 0, ETIME, EINVAL, EACCES (if SPI_LOCK is not held) |
| 667 | */ |
| 668 | #define MC_CMD_SPI_COMMAND 0x22 |
| 669 | #define MC_CMD_SPI_COMMAND_IN_LEN(_write_bytes) (12 + (_write_bytes)) |
| 670 | #define MC_CMD_SPI_COMMAND_IN_ARGS_OFST 0 |
| 671 | #define MC_CMD_SPI_COMMAND_IN_ARGS_ADDRESS_OFST 0 |
| 672 | #define MC_CMD_SPI_COMMAND_IN_ARGS_READ_BYTES_OFST 4 |
| 673 | #define MC_CMD_SPI_COMMAND_IN_ARGS_CHIP_SELECT_OFST 8 |
| 674 | /* Data to write here */ |
| 675 | #define MC_CMD_SPI_COMMAND_IN_WRITE_BUFFER_OFST 12 |
| 676 | #define MC_CMD_SPI_COMMAND_OUT_LEN(_read_bytes) (_read_bytes) |
| 677 | /* Data read here */ |
| 678 | #define MC_CMD_SPI_COMMAND_OUT_READ_BUFFER_OFST 0 |
| 679 | |
| 680 | /* MC_CMD_I2C_READ_WRITE: (variadic in, variadic out) |
| 681 | * Read/Write to/from the I2C bus. |
| 682 | * |
| 683 | * Locks required: I2C_LOCK |
| 684 | * Return code: 0, ETIME, EINVAL, EACCES (if I2C_LOCK is not held) |
| 685 | */ |
| 686 | #define MC_CMD_I2C_RW 0x23 |
| 687 | #define MC_CMD_I2C_RW_IN_LEN(_write_bytes) (8 + (_write_bytes)) |
| 688 | #define MC_CMD_I2C_RW_IN_ARGS_OFST 0 |
| 689 | #define MC_CMD_I2C_RW_IN_ARGS_ADDR_OFST 0 |
| 690 | #define MC_CMD_I2C_RW_IN_ARGS_READ_BYTES_OFST 4 |
| 691 | /* Data to write here */ |
| 692 | #define MC_CMD_I2C_RW_IN_WRITE_BUFFER_OFSET 8 |
| 693 | #define MC_CMD_I2C_RW_OUT_LEN(_read_bytes) (_read_bytes) |
| 694 | /* Data read here */ |
| 695 | #define MC_CMD_I2C_RW_OUT_READ_BUFFER_OFST 0 |
| 696 | |
| 697 | /* Generic phy capability bitmask */ |
| 698 | #define MC_CMD_PHY_CAP_10HDX_LBN 1 |
| 699 | #define MC_CMD_PHY_CAP_10HDX_WIDTH 1 |
| 700 | #define MC_CMD_PHY_CAP_10FDX_LBN 2 |
| 701 | #define MC_CMD_PHY_CAP_10FDX_WIDTH 1 |
| 702 | #define MC_CMD_PHY_CAP_100HDX_LBN 3 |
| 703 | #define MC_CMD_PHY_CAP_100HDX_WIDTH 1 |
| 704 | #define MC_CMD_PHY_CAP_100FDX_LBN 4 |
| 705 | #define MC_CMD_PHY_CAP_100FDX_WIDTH 1 |
| 706 | #define MC_CMD_PHY_CAP_1000HDX_LBN 5 |
| 707 | #define MC_CMD_PHY_CAP_1000HDX_WIDTH 1 |
| 708 | #define MC_CMD_PHY_CAP_1000FDX_LBN 6 |
| 709 | #define MC_CMD_PHY_CAP_1000FDX_WIDTH 1 |
| 710 | #define MC_CMD_PHY_CAP_10000FDX_LBN 7 |
| 711 | #define MC_CMD_PHY_CAP_10000FDX_WIDTH 1 |
| 712 | #define MC_CMD_PHY_CAP_PAUSE_LBN 8 |
| 713 | #define MC_CMD_PHY_CAP_PAUSE_WIDTH 1 |
| 714 | #define MC_CMD_PHY_CAP_ASYM_LBN 9 |
| 715 | #define MC_CMD_PHY_CAP_ASYM_WIDTH 1 |
| 716 | #define MC_CMD_PHY_CAP_AN_LBN 10 |
| 717 | #define MC_CMD_PHY_CAP_AN_WIDTH 1 |
| 718 | |
| 719 | /* Generic loopback enumeration */ |
| 720 | #define MC_CMD_LOOPBACK_NONE 0 |
| 721 | #define MC_CMD_LOOPBACK_DATA 1 |
| 722 | #define MC_CMD_LOOPBACK_GMAC 2 |
| 723 | #define MC_CMD_LOOPBACK_XGMII 3 |
| 724 | #define MC_CMD_LOOPBACK_XGXS 4 |
| 725 | #define MC_CMD_LOOPBACK_XAUI 5 |
| 726 | #define MC_CMD_LOOPBACK_GMII 6 |
| 727 | #define MC_CMD_LOOPBACK_SGMII 7 |
| 728 | #define MC_CMD_LOOPBACK_XGBR 8 |
| 729 | #define MC_CMD_LOOPBACK_XFI 9 |
| 730 | #define MC_CMD_LOOPBACK_XAUI_FAR 10 |
| 731 | #define MC_CMD_LOOPBACK_GMII_FAR 11 |
| 732 | #define MC_CMD_LOOPBACK_SGMII_FAR 12 |
| 733 | #define MC_CMD_LOOPBACK_XFI_FAR 13 |
| 734 | #define MC_CMD_LOOPBACK_GPHY 14 |
| 735 | #define MC_CMD_LOOPBACK_PHYXS 15 |
| 736 | #define MC_CMD_LOOPBACK_PCS 16 |
| 737 | #define MC_CMD_LOOPBACK_PMAPMD 17 |
| 738 | #define MC_CMD_LOOPBACK_XPORT 18 |
| 739 | #define MC_CMD_LOOPBACK_XGMII_WS 19 |
| 740 | #define MC_CMD_LOOPBACK_XAUI_WS 20 |
| 741 | #define MC_CMD_LOOPBACK_XAUI_WS_FAR 21 |
| 742 | #define MC_CMD_LOOPBACK_XAUI_WS_NEAR 22 |
| 743 | #define MC_CMD_LOOPBACK_GMII_WS 23 |
| 744 | #define MC_CMD_LOOPBACK_XFI_WS 24 |
| 745 | #define MC_CMD_LOOPBACK_XFI_WS_FAR 25 |
| 746 | #define MC_CMD_LOOPBACK_PHYXS_WS 26 |
| 747 | |
| 748 | /* Generic PHY statistics enumeration */ |
| 749 | #define MC_CMD_OUI 0 |
| 750 | #define MC_CMD_PMA_PMD_LINK_UP 1 |
| 751 | #define MC_CMD_PMA_PMD_RX_FAULT 2 |
| 752 | #define MC_CMD_PMA_PMD_TX_FAULT 3 |
| 753 | #define MC_CMD_PMA_PMD_SIGNAL 4 |
| 754 | #define MC_CMD_PMA_PMD_SNR_A 5 |
| 755 | #define MC_CMD_PMA_PMD_SNR_B 6 |
| 756 | #define MC_CMD_PMA_PMD_SNR_C 7 |
| 757 | #define MC_CMD_PMA_PMD_SNR_D 8 |
| 758 | #define MC_CMD_PCS_LINK_UP 9 |
| 759 | #define MC_CMD_PCS_RX_FAULT 10 |
| 760 | #define MC_CMD_PCS_TX_FAULT 11 |
| 761 | #define MC_CMD_PCS_BER 12 |
| 762 | #define MC_CMD_PCS_BLOCK_ERRORS 13 |
| 763 | #define MC_CMD_PHYXS_LINK_UP 14 |
| 764 | #define MC_CMD_PHYXS_RX_FAULT 15 |
| 765 | #define MC_CMD_PHYXS_TX_FAULT 16 |
| 766 | #define MC_CMD_PHYXS_ALIGN 17 |
| 767 | #define MC_CMD_PHYXS_SYNC 18 |
| 768 | #define MC_CMD_AN_LINK_UP 19 |
| 769 | #define MC_CMD_AN_COMPLETE 20 |
| 770 | #define MC_CMD_AN_10GBT_STATUS 21 |
| 771 | #define MC_CMD_CL22_LINK_UP 22 |
| 772 | #define MC_CMD_PHY_NSTATS 23 |
| 773 | |
| 774 | /* MC_CMD_GET_PHY_CFG: |
| 775 | * Report PHY configuration. This guarantees to succeed even if the PHY is in |
| 776 | * a "zombie" state. |
| 777 | * |
| 778 | * Locks required: None |
| 779 | * Return code: 0 |
| 780 | */ |
| 781 | #define MC_CMD_GET_PHY_CFG 0x24 |
| 782 | |
| 783 | #define MC_CMD_GET_PHY_CFG_IN_LEN 0 |
| 784 | #define MC_CMD_GET_PHY_CFG_OUT_LEN 72 |
| 785 | |
| 786 | #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0 |
| 787 | #define MC_CMD_GET_PHY_CFG_PRESENT_LBN 0 |
| 788 | #define MC_CMD_GET_PHY_CFG_PRESENT_WIDTH 1 |
Ben Hutchings | 5297a98 | 2010-02-03 09:28:14 +0000 | [diff] [blame] | 789 | #define MC_CMD_GET_PHY_CFG_BIST_CABLE_SHORT_LBN 1 |
| 790 | #define MC_CMD_GET_PHY_CFG_BIST_CABLE_SHORT_WIDTH 1 |
| 791 | #define MC_CMD_GET_PHY_CFG_BIST_CABLE_LONG_LBN 2 |
| 792 | #define MC_CMD_GET_PHY_CFG_BIST_CABLE_LONG_WIDTH 1 |
Steve Hodgson | f0d37f4 | 2009-11-29 15:15:07 +0000 | [diff] [blame] | 793 | #define MC_CMD_GET_PHY_CFG_LOWPOWER_LBN 3 |
| 794 | #define MC_CMD_GET_PHY_CFG_LOWPOWER_WIDTH 1 |
| 795 | #define MC_CMD_GET_PHY_CFG_POWEROFF_LBN 4 |
| 796 | #define MC_CMD_GET_PHY_CFG_POWEROFF_WIDTH 1 |
| 797 | #define MC_CMD_GET_PHY_CFG_TXDIS_LBN 5 |
| 798 | #define MC_CMD_GET_PHY_CFG_TXDIS_WIDTH 1 |
Ben Hutchings | 5297a98 | 2010-02-03 09:28:14 +0000 | [diff] [blame] | 799 | #define MC_CMD_GET_PHY_CFG_BIST_LBN 6 |
| 800 | #define MC_CMD_GET_PHY_CFG_BIST_WIDTH 1 |
Steve Hodgson | f0d37f4 | 2009-11-29 15:15:07 +0000 | [diff] [blame] | 801 | #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4 |
| 802 | /* Bitmask of supported capabilities */ |
| 803 | #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8 |
| 804 | #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12 |
| 805 | #define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16 |
| 806 | /* PHY statistics bitmap */ |
| 807 | #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20 |
| 808 | /* PHY type/name string */ |
| 809 | #define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24 |
| 810 | #define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20 |
| 811 | #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44 |
| 812 | #define MC_CMD_MEDIA_XAUI 1 |
| 813 | #define MC_CMD_MEDIA_CX4 2 |
| 814 | #define MC_CMD_MEDIA_KX4 3 |
| 815 | #define MC_CMD_MEDIA_XFP 4 |
| 816 | #define MC_CMD_MEDIA_SFP_PLUS 5 |
| 817 | #define MC_CMD_MEDIA_BASE_T 6 |
| 818 | /* MDIO "MMDS" supported */ |
| 819 | #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48 |
| 820 | /* Native clause 22 */ |
| 821 | #define MC_CMD_MMD_CLAUSE22 0 |
| 822 | #define MC_CMD_MMD_CLAUSE45_PMAPMD 1 |
| 823 | #define MC_CMD_MMD_CLAUSE45_WIS 2 |
| 824 | #define MC_CMD_MMD_CLAUSE45_PCS 3 |
| 825 | #define MC_CMD_MMD_CLAUSE45_PHYXS 4 |
| 826 | #define MC_CMD_MMD_CLAUSE45_DTEXS 5 |
| 827 | #define MC_CMD_MMD_CLAUSE45_TC 6 |
| 828 | #define MC_CMD_MMD_CLAUSE45_AN 7 |
| 829 | /* Clause22 proxied over clause45 by PHY */ |
| 830 | #define MC_CMD_MMD_CLAUSE45_C22EXT 29 |
| 831 | #define MC_CMD_MMD_CLAUSE45_VEND1 30 |
| 832 | #define MC_CMD_MMD_CLAUSE45_VEND2 31 |
| 833 | /* PHY stepping version */ |
| 834 | #define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52 |
| 835 | #define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20 |
| 836 | |
Ben Hutchings | 5297a98 | 2010-02-03 09:28:14 +0000 | [diff] [blame] | 837 | /* MC_CMD_START_BIST: |
Steve Hodgson | f0d37f4 | 2009-11-29 15:15:07 +0000 | [diff] [blame] | 838 | * Start a BIST test on the PHY. |
| 839 | * |
| 840 | * Locks required: PHY_LOCK if doing a PHY BIST |
| 841 | * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held) |
| 842 | */ |
| 843 | #define MC_CMD_START_BIST 0x25 |
| 844 | #define MC_CMD_START_BIST_IN_LEN 4 |
Ben Hutchings | 5297a98 | 2010-02-03 09:28:14 +0000 | [diff] [blame] | 845 | #define MC_CMD_START_BIST_IN_TYPE_OFST 0 |
| 846 | #define MC_CMD_START_BIST_OUT_LEN 0 |
Steve Hodgson | f0d37f4 | 2009-11-29 15:15:07 +0000 | [diff] [blame] | 847 | |
Ben Hutchings | 5297a98 | 2010-02-03 09:28:14 +0000 | [diff] [blame] | 848 | /* Run the PHY's short cable BIST */ |
| 849 | #define MC_CMD_PHY_BIST_CABLE_SHORT 1 |
| 850 | /* Run the PHY's long cable BIST */ |
| 851 | #define MC_CMD_PHY_BIST_CABLE_LONG 2 |
Steve Hodgson | f0d37f4 | 2009-11-29 15:15:07 +0000 | [diff] [blame] | 852 | /* Run BIST on the currently selected BPX Serdes (XAUI or XFI) */ |
| 853 | #define MC_CMD_BPX_SERDES_BIST 3 |
Ben Hutchings | 5297a98 | 2010-02-03 09:28:14 +0000 | [diff] [blame] | 854 | /* Run the MC loopback tests */ |
| 855 | #define MC_CMD_MC_LOOPBACK_BIST 4 |
| 856 | /* Run the PHY's standard BIST */ |
| 857 | #define MC_CMD_PHY_BIST 5 |
Steve Hodgson | f0d37f4 | 2009-11-29 15:15:07 +0000 | [diff] [blame] | 858 | |
| 859 | /* MC_CMD_POLL_PHY_BIST: (variadic output) |
| 860 | * Poll for BIST completion |
| 861 | * |
Ben Hutchings | 5297a98 | 2010-02-03 09:28:14 +0000 | [diff] [blame] | 862 | * Returns a single status code, and optionally some PHY specific |
| 863 | * bist output. The driver should only consume the BIST output |
| 864 | * after validating OUTLEN and PHY_CFG.PHY_TYPE. |
Steve Hodgson | f0d37f4 | 2009-11-29 15:15:07 +0000 | [diff] [blame] | 865 | * |
Ben Hutchings | fbcfe8e | 2010-04-28 09:29:14 +0000 | [diff] [blame] | 866 | * If a driver can't successfully parse the BIST output, it should |
Ben Hutchings | 5297a98 | 2010-02-03 09:28:14 +0000 | [diff] [blame] | 867 | * still respect the pass/Fail in OUT.RESULT |
| 868 | * |
| 869 | * Locks required: PHY_LOCK if doing a PHY BIST |
Steve Hodgson | f0d37f4 | 2009-11-29 15:15:07 +0000 | [diff] [blame] | 870 | * Return code: 0, EACCES (if PHY_LOCK is not held) |
| 871 | */ |
| 872 | #define MC_CMD_POLL_BIST 0x26 |
| 873 | #define MC_CMD_POLL_BIST_IN_LEN 0 |
| 874 | #define MC_CMD_POLL_BIST_OUT_LEN UNKNOWN |
Ben Hutchings | fbcfe8e | 2010-04-28 09:29:14 +0000 | [diff] [blame] | 875 | #define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36 |
Ben Hutchings | 5297a98 | 2010-02-03 09:28:14 +0000 | [diff] [blame] | 876 | #define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8 |
Steve Hodgson | f0d37f4 | 2009-11-29 15:15:07 +0000 | [diff] [blame] | 877 | #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 |
| 878 | #define MC_CMD_POLL_BIST_RUNNING 1 |
| 879 | #define MC_CMD_POLL_BIST_PASSED 2 |
| 880 | #define MC_CMD_POLL_BIST_FAILED 3 |
| 881 | #define MC_CMD_POLL_BIST_TIMEOUT 4 |
Ben Hutchings | 5297a98 | 2010-02-03 09:28:14 +0000 | [diff] [blame] | 882 | /* Generic: */ |
Steve Hodgson | f0d37f4 | 2009-11-29 15:15:07 +0000 | [diff] [blame] | 883 | #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4 |
Ben Hutchings | 5297a98 | 2010-02-03 09:28:14 +0000 | [diff] [blame] | 884 | /* SFT9001-specific: */ |
Ben Hutchings | fbcfe8e | 2010-04-28 09:29:14 +0000 | [diff] [blame] | 885 | #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4 |
| 886 | #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8 |
| 887 | #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12 |
| 888 | #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16 |
| 889 | #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20 |
| 890 | #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24 |
| 891 | #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28 |
| 892 | #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32 |
Ben Hutchings | 5297a98 | 2010-02-03 09:28:14 +0000 | [diff] [blame] | 893 | #define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 1 |
| 894 | #define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 2 |
| 895 | #define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 3 |
| 896 | #define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 4 |
| 897 | #define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 9 |
| 898 | /* mrsfp "PHY" driver: */ |
| 899 | #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4 |
| 900 | #define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0 |
| 901 | #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 1 |
| 902 | #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 2 |
| 903 | #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 3 |
| 904 | #define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 4 |
| 905 | #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 5 |
| 906 | #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 6 |
| 907 | #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 7 |
| 908 | #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 8 |
Steve Hodgson | f0d37f4 | 2009-11-29 15:15:07 +0000 | [diff] [blame] | 909 | |
| 910 | /* MC_CMD_PHY_SPI: (variadic in, variadic out) |
| 911 | * Read/Write/Erase the PHY SPI device |
| 912 | * |
| 913 | * Locks required: PHY_LOCK |
| 914 | * Return code: 0, ETIME, EINVAL, EACCES (if PHY_LOCK is not held) |
| 915 | */ |
| 916 | #define MC_CMD_PHY_SPI 0x27 |
| 917 | #define MC_CMD_PHY_SPI_IN_LEN(_write_bytes) (12 + (_write_bytes)) |
| 918 | #define MC_CMD_PHY_SPI_IN_ARGS_OFST 0 |
| 919 | #define MC_CMD_PHY_SPI_IN_ARGS_ADDR_OFST 0 |
| 920 | #define MC_CMD_PHY_SPI_IN_ARGS_READ_BYTES_OFST 4 |
| 921 | #define MC_CMD_PHY_SPI_IN_ARGS_ERASE_ALL_OFST 8 |
| 922 | /* Data to write here */ |
| 923 | #define MC_CMD_PHY_SPI_IN_WRITE_BUFFER_OFSET 12 |
| 924 | #define MC_CMD_PHY_SPI_OUT_LEN(_read_bytes) (_read_bytes) |
| 925 | /* Data read here */ |
| 926 | #define MC_CMD_PHY_SPI_OUT_READ_BUFFER_OFST 0 |
| 927 | |
| 928 | |
| 929 | /* MC_CMD_GET_LOOPBACK_MODES: |
| 930 | * Returns a bitmask of loopback modes evailable at each speed. |
| 931 | * |
| 932 | * Locks required: None |
| 933 | * Return code: 0 |
| 934 | */ |
| 935 | #define MC_CMD_GET_LOOPBACK_MODES 0x28 |
| 936 | #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0 |
| 937 | #define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 32 |
| 938 | #define MC_CMD_GET_LOOPBACK_MODES_100M_OFST 0 |
| 939 | #define MC_CMD_GET_LOOPBACK_MODES_1G_OFST 8 |
| 940 | #define MC_CMD_GET_LOOPBACK_MODES_10G_OFST 16 |
| 941 | #define MC_CMD_GET_LOOPBACK_MODES_SUGGESTED_OFST 24 |
| 942 | |
| 943 | /* Flow control enumeration */ |
| 944 | #define MC_CMD_FCNTL_OFF 0 |
| 945 | #define MC_CMD_FCNTL_RESPOND 1 |
| 946 | #define MC_CMD_FCNTL_BIDIR 2 |
| 947 | /* Auto - Use what the link has autonegotiated |
| 948 | * - The driver should modify the advertised capabilities via SET_LINK.CAP |
| 949 | * to control the negotiated flow control mode. |
| 950 | * - Can only be set if the PHY supports PAUSE+ASYM capabilities |
| 951 | * - Never returned by GET_LINK as the value programmed into the MAC |
| 952 | */ |
| 953 | #define MC_CMD_FCNTL_AUTO 3 |
| 954 | |
| 955 | /* Generic mac fault bitmask */ |
| 956 | #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 |
| 957 | #define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 |
| 958 | #define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 |
| 959 | #define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 |
| 960 | #define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 |
| 961 | #define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 |
| 962 | |
| 963 | /* MC_CMD_GET_LINK: |
| 964 | * Read the unified MAC/PHY link state |
| 965 | * |
| 966 | * Locks required: None |
| 967 | * Return code: 0, ETIME |
| 968 | */ |
| 969 | #define MC_CMD_GET_LINK 0x29 |
| 970 | #define MC_CMD_GET_LINK_IN_LEN 0 |
| 971 | #define MC_CMD_GET_LINK_OUT_LEN 28 |
| 972 | /* near-side and link-partner advertised capabilities */ |
| 973 | #define MC_CMD_GET_LINK_OUT_CAP_OFST 0 |
| 974 | #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4 |
| 975 | /* Autonegotiated speed in mbit/s. The link may still be down |
| 976 | * even if this reads non-zero */ |
| 977 | #define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8 |
| 978 | #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12 |
| 979 | #define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16 |
| 980 | /* Whether we have overall link up */ |
| 981 | #define MC_CMD_GET_LINK_LINK_UP_LBN 0 |
| 982 | #define MC_CMD_GET_LINK_LINK_UP_WIDTH 1 |
| 983 | #define MC_CMD_GET_LINK_FULL_DUPLEX_LBN 1 |
| 984 | #define MC_CMD_GET_LINK_FULL_DUPLEX_WIDTH 1 |
| 985 | /* Whether we have link at the layers provided by the BPX */ |
| 986 | #define MC_CMD_GET_LINK_BPX_LINK_LBN 2 |
| 987 | #define MC_CMD_GET_LINK_BPX_LINK_WIDTH 1 |
| 988 | /* Whether the PHY has external link */ |
| 989 | #define MC_CMD_GET_LINK_PHY_LINK_LBN 3 |
| 990 | #define MC_CMD_GET_LINK_PHY_LINK_WIDTH 1 |
| 991 | #define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20 |
| 992 | #define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24 |
| 993 | |
| 994 | /* MC_CMD_SET_LINK: |
| 995 | * Write the unified MAC/PHY link configuration |
| 996 | * |
| 997 | * A loopback speed of "0" is supported, and means |
| 998 | * (choose any available speed) |
| 999 | * |
| 1000 | * Locks required: None |
| 1001 | * Return code: 0, EINVAL, ETIME |
| 1002 | */ |
| 1003 | #define MC_CMD_SET_LINK 0x2a |
| 1004 | #define MC_CMD_SET_LINK_IN_LEN 16 |
| 1005 | #define MC_CMD_SET_LINK_IN_CAP_OFST 0 |
| 1006 | #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4 |
| 1007 | #define MC_CMD_SET_LINK_LOWPOWER_LBN 0 |
| 1008 | #define MC_CMD_SET_LINK_LOWPOWER_WIDTH 1 |
| 1009 | #define MC_CMD_SET_LINK_POWEROFF_LBN 1 |
| 1010 | #define MC_CMD_SET_LINK_POWEROFF_WIDTH 1 |
| 1011 | #define MC_CMD_SET_LINK_TXDIS_LBN 2 |
| 1012 | #define MC_CMD_SET_LINK_TXDIS_WIDTH 1 |
| 1013 | #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8 |
| 1014 | #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12 |
| 1015 | #define MC_CMD_SET_LINK_OUT_LEN 0 |
| 1016 | |
| 1017 | /* MC_CMD_SET_ID_LED: |
| 1018 | * Set indentification LED state |
| 1019 | * |
| 1020 | * Locks required: None |
| 1021 | * Return code: 0, EINVAL |
| 1022 | */ |
| 1023 | #define MC_CMD_SET_ID_LED 0x2b |
| 1024 | #define MC_CMD_SET_ID_LED_IN_LEN 4 |
| 1025 | #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0 |
| 1026 | #define MC_CMD_LED_OFF 0 |
| 1027 | #define MC_CMD_LED_ON 1 |
| 1028 | #define MC_CMD_LED_DEFAULT 2 |
| 1029 | #define MC_CMD_SET_ID_LED_OUT_LEN 0 |
| 1030 | |
| 1031 | /* MC_CMD_SET_MAC: |
| 1032 | * Set MAC configuration |
| 1033 | * |
| 1034 | * The MTU is the MTU programmed directly into the XMAC/GMAC |
| 1035 | * (inclusive of EtherII, VLAN, bug16011 padding) |
| 1036 | * |
| 1037 | * Locks required: None |
| 1038 | * Return code: 0, EINVAL |
| 1039 | */ |
| 1040 | #define MC_CMD_SET_MAC 0x2c |
| 1041 | #define MC_CMD_SET_MAC_IN_LEN 24 |
| 1042 | #define MC_CMD_SET_MAC_IN_MTU_OFST 0 |
| 1043 | #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4 |
| 1044 | #define MC_CMD_SET_MAC_IN_ADDR_OFST 8 |
| 1045 | #define MC_CMD_SET_MAC_IN_REJECT_OFST 16 |
| 1046 | #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0 |
| 1047 | #define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1 |
| 1048 | #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1 |
| 1049 | #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1 |
| 1050 | #define MC_CMD_SET_MAC_IN_FCNTL_OFST 20 |
| 1051 | #define MC_CMD_SET_MAC_OUT_LEN 0 |
| 1052 | |
| 1053 | /* MC_CMD_PHY_STATS: |
| 1054 | * Get generic PHY statistics |
| 1055 | * |
Ben Hutchings | fbcfe8e | 2010-04-28 09:29:14 +0000 | [diff] [blame] | 1056 | * This call returns the statistics for a generic PHY in a sparse |
| 1057 | * array (indexed by the enumerate). Each value is represented by |
| 1058 | * a 32bit number. |
| 1059 | * |
| 1060 | * If the DMA_ADDR is 0, then no DMA is performed, and the statistics |
| 1061 | * may be read directly out of shared memory. If DMA_ADDR != 0, then |
| 1062 | * the statistics are dmad to that (page-aligned location) |
Steve Hodgson | f0d37f4 | 2009-11-29 15:15:07 +0000 | [diff] [blame] | 1063 | * |
| 1064 | * Locks required: None |
| 1065 | * Returns: 0, ETIME |
| 1066 | * Response methods: shared memory, event |
| 1067 | */ |
| 1068 | #define MC_CMD_PHY_STATS 0x2d |
| 1069 | #define MC_CMD_PHY_STATS_IN_LEN 8 |
| 1070 | #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0 |
| 1071 | #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4 |
Ben Hutchings | fbcfe8e | 2010-04-28 09:29:14 +0000 | [diff] [blame] | 1072 | #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0 |
| 1073 | #define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (MC_CMD_PHY_NSTATS * 4) |
Steve Hodgson | f0d37f4 | 2009-11-29 15:15:07 +0000 | [diff] [blame] | 1074 | |
| 1075 | /* Unified MAC statistics enumeration */ |
| 1076 | #define MC_CMD_MAC_GENERATION_START 0 |
| 1077 | #define MC_CMD_MAC_TX_PKTS 1 |
| 1078 | #define MC_CMD_MAC_TX_PAUSE_PKTS 2 |
| 1079 | #define MC_CMD_MAC_TX_CONTROL_PKTS 3 |
| 1080 | #define MC_CMD_MAC_TX_UNICAST_PKTS 4 |
| 1081 | #define MC_CMD_MAC_TX_MULTICAST_PKTS 5 |
| 1082 | #define MC_CMD_MAC_TX_BROADCAST_PKTS 6 |
| 1083 | #define MC_CMD_MAC_TX_BYTES 7 |
| 1084 | #define MC_CMD_MAC_TX_BAD_BYTES 8 |
| 1085 | #define MC_CMD_MAC_TX_LT64_PKTS 9 |
| 1086 | #define MC_CMD_MAC_TX_64_PKTS 10 |
| 1087 | #define MC_CMD_MAC_TX_65_TO_127_PKTS 11 |
| 1088 | #define MC_CMD_MAC_TX_128_TO_255_PKTS 12 |
| 1089 | #define MC_CMD_MAC_TX_256_TO_511_PKTS 13 |
| 1090 | #define MC_CMD_MAC_TX_512_TO_1023_PKTS 14 |
| 1091 | #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 15 |
| 1092 | #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 16 |
| 1093 | #define MC_CMD_MAC_TX_GTJUMBO_PKTS 17 |
| 1094 | #define MC_CMD_MAC_TX_BAD_FCS_PKTS 18 |
| 1095 | #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 19 |
| 1096 | #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 20 |
| 1097 | #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 21 |
| 1098 | #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 22 |
| 1099 | #define MC_CMD_MAC_TX_DEFERRED_PKTS 23 |
| 1100 | #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 24 |
| 1101 | #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 25 |
| 1102 | #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 26 |
| 1103 | #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 27 |
| 1104 | #define MC_CMD_MAC_RX_PKTS 28 |
| 1105 | #define MC_CMD_MAC_RX_PAUSE_PKTS 29 |
| 1106 | #define MC_CMD_MAC_RX_GOOD_PKTS 30 |
| 1107 | #define MC_CMD_MAC_RX_CONTROL_PKTS 31 |
| 1108 | #define MC_CMD_MAC_RX_UNICAST_PKTS 32 |
| 1109 | #define MC_CMD_MAC_RX_MULTICAST_PKTS 33 |
| 1110 | #define MC_CMD_MAC_RX_BROADCAST_PKTS 34 |
| 1111 | #define MC_CMD_MAC_RX_BYTES 35 |
| 1112 | #define MC_CMD_MAC_RX_BAD_BYTES 36 |
| 1113 | #define MC_CMD_MAC_RX_64_PKTS 37 |
| 1114 | #define MC_CMD_MAC_RX_65_TO_127_PKTS 38 |
| 1115 | #define MC_CMD_MAC_RX_128_TO_255_PKTS 39 |
| 1116 | #define MC_CMD_MAC_RX_256_TO_511_PKTS 40 |
| 1117 | #define MC_CMD_MAC_RX_512_TO_1023_PKTS 41 |
| 1118 | #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 42 |
| 1119 | #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 43 |
| 1120 | #define MC_CMD_MAC_RX_GTJUMBO_PKTS 44 |
| 1121 | #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 45 |
| 1122 | #define MC_CMD_MAC_RX_BAD_FCS_PKTS 46 |
| 1123 | #define MC_CMD_MAC_RX_OVERFLOW_PKTS 47 |
| 1124 | #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 48 |
| 1125 | #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 49 |
| 1126 | #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 50 |
| 1127 | #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 51 |
| 1128 | #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 52 |
| 1129 | #define MC_CMD_MAC_RX_JABBER_PKTS 53 |
| 1130 | #define MC_CMD_MAC_RX_NODESC_DROPS 54 |
| 1131 | #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 55 |
| 1132 | #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 56 |
| 1133 | #define MC_CMD_MAC_RX_LANES01_DISP_ERR 57 |
| 1134 | #define MC_CMD_MAC_RX_LANES23_DISP_ERR 58 |
| 1135 | #define MC_CMD_MAC_RX_MATCH_FAULT 59 |
Guido Barzini | 8704a2c | 2010-01-25 15:49:19 -0800 | [diff] [blame] | 1136 | #define MC_CMD_GMAC_DMABUF_START 64 |
| 1137 | #define MC_CMD_GMAC_DMABUF_END 95 |
Steve Hodgson | f0d37f4 | 2009-11-29 15:15:07 +0000 | [diff] [blame] | 1138 | /* Insert new members here. */ |
Guido Barzini | 8704a2c | 2010-01-25 15:49:19 -0800 | [diff] [blame] | 1139 | #define MC_CMD_MAC_GENERATION_END 96 |
Steve Hodgson | f0d37f4 | 2009-11-29 15:15:07 +0000 | [diff] [blame] | 1140 | #define MC_CMD_MAC_NSTATS (MC_CMD_MAC_GENERATION_END+1) |
| 1141 | |
| 1142 | /* MC_CMD_MAC_STATS: |
| 1143 | * Get unified GMAC/XMAC statistics |
| 1144 | * |
| 1145 | * This call returns unified statistics maintained by the MC as it |
| 1146 | * switches between the GMAC and XMAC. The MC will write out all |
| 1147 | * supported stats. The driver should zero initialise the buffer to |
| 1148 | * guarantee consistent results. |
| 1149 | * |
| 1150 | * Locks required: None |
| 1151 | * Returns: 0 |
| 1152 | * Response methods: shared memory, event |
| 1153 | */ |
| 1154 | #define MC_CMD_MAC_STATS 0x2e |
| 1155 | #define MC_CMD_MAC_STATS_IN_LEN 16 |
| 1156 | #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0 |
| 1157 | #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4 |
| 1158 | #define MC_CMD_MAC_STATS_IN_CMD_OFST 8 |
| 1159 | #define MC_CMD_MAC_STATS_CMD_DMA_LBN 0 |
| 1160 | #define MC_CMD_MAC_STATS_CMD_DMA_WIDTH 1 |
| 1161 | #define MC_CMD_MAC_STATS_CMD_CLEAR_LBN 1 |
| 1162 | #define MC_CMD_MAC_STATS_CMD_CLEAR_WIDTH 1 |
| 1163 | #define MC_CMD_MAC_STATS_CMD_PERIODIC_CHANGE_LBN 2 |
| 1164 | #define MC_CMD_MAC_STATS_CMD_PERIODIC_CHANGE_WIDTH 1 |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 1165 | /* Remaining PERIOD* fields only relevant when PERIODIC_CHANGE is set */ |
Steve Hodgson | f0d37f4 | 2009-11-29 15:15:07 +0000 | [diff] [blame] | 1166 | #define MC_CMD_MAC_STATS_CMD_PERIODIC_ENABLE_LBN 3 |
| 1167 | #define MC_CMD_MAC_STATS_CMD_PERIODIC_ENABLE_WIDTH 1 |
| 1168 | #define MC_CMD_MAC_STATS_CMD_PERIODIC_CLEAR_LBN 4 |
| 1169 | #define MC_CMD_MAC_STATS_CMD_PERIODIC_CLEAR_WIDTH 1 |
Ben Hutchings | fbcfe8e | 2010-04-28 09:29:14 +0000 | [diff] [blame] | 1170 | #define MC_CMD_MAC_STATS_CMD_PERIODIC_NOEVENT_LBN 5 |
| 1171 | #define MC_CMD_MAC_STATS_CMD_PERIODIC_NOEVENT_WIDTH 1 |
Steve Hodgson | f0d37f4 | 2009-11-29 15:15:07 +0000 | [diff] [blame] | 1172 | #define MC_CMD_MAC_STATS_CMD_PERIOD_MS_LBN 16 |
| 1173 | #define MC_CMD_MAC_STATS_CMD_PERIOD_MS_WIDTH 16 |
| 1174 | #define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12 |
| 1175 | |
| 1176 | #define MC_CMD_MAC_STATS_OUT_LEN 0 |
| 1177 | |
| 1178 | /* Callisto flags */ |
| 1179 | #define MC_CMD_SFT9001_ROBUST_LBN 0 |
| 1180 | #define MC_CMD_SFT9001_ROBUST_WIDTH 1 |
| 1181 | #define MC_CMD_SFT9001_SHORT_REACH_LBN 1 |
| 1182 | #define MC_CMD_SFT9001_SHORT_REACH_WIDTH 1 |
| 1183 | |
| 1184 | /* MC_CMD_SFT9001_GET: |
| 1185 | * Read current callisto specific setting |
| 1186 | * |
| 1187 | * Locks required: None |
| 1188 | * Returns: 0, ETIME |
| 1189 | */ |
| 1190 | #define MC_CMD_SFT9001_GET 0x30 |
| 1191 | #define MC_CMD_SFT9001_GET_IN_LEN 0 |
| 1192 | #define MC_CMD_SFT9001_GET_OUT_LEN 4 |
| 1193 | #define MC_CMD_SFT9001_GET_OUT_FLAGS_OFST 0 |
| 1194 | |
| 1195 | /* MC_CMD_SFT9001_SET: |
| 1196 | * Write current callisto specific setting |
| 1197 | * |
| 1198 | * Locks required: None |
| 1199 | * Returns: 0, ETIME, EINVAL |
| 1200 | */ |
| 1201 | #define MC_CMD_SFT9001_SET 0x31 |
| 1202 | #define MC_CMD_SFT9001_SET_IN_LEN 4 |
| 1203 | #define MC_CMD_SFT9001_SET_IN_FLAGS_OFST 0 |
| 1204 | #define MC_CMD_SFT9001_SET_OUT_LEN 0 |
| 1205 | |
| 1206 | |
| 1207 | /* MC_CMD_WOL_FILTER_SET: |
| 1208 | * Set a WoL filter |
| 1209 | * |
| 1210 | * Locks required: None |
| 1211 | * Returns: 0, EBUSY, EINVAL, ENOSYS |
| 1212 | */ |
| 1213 | #define MC_CMD_WOL_FILTER_SET 0x32 |
| 1214 | #define MC_CMD_WOL_FILTER_SET_IN_LEN 192 /* 190 rounded up to a word */ |
| 1215 | #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 |
| 1216 | #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 |
| 1217 | |
| 1218 | /* There is a union at offset 8, following defines overlap due to |
| 1219 | * this */ |
| 1220 | #define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8 |
| 1221 | |
| 1222 | #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST \ |
| 1223 | MC_CMD_WOL_FILTER_SET_IN_DATA_OFST |
| 1224 | |
| 1225 | #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST \ |
| 1226 | MC_CMD_WOL_FILTER_SET_IN_DATA_OFST |
| 1227 | #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST \ |
| 1228 | (MC_CMD_WOL_FILTER_SET_IN_DATA_OFST + 4) |
| 1229 | #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST \ |
| 1230 | (MC_CMD_WOL_FILTER_SET_IN_DATA_OFST + 8) |
| 1231 | #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST \ |
| 1232 | (MC_CMD_WOL_FILTER_SET_IN_DATA_OFST + 10) |
| 1233 | |
| 1234 | #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST \ |
| 1235 | MC_CMD_WOL_FILTER_SET_IN_DATA_OFST |
| 1236 | #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST \ |
| 1237 | (MC_CMD_WOL_FILTER_SET_IN_DATA_OFST + 16) |
| 1238 | #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST \ |
| 1239 | (MC_CMD_WOL_FILTER_SET_IN_DATA_OFST + 32) |
| 1240 | #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST \ |
| 1241 | (MC_CMD_WOL_FILTER_SET_IN_DATA_OFST + 34) |
| 1242 | |
| 1243 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST \ |
| 1244 | MC_CMD_WOL_FILTER_SET_IN_DATA_OFST |
| 1245 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_OFST \ |
| 1246 | (MC_CMD_WOL_FILTER_SET_IN_DATA_OFST + 48) |
| 1247 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST \ |
| 1248 | (MC_CMD_WOL_FILTER_SET_IN_DATA_OFST + 176) |
| 1249 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST \ |
| 1250 | (MC_CMD_WOL_FILTER_SET_IN_DATA_OFST + 177) |
| 1251 | #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST \ |
| 1252 | (MC_CMD_WOL_FILTER_SET_IN_DATA_OFST + 178) |
| 1253 | |
Ben Hutchings | 5297a98 | 2010-02-03 09:28:14 +0000 | [diff] [blame] | 1254 | #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST \ |
| 1255 | MC_CMD_WOL_FILTER_SET_IN_DATA_OFST |
| 1256 | #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0 |
| 1257 | #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1 |
| 1258 | #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1 |
| 1259 | #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1 |
| 1260 | |
Steve Hodgson | f0d37f4 | 2009-11-29 15:15:07 +0000 | [diff] [blame] | 1261 | #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4 |
| 1262 | #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0 |
| 1263 | |
| 1264 | /* WOL Filter types enumeration */ |
| 1265 | #define MC_CMD_WOL_TYPE_MAGIC 0x0 |
| 1266 | /* unused 0x1 */ |
| 1267 | #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2 |
| 1268 | #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3 |
| 1269 | #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4 |
| 1270 | #define MC_CMD_WOL_TYPE_BITMAP 0x5 |
Ben Hutchings | 5297a98 | 2010-02-03 09:28:14 +0000 | [diff] [blame] | 1271 | #define MC_CMD_WOL_TYPE_LINK 0x6 |
| 1272 | #define MC_CMD_WOL_TYPE_MAX 0x7 |
Steve Hodgson | f0d37f4 | 2009-11-29 15:15:07 +0000 | [diff] [blame] | 1273 | |
| 1274 | #define MC_CMD_FILTER_MODE_SIMPLE 0x0 |
| 1275 | #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff |
| 1276 | |
| 1277 | /* MC_CMD_WOL_FILTER_REMOVE: |
| 1278 | * Remove a WoL filter |
| 1279 | * |
| 1280 | * Locks required: None |
| 1281 | * Returns: 0, EINVAL, ENOSYS |
| 1282 | */ |
| 1283 | #define MC_CMD_WOL_FILTER_REMOVE 0x33 |
| 1284 | #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4 |
| 1285 | #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0 |
| 1286 | #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0 |
| 1287 | |
| 1288 | |
| 1289 | /* MC_CMD_WOL_FILTER_RESET: |
| 1290 | * Reset (i.e. remove all) WoL filters |
| 1291 | * |
| 1292 | * Locks required: None |
| 1293 | * Returns: 0, ENOSYS |
| 1294 | */ |
| 1295 | #define MC_CMD_WOL_FILTER_RESET 0x34 |
| 1296 | #define MC_CMD_WOL_FILTER_RESET_IN_LEN 0 |
| 1297 | #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0 |
| 1298 | |
| 1299 | /* MC_CMD_SET_MCAST_HASH: |
| 1300 | * Set the MCASH hash value without otherwise |
| 1301 | * reconfiguring the MAC |
| 1302 | */ |
| 1303 | #define MC_CMD_SET_MCAST_HASH 0x35 |
| 1304 | #define MC_CMD_SET_MCAST_HASH_IN_LEN 32 |
| 1305 | #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0 |
| 1306 | #define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16 |
| 1307 | #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0 |
| 1308 | |
| 1309 | /* MC_CMD_NVRAM_TYPES: |
| 1310 | * Return bitfield indicating available types of virtual NVRAM partitions |
| 1311 | * |
| 1312 | * Locks required: none |
| 1313 | * Returns: 0 |
| 1314 | */ |
| 1315 | #define MC_CMD_NVRAM_TYPES 0x36 |
| 1316 | #define MC_CMD_NVRAM_TYPES_IN_LEN 0 |
| 1317 | #define MC_CMD_NVRAM_TYPES_OUT_LEN 4 |
| 1318 | #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0 |
| 1319 | |
| 1320 | /* Supported NVRAM types */ |
| 1321 | #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0 |
| 1322 | #define MC_CMD_NVRAM_TYPE_MC_FW 1 |
| 1323 | #define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 2 |
| 1324 | #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 3 |
| 1325 | #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 4 |
| 1326 | #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 5 |
| 1327 | #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 6 |
| 1328 | #define MC_CMD_NVRAM_TYPE_EXP_ROM 7 |
| 1329 | #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 8 |
| 1330 | #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 9 |
| 1331 | #define MC_CMD_NVRAM_TYPE_PHY_PORT0 10 |
| 1332 | #define MC_CMD_NVRAM_TYPE_PHY_PORT1 11 |
| 1333 | #define MC_CMD_NVRAM_TYPE_LOG 12 |
| 1334 | |
| 1335 | /* MC_CMD_NVRAM_INFO: |
| 1336 | * Read info about a virtual NVRAM partition |
| 1337 | * |
| 1338 | * Locks required: none |
| 1339 | * Returns: 0, EINVAL (bad type) |
| 1340 | */ |
| 1341 | #define MC_CMD_NVRAM_INFO 0x37 |
| 1342 | #define MC_CMD_NVRAM_INFO_IN_LEN 4 |
| 1343 | #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0 |
| 1344 | #define MC_CMD_NVRAM_INFO_OUT_LEN 24 |
| 1345 | #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0 |
| 1346 | #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4 |
| 1347 | #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8 |
| 1348 | #define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12 |
| 1349 | #define MC_CMD_NVRAM_PROTECTED_LBN 0 |
| 1350 | #define MC_CMD_NVRAM_PROTECTED_WIDTH 1 |
| 1351 | #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16 |
| 1352 | #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20 |
| 1353 | |
| 1354 | /* MC_CMD_NVRAM_UPDATE_START: |
| 1355 | * Start a group of update operations on a virtual NVRAM partition |
| 1356 | * |
| 1357 | * Locks required: PHY_LOCK if type==*PHY* |
| 1358 | * Returns: 0, EINVAL (bad type), EACCES (if PHY_LOCK required and not held) |
| 1359 | */ |
| 1360 | #define MC_CMD_NVRAM_UPDATE_START 0x38 |
| 1361 | #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4 |
| 1362 | #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0 |
| 1363 | #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0 |
| 1364 | |
| 1365 | /* MC_CMD_NVRAM_READ: |
| 1366 | * Read data from a virtual NVRAM partition |
| 1367 | * |
| 1368 | * Locks required: PHY_LOCK if type==*PHY* |
| 1369 | * Returns: 0, EINVAL (bad type/offset/length), EACCES (if PHY_LOCK required and not held) |
| 1370 | */ |
| 1371 | #define MC_CMD_NVRAM_READ 0x39 |
| 1372 | #define MC_CMD_NVRAM_READ_IN_LEN 12 |
| 1373 | #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0 |
| 1374 | #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4 |
| 1375 | #define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8 |
| 1376 | #define MC_CMD_NVRAM_READ_OUT_LEN(_read_bytes) (_read_bytes) |
| 1377 | #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0 |
| 1378 | |
| 1379 | /* MC_CMD_NVRAM_WRITE: |
| 1380 | * Write data to a virtual NVRAM partition |
| 1381 | * |
| 1382 | * Locks required: PHY_LOCK if type==*PHY* |
| 1383 | * Returns: 0, EINVAL (bad type/offset/length), EACCES (if PHY_LOCK required and not held) |
| 1384 | */ |
| 1385 | #define MC_CMD_NVRAM_WRITE 0x3a |
| 1386 | #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0 |
| 1387 | #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4 |
| 1388 | #define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8 |
| 1389 | #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12 |
| 1390 | #define MC_CMD_NVRAM_WRITE_IN_LEN(_write_bytes) (12 + _write_bytes) |
| 1391 | #define MC_CMD_NVRAM_WRITE_OUT_LEN 0 |
| 1392 | |
| 1393 | /* MC_CMD_NVRAM_ERASE: |
| 1394 | * Erase sector(s) from a virtual NVRAM partition |
| 1395 | * |
| 1396 | * Locks required: PHY_LOCK if type==*PHY* |
| 1397 | * Returns: 0, EINVAL (bad type/offset/length), EACCES (if PHY_LOCK required and not held) |
| 1398 | */ |
| 1399 | #define MC_CMD_NVRAM_ERASE 0x3b |
| 1400 | #define MC_CMD_NVRAM_ERASE_IN_LEN 12 |
| 1401 | #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0 |
| 1402 | #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4 |
| 1403 | #define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8 |
| 1404 | #define MC_CMD_NVRAM_ERASE_OUT_LEN 0 |
| 1405 | |
| 1406 | /* MC_CMD_NVRAM_UPDATE_FINISH: |
| 1407 | * Finish a group of update operations on a virtual NVRAM partition |
| 1408 | * |
| 1409 | * Locks required: PHY_LOCK if type==*PHY* |
| 1410 | * Returns: 0, EINVAL (bad type/offset/length), EACCES (if PHY_LOCK required and not held) |
| 1411 | */ |
| 1412 | #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c |
Ben Hutchings | 5297a98 | 2010-02-03 09:28:14 +0000 | [diff] [blame] | 1413 | #define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8 |
Steve Hodgson | f0d37f4 | 2009-11-29 15:15:07 +0000 | [diff] [blame] | 1414 | #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0 |
Ben Hutchings | 5297a98 | 2010-02-03 09:28:14 +0000 | [diff] [blame] | 1415 | #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4 |
Steve Hodgson | f0d37f4 | 2009-11-29 15:15:07 +0000 | [diff] [blame] | 1416 | #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0 |
| 1417 | |
| 1418 | /* MC_CMD_REBOOT: |
Ben Hutchings | 5297a98 | 2010-02-03 09:28:14 +0000 | [diff] [blame] | 1419 | * Reboot the MC. |
| 1420 | * |
| 1421 | * The AFTER_ASSERTION flag is intended to be used when the driver notices |
| 1422 | * an assertion failure (at which point it is expected to perform a complete |
| 1423 | * tear down and reinitialise), to allow both ports to reset the MC once |
| 1424 | * in an atomic fashion. |
| 1425 | * |
| 1426 | * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1, |
| 1427 | * which means that they will automatically reboot out of the assertion |
| 1428 | * handler, so this is in practise an optional operation. It is still |
| 1429 | * recommended that drivers execute this to support custom firmwares |
| 1430 | * with REBOOT_ON_ASSERT=0. |
Steve Hodgson | f0d37f4 | 2009-11-29 15:15:07 +0000 | [diff] [blame] | 1431 | * |
| 1432 | * Locks required: NONE |
| 1433 | * Returns: Nothing. You get back a response with ERR=1, DATALEN=0 |
| 1434 | */ |
| 1435 | #define MC_CMD_REBOOT 0x3d |
| 1436 | #define MC_CMD_REBOOT_IN_LEN 4 |
| 1437 | #define MC_CMD_REBOOT_IN_FLAGS_OFST 0 |
| 1438 | #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 1 |
| 1439 | #define MC_CMD_REBOOT_OUT_LEN 0 |
| 1440 | |
| 1441 | /* MC_CMD_SCHEDINFO: |
| 1442 | * Request scheduler info. from the MC. |
| 1443 | * |
| 1444 | * Locks required: NONE |
| 1445 | * Returns: An array of (timeslice,maximum overrun), one for each thread, |
| 1446 | * in ascending order of thread address.s |
| 1447 | */ |
| 1448 | #define MC_CMD_SCHEDINFO 0x3e |
| 1449 | #define MC_CMD_SCHEDINFO_IN_LEN 0 |
| 1450 | |
| 1451 | |
| 1452 | /* MC_CMD_SET_REBOOT_MODE: (debug) |
| 1453 | * Set the mode for the next MC reboot. |
| 1454 | * |
| 1455 | * Locks required: NONE |
| 1456 | * |
| 1457 | * Sets the reboot mode to the specified value. Returns the old mode. |
| 1458 | */ |
| 1459 | #define MC_CMD_REBOOT_MODE 0x3f |
| 1460 | #define MC_CMD_REBOOT_MODE_IN_LEN 4 |
| 1461 | #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0 |
| 1462 | #define MC_CMD_REBOOT_MODE_OUT_LEN 4 |
| 1463 | #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0 |
| 1464 | #define MC_CMD_REBOOT_MODE_NORMAL 0 |
| 1465 | #define MC_CMD_REBOOT_MODE_SNAPPER 3 |
| 1466 | |
| 1467 | /* MC_CMD_DEBUG_LOG: |
| 1468 | * Null request/response command (debug) |
| 1469 | * - sequence number is always zero |
| 1470 | * - only supported on the UART interface |
| 1471 | * (the same set of bytes is delivered as an |
| 1472 | * event over PCI) |
| 1473 | */ |
| 1474 | #define MC_CMD_DEBUG_LOG 0x40 |
| 1475 | #define MC_CMD_DEBUG_LOG_IN_LEN 0 |
| 1476 | #define MC_CMD_DEBUG_LOG_OUT_LEN 0 |
| 1477 | |
| 1478 | /* Generic sensor enumeration. Note that a dual port NIC |
| 1479 | * will EITHER expose PHY_COMMON_TEMP OR PHY0_TEMP and |
| 1480 | * PHY1_TEMP depending on whether there is a single sensor |
| 1481 | * in the vicinity of the two port, or one per port. |
| 1482 | */ |
| 1483 | #define MC_CMD_SENSOR_CONTROLLER_TEMP 0 /* degC */ |
| 1484 | #define MC_CMD_SENSOR_PHY_COMMON_TEMP 1 /* degC */ |
| 1485 | #define MC_CMD_SENSOR_CONTROLLER_COOLING 2 /* bool */ |
| 1486 | #define MC_CMD_SENSOR_PHY0_TEMP 3 /* degC */ |
| 1487 | #define MC_CMD_SENSOR_PHY0_COOLING 4 /* bool */ |
| 1488 | #define MC_CMD_SENSOR_PHY1_TEMP 5 /* degC */ |
| 1489 | #define MC_CMD_SENSOR_PHY1_COOLING 6 /* bool */ |
| 1490 | #define MC_CMD_SENSOR_IN_1V0 7 /* mV */ |
| 1491 | #define MC_CMD_SENSOR_IN_1V2 8 /* mV */ |
| 1492 | #define MC_CMD_SENSOR_IN_1V8 9 /* mV */ |
| 1493 | #define MC_CMD_SENSOR_IN_2V5 10 /* mV */ |
| 1494 | #define MC_CMD_SENSOR_IN_3V3 11 /* mV */ |
| 1495 | #define MC_CMD_SENSOR_IN_12V0 12 /* mV */ |
| 1496 | |
| 1497 | |
| 1498 | /* Sensor state */ |
| 1499 | #define MC_CMD_SENSOR_STATE_OK 0 |
| 1500 | #define MC_CMD_SENSOR_STATE_WARNING 1 |
| 1501 | #define MC_CMD_SENSOR_STATE_FATAL 2 |
| 1502 | #define MC_CMD_SENSOR_STATE_BROKEN 3 |
| 1503 | |
| 1504 | /* MC_CMD_SENSOR_INFO: |
| 1505 | * Returns information about every available sensor. |
| 1506 | * |
| 1507 | * Each sensor has a single (16bit) value, and a corresponding state. |
| 1508 | * The mapping between value and sensor is nominally determined by the |
| 1509 | * MC, but in practise is implemented as zero (BROKEN), one (TEMPERATURE), |
| 1510 | * or two (VOLTAGE) ranges per sensor per state. |
| 1511 | * |
| 1512 | * This call returns a mask (32bit) of the sensors that are supported |
| 1513 | * by this platform, then an array (indexed by MC_CMD_SENSOR) of byte |
| 1514 | * offsets to the per-sensor arrays. Each sensor array has four 16bit |
| 1515 | * numbers, min1, max1, min2, max2. |
| 1516 | * |
| 1517 | * Locks required: None |
| 1518 | * Returns: 0 |
| 1519 | */ |
| 1520 | #define MC_CMD_SENSOR_INFO 0x41 |
| 1521 | #define MC_CMD_SENSOR_INFO_IN_LEN 0 |
| 1522 | #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0 |
| 1523 | #define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \ |
| 1524 | (4 + (_x)) |
| 1525 | #define MC_CMD_SENSOR_INFO_OUT_MIN1_OFST(_ofst) \ |
| 1526 | ((_ofst) + 0) |
| 1527 | #define MC_CMD_SENSOR_INFO_OUT_MAX1_OFST(_ofst) \ |
| 1528 | ((_ofst) + 2) |
| 1529 | #define MC_CMD_SENSOR_INFO_OUT_MIN2_OFST(_ofst) \ |
| 1530 | ((_ofst) + 4) |
| 1531 | #define MC_CMD_SENSOR_INFO_OUT_MAX2_OFST(_ofst) \ |
| 1532 | ((_ofst) + 6) |
| 1533 | |
| 1534 | /* MC_CMD_READ_SENSORS |
Ben Hutchings | 5297a98 | 2010-02-03 09:28:14 +0000 | [diff] [blame] | 1535 | * Returns the current reading from each sensor |
Steve Hodgson | f0d37f4 | 2009-11-29 15:15:07 +0000 | [diff] [blame] | 1536 | * |
Ben Hutchings | 5297a98 | 2010-02-03 09:28:14 +0000 | [diff] [blame] | 1537 | * Returns a sparse array of sensor readings (indexed by the sensor |
| 1538 | * type) into host memory. Each array element is a dword. |
Steve Hodgson | f0d37f4 | 2009-11-29 15:15:07 +0000 | [diff] [blame] | 1539 | * |
| 1540 | * The MC will send a SENSOREVT event every time any sensor changes state. The |
| 1541 | * driver is responsible for ensuring that it doesn't miss any events. The board |
| 1542 | * will function normally if all sensors are in STATE_OK or state_WARNING. |
| 1543 | * Otherwise the board should not be expected to function. |
| 1544 | */ |
| 1545 | #define MC_CMD_READ_SENSORS 0x42 |
| 1546 | #define MC_CMD_READ_SENSORS_IN_LEN 8 |
| 1547 | #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0 |
| 1548 | #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4 |
| 1549 | #define MC_CMD_READ_SENSORS_OUT_LEN 0 |
| 1550 | |
Ben Hutchings | 5297a98 | 2010-02-03 09:28:14 +0000 | [diff] [blame] | 1551 | /* Sensor reading fields */ |
| 1552 | #define MC_CMD_READ_SENSOR_VALUE_LBN 0 |
| 1553 | #define MC_CMD_READ_SENSOR_VALUE_WIDTH 16 |
| 1554 | #define MC_CMD_READ_SENSOR_STATE_LBN 16 |
| 1555 | #define MC_CMD_READ_SENSOR_STATE_WIDTH 8 |
| 1556 | |
Steve Hodgson | f0d37f4 | 2009-11-29 15:15:07 +0000 | [diff] [blame] | 1557 | |
| 1558 | /* MC_CMD_GET_PHY_STATE: |
| 1559 | * Report current state of PHY. A "zombie" PHY is a PHY that has failed to |
| 1560 | * boot (e.g. due to missing or corrupted firmware). |
| 1561 | * |
| 1562 | * Locks required: None |
| 1563 | * Return code: 0 |
| 1564 | */ |
| 1565 | #define MC_CMD_GET_PHY_STATE 0x43 |
| 1566 | |
| 1567 | #define MC_CMD_GET_PHY_STATE_IN_LEN 0 |
| 1568 | #define MC_CMD_GET_PHY_STATE_OUT_LEN 4 |
| 1569 | #define MC_CMD_GET_PHY_STATE_STATE_OFST 0 |
| 1570 | /* PHY state enumeration: */ |
| 1571 | #define MC_CMD_PHY_STATE_OK 1 |
| 1572 | #define MC_CMD_PHY_STATE_ZOMBIE 2 |
| 1573 | |
| 1574 | |
| 1575 | /* 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to |
| 1576 | * disable 802.Qbb for a given priority. */ |
| 1577 | #define MC_CMD_SETUP_8021QBB 0x44 |
| 1578 | #define MC_CMD_SETUP_8021QBB_IN_LEN 32 |
| 1579 | #define MC_CMD_SETUP_8021QBB_OUT_LEN 0 |
| 1580 | #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFFST 0 |
| 1581 | |
| 1582 | |
| 1583 | /* MC_CMD_WOL_FILTER_GET: |
| 1584 | * Retrieve ID of any WoL filters |
| 1585 | * |
| 1586 | * Locks required: None |
| 1587 | * Returns: 0, ENOSYS |
| 1588 | */ |
| 1589 | #define MC_CMD_WOL_FILTER_GET 0x45 |
| 1590 | #define MC_CMD_WOL_FILTER_GET_IN_LEN 0 |
| 1591 | #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4 |
| 1592 | #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0 |
| 1593 | |
| 1594 | |
| 1595 | /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD: |
| 1596 | * Offload a protocol to NIC for lights-out state |
| 1597 | * |
| 1598 | * Locks required: None |
| 1599 | * Returns: 0, ENOSYS |
| 1600 | */ |
| 1601 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46 |
| 1602 | |
| 1603 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN 16 |
| 1604 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 |
| 1605 | |
| 1606 | /* There is a union at offset 4, following defines overlap due to |
| 1607 | * this */ |
| 1608 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4 |
| 1609 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARPMAC_OFST 4 |
| 1610 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARPIP_OFST 10 |
| 1611 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NSMAC_OFST 4 |
| 1612 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NSSNIPV6_OFST 10 |
| 1613 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NSIPV6_OFST 26 |
| 1614 | |
| 1615 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4 |
| 1616 | #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0 |
| 1617 | |
| 1618 | |
| 1619 | /* MC_CMD_REMOVE_LIGHTSOUT_PROTOCOL_OFFLOAD: |
| 1620 | * Offload a protocol to NIC for lights-out state |
| 1621 | * |
| 1622 | * Locks required: None |
| 1623 | * Returns: 0, ENOSYS |
| 1624 | */ |
| 1625 | #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47 |
| 1626 | #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8 |
| 1627 | #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0 |
| 1628 | |
| 1629 | #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 |
| 1630 | #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4 |
| 1631 | |
| 1632 | /* Lights-out offload protocols enumeration */ |
| 1633 | #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 |
| 1634 | #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 |
| 1635 | |
| 1636 | |
| 1637 | /* MC_CMD_MAC_RESET_RESTORE: |
| 1638 | * Restore MAC after block reset |
| 1639 | * |
| 1640 | * Locks required: None |
| 1641 | * Returns: 0 |
| 1642 | */ |
| 1643 | |
| 1644 | #define MC_CMD_MAC_RESET_RESTORE 0x48 |
| 1645 | #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0 |
| 1646 | #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0 |
| 1647 | |
Ben Hutchings | 5297a98 | 2010-02-03 09:28:14 +0000 | [diff] [blame] | 1648 | |
| 1649 | /* MC_CMD_TEST_ASSERT: |
| 1650 | * Deliberately trigger an assert-detonation in the firmware for testing |
| 1651 | * purposes (i.e. to allow tests that the driver copes gracefully). |
| 1652 | * |
| 1653 | * Locks required: None |
| 1654 | * Returns: 0 |
| 1655 | */ |
| 1656 | |
| 1657 | #define MC_CMD_TESTASSERT 0x49 |
| 1658 | #define MC_CMD_TESTASSERT_IN_LEN 0 |
| 1659 | #define MC_CMD_TESTASSERT_OUT_LEN 0 |
| 1660 | |
| 1661 | /* MC_CMD_WORKAROUND 0x4a |
| 1662 | * |
| 1663 | * Enable/Disable a given workaround. The mcfw will return EINVAL if it |
| 1664 | * doesn't understand the given workaround number - which should not |
| 1665 | * be treated as a hard error by client code. |
| 1666 | * |
| 1667 | * This op does not imply any semantics about each workaround, that's between |
| 1668 | * the driver and the mcfw on a per-workaround basis. |
| 1669 | * |
| 1670 | * Locks required: None |
| 1671 | * Returns: 0, EINVAL |
| 1672 | */ |
| 1673 | #define MC_CMD_WORKAROUND 0x4a |
| 1674 | #define MC_CMD_WORKAROUND_IN_LEN 8 |
| 1675 | #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0 |
| 1676 | #define MC_CMD_WORKAROUND_BUG17230 1 |
| 1677 | #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4 |
| 1678 | #define MC_CMD_WORKAROUND_OUT_LEN 0 |
| 1679 | |
| 1680 | /* MC_CMD_GET_PHY_MEDIA_INFO: |
| 1681 | * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for |
| 1682 | * SFP+ PHYs). |
| 1683 | * |
| 1684 | * The "media type" can be found via GET_PHY_CFG (GET_PHY_CFG_OUT_MEDIA_TYPE); |
| 1685 | * the valid "page number" input values, and the output data, are interpreted |
| 1686 | * on a per-type basis. |
| 1687 | * |
| 1688 | * For SFP+: PAGE=0 or 1 returns a 128-byte block read from module I2C address |
| 1689 | * 0xA0 offset 0 or 0x80. |
| 1690 | * Anything else: currently undefined. |
| 1691 | * |
| 1692 | * Locks required: None |
| 1693 | * Return code: 0 |
| 1694 | */ |
| 1695 | #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b |
| 1696 | #define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4 |
| 1697 | #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0 |
| 1698 | #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(_num_bytes) (4 + (_num_bytes)) |
| 1699 | #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0 |
| 1700 | #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4 |
| 1701 | |
| 1702 | /* MC_CMD_NVRAM_TEST: |
| 1703 | * Test a particular NVRAM partition for valid contents (where "valid" |
| 1704 | * depends on the type of partition). |
| 1705 | * |
| 1706 | * Locks required: None |
| 1707 | * Return code: 0 |
| 1708 | */ |
| 1709 | #define MC_CMD_NVRAM_TEST 0x4c |
| 1710 | #define MC_CMD_NVRAM_TEST_IN_LEN 4 |
| 1711 | #define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0 |
| 1712 | #define MC_CMD_NVRAM_TEST_OUT_LEN 4 |
| 1713 | #define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0 |
| 1714 | #define MC_CMD_NVRAM_TEST_PASS 0 |
| 1715 | #define MC_CMD_NVRAM_TEST_FAIL 1 |
| 1716 | #define MC_CMD_NVRAM_TEST_NOTSUPP 2 |
| 1717 | |
| 1718 | /* MC_CMD_MRSFP_TWEAK: (debug) |
| 1719 | * Read status and/or set parameters for the "mrsfp" driver in mr_rusty builds. |
| 1720 | * I2C I/O expander bits are always read; if equaliser parameters are supplied, |
| 1721 | * they are configured first. |
| 1722 | * |
| 1723 | * Locks required: None |
| 1724 | * Return code: 0, EINVAL |
| 1725 | */ |
| 1726 | #define MC_CMD_MRSFP_TWEAK 0x4d |
| 1727 | #define MC_CMD_MRSFP_TWEAK_IN_LEN_READ_ONLY 0 |
| 1728 | #define MC_CMD_MRSFP_TWEAK_IN_LEN_EQ_CONFIG 16 |
| 1729 | #define MC_CMD_MRSFP_TWEAK_IN_TXEQ_LEVEL_OFST 0 /* 0-6 low->high de-emph. */ |
| 1730 | #define MC_CMD_MRSFP_TWEAK_IN_TXEQ_DT_CFG_OFST 4 /* 0-8 low->high ref.V */ |
| 1731 | #define MC_CMD_MRSFP_TWEAK_IN_RXEQ_BOOST_OFST 8 /* 0-8 low->high boost */ |
| 1732 | #define MC_CMD_MRSFP_TWEAK_IN_RXEQ_DT_CFG_OFST 12 /* 0-8 low->high ref.V */ |
| 1733 | #define MC_CMD_MRSFP_TWEAK_OUT_LEN 12 |
| 1734 | #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0 /* input bits */ |
| 1735 | #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4 /* output bits */ |
| 1736 | #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8 /* dirs: 0=out, 1=in */ |
| 1737 | |
Ben Hutchings | fbcfe8e | 2010-04-28 09:29:14 +0000 | [diff] [blame] | 1738 | /* MC_CMD_TEST_HACK: (debug (unsurprisingly)) |
| 1739 | * Change bits of network port state for test purposes in ways that would never be |
| 1740 | * useful in normal operation and so need a special command to change. */ |
| 1741 | #define MC_CMD_TEST_HACK 0x2f |
| 1742 | #define MC_CMD_TEST_HACK_IN_LEN 8 |
| 1743 | #define MC_CMD_TEST_HACK_IN_TXPAD_OFST 0 |
| 1744 | #define MC_CMD_TEST_HACK_IN_TXPAD_AUTO 0 /* Let the MC manage things */ |
| 1745 | #define MC_CMD_TEST_HACK_IN_TXPAD_ON 1 /* Force on */ |
| 1746 | #define MC_CMD_TEST_HACK_IN_TXPAD_OFF 2 /* Force on */ |
| 1747 | #define MC_CMD_TEST_HACK_IN_IPG_OFST 4 /* Takes a value in bits */ |
| 1748 | #define MC_CMD_TEST_HACK_IN_IPG_AUTO 0 /* The MC picks the value */ |
| 1749 | #define MC_CMD_TEST_HACK_OUT_LEN 0 |
| 1750 | |
| 1751 | /* MC_CMD_SENSOR_SET_LIMS: (debug) (mostly) adjust the sensor limits. This |
| 1752 | * is a warranty-voiding operation. |
| 1753 | * |
| 1754 | * IN: sensor identifier (one of the enumeration starting with MC_CMD_SENSOR_CONTROLLER_TEMP |
| 1755 | * followed by 4 32-bit values: min(warning) max(warning), min(fatal), max(fatal). Which |
| 1756 | * of these limits are meaningful and what their interpretation is is sensor-specific. |
| 1757 | * |
| 1758 | * OUT: nothing |
| 1759 | * |
| 1760 | * Returns: ENOENT if the sensor specified does not exist, EINVAL if the limits are |
| 1761 | * out of range. |
| 1762 | */ |
| 1763 | #define MC_CMD_SENSOR_SET_LIMS 0x4e |
| 1764 | #define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20 |
| 1765 | #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0 |
| 1766 | #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4 |
| 1767 | #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8 |
| 1768 | #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12 |
| 1769 | #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16 |
| 1770 | |
Ben Hutchings | 5297a98 | 2010-02-03 09:28:14 +0000 | [diff] [blame] | 1771 | /* Do NOT add new commands beyond 0x4f as part of 3.0 : 0x50 - 0x7f will be |
| 1772 | * used for post-3.0 extensions. If you run out of space, look for gaps or |
| 1773 | * commands that are unused in the existing range. */ |
| 1774 | |
Steve Hodgson | f0d37f4 | 2009-11-29 15:15:07 +0000 | [diff] [blame] | 1775 | #endif /* MCDI_PCOL_H */ |