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Dan Williams3668b452007-02-13 17:13:34 +01001#ifndef _IOP13XX_TIME_H_
2#define _IOP13XX_TIME_H_
3#define IRQ_IOP_TIMER0 IRQ_IOP13XX_TIMER0
4
5#define IOP_TMR_EN 0x02
6#define IOP_TMR_RELOAD 0x04
7#define IOP_TMR_PRIVILEGED 0x08
8#define IOP_TMR_RATIO_1_1 0x00
9
Dan Williams84c981f2007-04-29 09:32:51 +010010#define IOP13XX_XSI_FREQ_RATIO_MASK (3 << 19)
11#define IOP13XX_XSI_FREQ_RATIO_2 (0 << 19)
12#define IOP13XX_XSI_FREQ_RATIO_3 (1 << 19)
13#define IOP13XX_XSI_FREQ_RATIO_4 (2 << 19)
14#define IOP13XX_CORE_FREQ_MASK (7 << 16)
15#define IOP13XX_CORE_FREQ_600 (0 << 16)
16#define IOP13XX_CORE_FREQ_667 (1 << 16)
17#define IOP13XX_CORE_FREQ_800 (2 << 16)
18#define IOP13XX_CORE_FREQ_933 (3 << 16)
19#define IOP13XX_CORE_FREQ_1000 (4 << 16)
20#define IOP13XX_CORE_FREQ_1200 (5 << 16)
21
Dan Williams3668b452007-02-13 17:13:34 +010022void iop_init_time(unsigned long tickrate);
Dan Williams3668b452007-02-13 17:13:34 +010023
Dan Williams84c981f2007-04-29 09:32:51 +010024static inline unsigned long iop13xx_core_freq(void)
25{
26 unsigned long freq = __raw_readl(IOP13XX_PROCESSOR_FREQ);
27 freq &= IOP13XX_CORE_FREQ_MASK;
28 switch (freq) {
29 case IOP13XX_CORE_FREQ_600:
30 return 600000000;
31 case IOP13XX_CORE_FREQ_667:
32 return 667000000;
33 case IOP13XX_CORE_FREQ_800:
34 return 800000000;
35 case IOP13XX_CORE_FREQ_933:
36 return 933000000;
37 case IOP13XX_CORE_FREQ_1000:
38 return 1000000000;
39 case IOP13XX_CORE_FREQ_1200:
40 return 1200000000;
41 default:
42 printk("%s: warning unknown frequency, defaulting to 800Mhz\n",
Harvey Harrison653c0312008-10-20 16:00:08 -070043 __func__);
Dan Williams84c981f2007-04-29 09:32:51 +010044 }
45
46 return 800000000;
47}
48
49static inline unsigned long iop13xx_xsi_bus_ratio(void)
50{
51 unsigned long ratio = __raw_readl(IOP13XX_PROCESSOR_FREQ);
52 ratio &= IOP13XX_XSI_FREQ_RATIO_MASK;
53 switch (ratio) {
54 case IOP13XX_XSI_FREQ_RATIO_2:
55 return 2;
56 case IOP13XX_XSI_FREQ_RATIO_3:
57 return 3;
58 case IOP13XX_XSI_FREQ_RATIO_4:
59 return 4;
60 default:
61 printk("%s: warning unknown ratio, defaulting to 2\n",
Harvey Harrison653c0312008-10-20 16:00:08 -070062 __func__);
Dan Williams84c981f2007-04-29 09:32:51 +010063 }
64
65 return 2;
66}
67
Mikael Pettersson469d30442009-10-29 11:46:54 -070068static inline u32 read_tmr0(void)
69{
70 u32 val;
71 asm volatile("mrc p6, 0, %0, c0, c9, 0" : "=r" (val));
72 return val;
73}
74
Dan Williams3668b452007-02-13 17:13:34 +010075static inline void write_tmr0(u32 val)
76{
77 asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val));
78}
79
80static inline void write_tmr1(u32 val)
81{
82 asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (val));
83}
84
85static inline u32 read_tcr0(void)
86{
87 u32 val;
88 asm volatile("mrc p6, 0, %0, c2, c9, 0" : "=r" (val));
89 return val;
90}
91
Mikael Pettersson469d30442009-10-29 11:46:54 -070092static inline void write_tcr0(u32 val)
93{
94 asm volatile("mcr p6, 0, %0, c2, c9, 0" : : "r" (val));
95}
96
Dan Williams3668b452007-02-13 17:13:34 +010097static inline u32 read_tcr1(void)
98{
99 u32 val;
100 asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val));
101 return val;
102}
103
Mikael Petterssona91549a2009-10-29 11:46:54 -0700104static inline void write_tcr1(u32 val)
105{
106 asm volatile("mcr p6, 0, %0, c3, c9, 0" : : "r" (val));
107}
108
Dan Williams3668b452007-02-13 17:13:34 +0100109static inline void write_trr0(u32 val)
110{
111 asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (val));
112}
113
114static inline void write_trr1(u32 val)
115{
116 asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (val));
117}
118
119static inline void write_tisr(u32 val)
120{
121 asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (val));
122}
123#endif