viresh kumar | 986435e | 2010-04-01 12:30:49 +0100 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/plat-spear/time.c |
| 3 | * |
| 4 | * Copyright (C) 2009 ST Microelectronics |
| 5 | * Shiraz Hashim<shiraz.hashim@st.com> |
| 6 | * |
| 7 | * This file is licensed under the terms of the GNU General Public |
| 8 | * License version 2. This program is licensed "as is" without any |
| 9 | * warranty of any kind, whether express or implied. |
| 10 | */ |
| 11 | |
| 12 | #include <linux/clk.h> |
| 13 | #include <linux/clockchips.h> |
| 14 | #include <linux/clocksource.h> |
| 15 | #include <linux/err.h> |
| 16 | #include <linux/init.h> |
| 17 | #include <linux/interrupt.h> |
| 18 | #include <linux/io.h> |
| 19 | #include <linux/kernel.h> |
| 20 | #include <linux/time.h> |
| 21 | #include <linux/irq.h> |
| 22 | #include <asm/mach/time.h> |
| 23 | #include <mach/irqs.h> |
| 24 | #include <mach/hardware.h> |
| 25 | #include <mach/spear.h> |
| 26 | #include <mach/generic.h> |
| 27 | |
| 28 | /* |
| 29 | * We would use TIMER0 and TIMER1 as clockevent and clocksource. |
| 30 | * Timer0 and Timer1 both belong to same gpt block in cpu subbsystem. Further |
| 31 | * they share same functional clock. Any change in one's functional clock will |
| 32 | * also affect other timer. |
| 33 | */ |
| 34 | |
| 35 | #define CLKEVT 0 /* gpt0, channel0 as clockevent */ |
| 36 | #define CLKSRC 1 /* gpt0, channel1 as clocksource */ |
| 37 | |
| 38 | /* Register offsets, x is channel number */ |
| 39 | #define CR(x) ((x) * 0x80 + 0x80) |
| 40 | #define IR(x) ((x) * 0x80 + 0x84) |
| 41 | #define LOAD(x) ((x) * 0x80 + 0x88) |
| 42 | #define COUNT(x) ((x) * 0x80 + 0x8C) |
| 43 | |
| 44 | /* Reg bit definitions */ |
| 45 | #define CTRL_INT_ENABLE 0x0100 |
| 46 | #define CTRL_ENABLE 0x0020 |
| 47 | #define CTRL_ONE_SHOT 0x0010 |
| 48 | |
| 49 | #define CTRL_PRESCALER1 0x0 |
| 50 | #define CTRL_PRESCALER2 0x1 |
| 51 | #define CTRL_PRESCALER4 0x2 |
| 52 | #define CTRL_PRESCALER8 0x3 |
| 53 | #define CTRL_PRESCALER16 0x4 |
| 54 | #define CTRL_PRESCALER32 0x5 |
| 55 | #define CTRL_PRESCALER64 0x6 |
| 56 | #define CTRL_PRESCALER128 0x7 |
| 57 | #define CTRL_PRESCALER256 0x8 |
| 58 | |
| 59 | #define INT_STATUS 0x1 |
| 60 | |
Linus Walleij | 4bd4894 | 2010-07-19 20:55:46 +0100 | [diff] [blame] | 61 | /* |
| 62 | * Minimum clocksource/clockevent timer range in seconds |
| 63 | */ |
| 64 | #define SPEAR_MIN_RANGE 4 |
| 65 | |
viresh kumar | 986435e | 2010-04-01 12:30:49 +0100 | [diff] [blame] | 66 | static __iomem void *gpt_base; |
| 67 | static struct clk *gpt_clk; |
| 68 | |
| 69 | static void clockevent_set_mode(enum clock_event_mode mode, |
| 70 | struct clock_event_device *clk_event_dev); |
| 71 | static int clockevent_next_event(unsigned long evt, |
| 72 | struct clock_event_device *clk_event_dev); |
| 73 | |
viresh kumar | 986435e | 2010-04-01 12:30:49 +0100 | [diff] [blame] | 74 | static cycle_t clocksource_read_cycles(struct clocksource *cs) |
| 75 | { |
| 76 | return (cycle_t) readw(gpt_base + COUNT(CLKSRC)); |
| 77 | } |
| 78 | |
| 79 | static struct clocksource clksrc = { |
| 80 | .name = "tmr1", |
| 81 | .rating = 200, /* its a pretty decent clock */ |
| 82 | .read = clocksource_read_cycles, |
| 83 | .mask = 0xFFFF, /* 16 bits */ |
| 84 | .mult = 0, /* to be computed */ |
| 85 | .shift = 0, /* to be computed */ |
| 86 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 87 | }; |
| 88 | |
| 89 | static void spear_clocksource_init(void) |
| 90 | { |
| 91 | u32 tick_rate; |
| 92 | u16 val; |
| 93 | |
| 94 | /* program the prescaler (/256)*/ |
| 95 | writew(CTRL_PRESCALER256, gpt_base + CR(CLKSRC)); |
| 96 | |
| 97 | /* find out actual clock driving Timer */ |
| 98 | tick_rate = clk_get_rate(gpt_clk); |
| 99 | tick_rate >>= CTRL_PRESCALER256; |
| 100 | |
| 101 | writew(0xFFFF, gpt_base + LOAD(CLKSRC)); |
| 102 | |
| 103 | val = readw(gpt_base + CR(CLKSRC)); |
| 104 | val &= ~CTRL_ONE_SHOT; /* autoreload mode */ |
| 105 | val |= CTRL_ENABLE ; |
| 106 | writew(val, gpt_base + CR(CLKSRC)); |
| 107 | |
Linus Walleij | 4bd4894 | 2010-07-19 20:55:46 +0100 | [diff] [blame] | 108 | clocksource_calc_mult_shift(&clksrc, tick_rate, SPEAR_MIN_RANGE); |
viresh kumar | 986435e | 2010-04-01 12:30:49 +0100 | [diff] [blame] | 109 | |
| 110 | /* register the clocksource */ |
| 111 | clocksource_register(&clksrc); |
| 112 | } |
| 113 | |
| 114 | static struct clock_event_device clkevt = { |
| 115 | .name = "tmr0", |
| 116 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
| 117 | .set_mode = clockevent_set_mode, |
| 118 | .set_next_event = clockevent_next_event, |
| 119 | .shift = 0, /* to be computed */ |
| 120 | }; |
| 121 | |
| 122 | static void clockevent_set_mode(enum clock_event_mode mode, |
| 123 | struct clock_event_device *clk_event_dev) |
| 124 | { |
| 125 | u32 period; |
| 126 | u16 val; |
| 127 | |
| 128 | /* stop the timer */ |
| 129 | val = readw(gpt_base + CR(CLKEVT)); |
| 130 | val &= ~CTRL_ENABLE; |
| 131 | writew(val, gpt_base + CR(CLKEVT)); |
| 132 | |
| 133 | switch (mode) { |
| 134 | case CLOCK_EVT_MODE_PERIODIC: |
| 135 | period = clk_get_rate(gpt_clk) / HZ; |
| 136 | period >>= CTRL_PRESCALER16; |
| 137 | writew(period, gpt_base + LOAD(CLKEVT)); |
| 138 | |
| 139 | val = readw(gpt_base + CR(CLKEVT)); |
| 140 | val &= ~CTRL_ONE_SHOT; |
| 141 | val |= CTRL_ENABLE | CTRL_INT_ENABLE; |
| 142 | writew(val, gpt_base + CR(CLKEVT)); |
| 143 | |
| 144 | break; |
| 145 | case CLOCK_EVT_MODE_ONESHOT: |
| 146 | val = readw(gpt_base + CR(CLKEVT)); |
| 147 | val |= CTRL_ONE_SHOT; |
| 148 | writew(val, gpt_base + CR(CLKEVT)); |
| 149 | |
| 150 | break; |
| 151 | case CLOCK_EVT_MODE_UNUSED: |
| 152 | case CLOCK_EVT_MODE_SHUTDOWN: |
| 153 | case CLOCK_EVT_MODE_RESUME: |
| 154 | |
| 155 | break; |
| 156 | default: |
| 157 | pr_err("Invalid mode requested\n"); |
| 158 | break; |
| 159 | } |
| 160 | } |
| 161 | |
| 162 | static int clockevent_next_event(unsigned long cycles, |
| 163 | struct clock_event_device *clk_event_dev) |
| 164 | { |
| 165 | u16 val; |
| 166 | |
| 167 | writew(cycles, gpt_base + LOAD(CLKEVT)); |
| 168 | |
| 169 | val = readw(gpt_base + CR(CLKEVT)); |
| 170 | val |= CTRL_ENABLE | CTRL_INT_ENABLE; |
| 171 | writew(val, gpt_base + CR(CLKEVT)); |
| 172 | |
| 173 | return 0; |
| 174 | } |
| 175 | |
| 176 | static irqreturn_t spear_timer_interrupt(int irq, void *dev_id) |
| 177 | { |
| 178 | struct clock_event_device *evt = &clkevt; |
| 179 | |
| 180 | writew(INT_STATUS, gpt_base + IR(CLKEVT)); |
| 181 | |
| 182 | evt->event_handler(evt); |
| 183 | |
| 184 | return IRQ_HANDLED; |
| 185 | } |
| 186 | |
| 187 | static struct irqaction spear_timer_irq = { |
| 188 | .name = "timer", |
| 189 | .flags = IRQF_DISABLED | IRQF_TIMER, |
| 190 | .handler = spear_timer_interrupt |
| 191 | }; |
| 192 | |
| 193 | static void __init spear_clockevent_init(void) |
| 194 | { |
| 195 | u32 tick_rate; |
| 196 | |
| 197 | /* program the prescaler */ |
| 198 | writew(CTRL_PRESCALER16, gpt_base + CR(CLKEVT)); |
| 199 | |
| 200 | tick_rate = clk_get_rate(gpt_clk); |
| 201 | tick_rate >>= CTRL_PRESCALER16; |
| 202 | |
Linus Walleij | 4bd4894 | 2010-07-19 20:55:46 +0100 | [diff] [blame] | 203 | clockevents_calc_mult_shift(&clkevt, tick_rate, SPEAR_MIN_RANGE); |
viresh kumar | 986435e | 2010-04-01 12:30:49 +0100 | [diff] [blame] | 204 | |
| 205 | clkevt.max_delta_ns = clockevent_delta2ns(0xfff0, |
| 206 | &clkevt); |
| 207 | clkevt.min_delta_ns = clockevent_delta2ns(3, &clkevt); |
| 208 | |
| 209 | clkevt.cpumask = cpumask_of(0); |
| 210 | |
| 211 | clockevents_register_device(&clkevt); |
| 212 | |
| 213 | setup_irq(SPEAR_GPT0_CHAN0_IRQ, &spear_timer_irq); |
| 214 | } |
| 215 | |
| 216 | void __init spear_setup_timer(void) |
| 217 | { |
| 218 | struct clk *pll3_clk; |
| 219 | |
| 220 | if (!request_mem_region(SPEAR_GPT0_BASE, SZ_1K, "gpt0")) { |
| 221 | pr_err("%s:cannot get IO addr\n", __func__); |
| 222 | return; |
| 223 | } |
| 224 | |
| 225 | gpt_base = (void __iomem *)ioremap(SPEAR_GPT0_BASE, SZ_1K); |
| 226 | if (!gpt_base) { |
| 227 | pr_err("%s:ioremap failed for gpt\n", __func__); |
| 228 | goto err_mem; |
| 229 | } |
| 230 | |
| 231 | gpt_clk = clk_get_sys("gpt0", NULL); |
| 232 | if (!gpt_clk) { |
| 233 | pr_err("%s:couldn't get clk for gpt\n", __func__); |
| 234 | goto err_iomap; |
| 235 | } |
| 236 | |
| 237 | pll3_clk = clk_get(NULL, "pll3_48m_clk"); |
| 238 | if (!pll3_clk) { |
| 239 | pr_err("%s:couldn't get PLL3 as parent for gpt\n", __func__); |
| 240 | goto err_iomap; |
| 241 | } |
| 242 | |
| 243 | clk_set_parent(gpt_clk, pll3_clk); |
| 244 | |
| 245 | spear_clockevent_init(); |
| 246 | spear_clocksource_init(); |
| 247 | |
| 248 | return; |
| 249 | |
| 250 | err_iomap: |
| 251 | iounmap(gpt_base); |
| 252 | |
| 253 | err_mem: |
| 254 | release_mem_region(SPEAR_GPT0_BASE, SZ_1K); |
| 255 | } |
| 256 | |
| 257 | struct sys_timer spear_sys_timer = { |
| 258 | .init = spear_setup_timer, |
| 259 | }; |