blob: b1300b3f1812977c5c525cd801490f3a9b44b744 [file] [log] [blame]
Bryan Wu1394f032007-05-06 14:50:22 -07001/*
2 * File: arch/blackfin/mach-bf537/ints-priority.c
3 * Based on: arch/blackfin/mach-bf533/ints-priority.c
4 * Author: Michael Hennerich
5 *
6 * Created:
Simon Arlottd2d50aa2007-06-11 15:31:30 +08007 * Description: Set up the interrupt priorities
Bryan Wu1394f032007-05-06 14:50:22 -07008 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/module.h>
Mike Frysinger1f83b8f2007-07-12 22:58:21 +080031#include <linux/irq.h>
Bryan Wu1394f032007-05-06 14:50:22 -070032#include <asm/blackfin.h>
Bryan Wu1394f032007-05-06 14:50:22 -070033
Mike Frysinger9216bbc2008-08-14 14:35:20 +080034void __init program_IAR(void)
Bryan Wu1394f032007-05-06 14:50:22 -070035{
36 /* Program the IAR0 Register with the configured priority */
37 bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
38 ((CONFIG_IRQ_DMA_ERROR - 7) << IRQ_DMA_ERROR_POS) |
39 ((CONFIG_IRQ_ERROR - 7) << IRQ_ERROR_POS) |
40 ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS) |
41 ((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS) |
42 ((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
43 ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
44 ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS));
45
46 bfin_write_SIC_IAR1(((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
47 ((CONFIG_IRQ_TWI - 7) << IRQ_TWI_POS) |
48 ((CONFIG_IRQ_SPI - 7) << IRQ_SPI_POS) |
49 ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
50 ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS) |
51 ((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
52 ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
53 ((CONFIG_IRQ_CAN_RX - 7) << IRQ_CAN_RX_POS));
54
55 bfin_write_SIC_IAR2(((CONFIG_IRQ_CAN_TX - 7) << IRQ_CAN_TX_POS) |
56 ((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) |
57 ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
58 ((CONFIG_IRQ_TMR0 - 7) << IRQ_TMR0_POS) |
59 ((CONFIG_IRQ_TMR1 - 7) << IRQ_TMR1_POS) |
60 ((CONFIG_IRQ_TMR2 - 7) << IRQ_TMR2_POS) |
61 ((CONFIG_IRQ_TMR3 - 7) << IRQ_TMR3_POS) |
62 ((CONFIG_IRQ_TMR4 - 7) << IRQ_TMR4_POS));
63
64 bfin_write_SIC_IAR3(((CONFIG_IRQ_TMR5 - 7) << IRQ_TMR5_POS) |
65 ((CONFIG_IRQ_TMR6 - 7) << IRQ_TMR6_POS) |
66 ((CONFIG_IRQ_TMR7 - 7) << IRQ_TMR7_POS) |
67 ((CONFIG_IRQ_PROG_INTA - 7) << IRQ_PROG_INTA_POS) |
68 ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
69 ((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) |
70 ((CONFIG_IRQ_MEM_DMA1 - 7) << IRQ_MEM_DMA1_POS) |
71 ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS));
72
73 SSYNC();
74}