Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Local APIC handling, local APIC timers |
| 3 | * |
| 4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> |
| 5 | * |
| 6 | * Fixes |
| 7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; |
| 8 | * thanks to Eric Gilmore |
| 9 | * and Rolf G. Tews |
| 10 | * for testing these extensively. |
| 11 | * Maciej W. Rozycki : Various updates and fixes. |
| 12 | * Mikael Pettersson : Power Management for UP-APIC. |
| 13 | * Pavel Machek and |
| 14 | * Mikael Pettersson : PM converted to driver model. |
| 15 | */ |
| 16 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 17 | #include <linux/init.h> |
| 18 | |
| 19 | #include <linux/mm.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 20 | #include <linux/delay.h> |
| 21 | #include <linux/bootmem.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 22 | #include <linux/interrupt.h> |
| 23 | #include <linux/mc146818rtc.h> |
| 24 | #include <linux/kernel_stat.h> |
| 25 | #include <linux/sysdev.h> |
Aaron Durbin | 3992872 | 2006-12-07 02:14:01 +0100 | [diff] [blame] | 26 | #include <linux/ioport.h> |
Yinghai Lu | 773763d | 2008-08-24 02:01:52 -0700 | [diff] [blame] | 27 | #include <linux/cpu.h> |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 28 | #include <linux/clockchips.h> |
Thomas Gleixner | 70a2002 | 2008-01-30 13:30:18 +0100 | [diff] [blame] | 29 | #include <linux/acpi_pmtmr.h> |
Hiroshi Shimamoto | e83a5fd | 2008-01-30 13:32:35 +0100 | [diff] [blame] | 30 | #include <linux/module.h> |
Yinghai Lu | 773763d | 2008-08-24 02:01:52 -0700 | [diff] [blame] | 31 | #include <linux/dmi.h> |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 32 | #include <linux/dmar.h> |
Frederic Weisbecker | bcbc4f2 | 2008-12-09 23:54:20 +0100 | [diff] [blame] | 33 | #include <linux/ftrace.h> |
Jaswinder Singh Rajput | e423e33 | 2009-01-04 16:16:25 +0530 | [diff] [blame] | 34 | #include <linux/smp.h> |
| 35 | #include <linux/nmi.h> |
| 36 | #include <linux/timex.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | |
| 38 | #include <asm/atomic.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 39 | #include <asm/mtrr.h> |
| 40 | #include <asm/mpspec.h> |
Yinghai Lu | efa2559 | 2008-08-19 20:50:36 -0700 | [diff] [blame] | 41 | #include <asm/desc.h> |
Yinghai Lu | 773763d | 2008-08-24 02:01:52 -0700 | [diff] [blame] | 42 | #include <asm/arch_hooks.h> |
Hiroshi Shimamoto | e83a5fd | 2008-01-30 13:32:35 +0100 | [diff] [blame] | 43 | #include <asm/hpet.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 44 | #include <asm/pgalloc.h> |
Yinghai Lu | 773763d | 2008-08-24 02:01:52 -0700 | [diff] [blame] | 45 | #include <asm/i8253.h> |
Andi Kleen | 95833c8 | 2006-01-11 22:44:36 +0100 | [diff] [blame] | 46 | #include <asm/idle.h> |
Andi Kleen | 73dea47 | 2006-02-03 21:50:50 +0100 | [diff] [blame] | 47 | #include <asm/proto.h> |
Andi Kleen | 2c8c0e6 | 2006-09-26 10:52:32 +0200 | [diff] [blame] | 48 | #include <asm/apic.h> |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 49 | #include <asm/i8259.h> |
Jaswinder Singh Rajput | 2bc1379 | 2009-01-11 20:34:47 +0530 | [diff] [blame] | 50 | #include <asm/smp.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 51 | |
Yinghai Lu | 773763d | 2008-08-24 02:01:52 -0700 | [diff] [blame] | 52 | #include <mach_ipi.h> |
Glauber Costa | 5af5573 | 2008-03-25 13:28:56 -0300 | [diff] [blame] | 53 | |
Cyrill Gorcunov | 80e5609 | 2008-08-24 02:01:42 -0700 | [diff] [blame] | 54 | /* |
| 55 | * Sanity check |
| 56 | */ |
| 57 | #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F) |
| 58 | # error SPURIOUS_APIC_VECTOR definition error |
| 59 | #endif |
| 60 | |
Brian Gerst | ec70de8 | 2009-01-27 12:56:47 +0900 | [diff] [blame] | 61 | unsigned int num_processors; |
| 62 | unsigned disabled_cpus __cpuinitdata; |
| 63 | /* Processor that is doing the boot up */ |
| 64 | unsigned int boot_cpu_physical_apicid = -1U; |
| 65 | EXPORT_SYMBOL(boot_cpu_physical_apicid); |
| 66 | unsigned int max_physical_apicid; |
| 67 | |
| 68 | /* Bitmask of physically existing CPUs */ |
| 69 | physid_mask_t phys_cpu_present_map; |
| 70 | |
| 71 | /* |
| 72 | * Map cpu index to physical APIC ID |
| 73 | */ |
| 74 | DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID); |
| 75 | DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID); |
| 76 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); |
| 77 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); |
| 78 | |
Yinghai Lu | b3c5117 | 2008-08-24 02:01:46 -0700 | [diff] [blame] | 79 | #ifdef CONFIG_X86_32 |
| 80 | /* |
| 81 | * Knob to control our willingness to enable the local APIC. |
| 82 | * |
| 83 | * +1=force-enable |
| 84 | */ |
| 85 | static int force_enable_local_apic; |
| 86 | /* |
| 87 | * APIC command line parameters |
| 88 | */ |
| 89 | static int __init parse_lapic(char *arg) |
| 90 | { |
| 91 | force_enable_local_apic = 1; |
| 92 | return 0; |
| 93 | } |
| 94 | early_param("lapic", parse_lapic); |
Yinghai Lu | f28c0ae | 2008-08-24 02:01:49 -0700 | [diff] [blame] | 95 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ |
| 96 | static int enabled_via_apicbase; |
| 97 | |
Yinghai Lu | b3c5117 | 2008-08-24 02:01:46 -0700 | [diff] [blame] | 98 | #endif |
| 99 | |
| 100 | #ifdef CONFIG_X86_64 |
Chris Wright | bc1d99c | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 101 | static int apic_calibrate_pmtmr __initdata; |
Yinghai Lu | b3c5117 | 2008-08-24 02:01:46 -0700 | [diff] [blame] | 102 | static __init int setup_apicpmtimer(char *s) |
| 103 | { |
| 104 | apic_calibrate_pmtmr = 1; |
| 105 | notsc_setup(NULL); |
| 106 | return 0; |
| 107 | } |
| 108 | __setup("apicpmtimer", setup_apicpmtimer); |
| 109 | #endif |
| 110 | |
Yinghai Lu | 49899ea | 2008-08-24 02:01:47 -0700 | [diff] [blame] | 111 | #ifdef CONFIG_X86_64 |
| 112 | #define HAVE_X2APIC |
| 113 | #endif |
| 114 | |
| 115 | #ifdef HAVE_X2APIC |
Suresh Siddha | 89027d3 | 2008-07-10 11:16:56 -0700 | [diff] [blame] | 116 | int x2apic; |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 117 | /* x2apic enabled before OS handover */ |
Jaswinder Singh | b6b301a | 2008-12-23 21:52:33 +0530 | [diff] [blame] | 118 | static int x2apic_preenabled; |
| 119 | static int disable_x2apic; |
Yinghai Lu | 49899ea | 2008-08-24 02:01:47 -0700 | [diff] [blame] | 120 | static __init int setup_nox2apic(char *str) |
| 121 | { |
| 122 | disable_x2apic = 1; |
| 123 | setup_clear_cpu_cap(X86_FEATURE_X2APIC); |
| 124 | return 0; |
| 125 | } |
| 126 | early_param("nox2apic", setup_nox2apic); |
| 127 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 128 | |
Yinghai Lu | b3c5117 | 2008-08-24 02:01:46 -0700 | [diff] [blame] | 129 | unsigned long mp_lapic_addr; |
| 130 | int disable_apic; |
| 131 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ |
| 132 | static int disable_apic_timer __cpuinitdata; |
Hiroshi Shimamoto | e83a5fd | 2008-01-30 13:32:35 +0100 | [diff] [blame] | 133 | /* Local APIC timer works in C2 */ |
Linus Torvalds | 2e7c283 | 2007-03-23 11:32:31 -0700 | [diff] [blame] | 134 | int local_apic_timer_c2_ok; |
| 135 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); |
| 136 | |
Yinghai Lu | efa2559 | 2008-08-19 20:50:36 -0700 | [diff] [blame] | 137 | int first_system_vector = 0xfe; |
| 138 | |
Hiroshi Shimamoto | e83a5fd | 2008-01-30 13:32:35 +0100 | [diff] [blame] | 139 | /* |
| 140 | * Debug level, exported for io_apic.c |
| 141 | */ |
Maciej W. Rozycki | baa1318 | 2008-07-14 18:44:51 +0100 | [diff] [blame] | 142 | unsigned int apic_verbosity; |
Hiroshi Shimamoto | e83a5fd | 2008-01-30 13:32:35 +0100 | [diff] [blame] | 143 | |
Cyrill Gorcunov | 89c38c2 | 2008-08-24 02:01:43 -0700 | [diff] [blame] | 144 | int pic_mode; |
| 145 | |
Alexey Starikovskiy | bab4b27 | 2008-05-19 19:47:03 +0400 | [diff] [blame] | 146 | /* Have we found an MP table */ |
| 147 | int smp_found_config; |
| 148 | |
Aaron Durbin | 3992872 | 2006-12-07 02:14:01 +0100 | [diff] [blame] | 149 | static struct resource lapic_resource = { |
| 150 | .name = "Local APIC", |
| 151 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, |
| 152 | }; |
| 153 | |
Thomas Gleixner | d03030e | 2007-10-12 23:04:06 +0200 | [diff] [blame] | 154 | static unsigned int calibration_result; |
| 155 | |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 156 | static int lapic_next_event(unsigned long delta, |
| 157 | struct clock_event_device *evt); |
| 158 | static void lapic_timer_setup(enum clock_event_mode mode, |
| 159 | struct clock_event_device *evt); |
Mike Travis | 9628937 | 2008-12-31 18:08:46 -0800 | [diff] [blame] | 160 | static void lapic_timer_broadcast(const struct cpumask *mask); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 161 | static void apic_pm_activate(void); |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 162 | |
Cyrill Gorcunov | 274cfe5 | 2008-08-16 23:21:53 +0400 | [diff] [blame] | 163 | /* |
| 164 | * The local apic timer can be used for any function which is CPU local. |
| 165 | */ |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 166 | static struct clock_event_device lapic_clockevent = { |
| 167 | .name = "lapic", |
| 168 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
| 169 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, |
| 170 | .shift = 32, |
| 171 | .set_mode = lapic_timer_setup, |
| 172 | .set_next_event = lapic_next_event, |
| 173 | .broadcast = lapic_timer_broadcast, |
| 174 | .rating = 100, |
| 175 | .irq = -1, |
| 176 | }; |
| 177 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); |
| 178 | |
Andi Kleen | d343289 | 2008-01-30 13:33:17 +0100 | [diff] [blame] | 179 | static unsigned long apic_phys; |
| 180 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 181 | /* |
| 182 | * Get the LAPIC version |
| 183 | */ |
| 184 | static inline int lapic_get_version(void) |
| 185 | { |
| 186 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
| 187 | } |
| 188 | |
| 189 | /* |
Cyrill Gorcunov | 9c80386 | 2008-08-16 23:21:54 +0400 | [diff] [blame] | 190 | * Check, if the APIC is integrated or a separate chip |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 191 | */ |
| 192 | static inline int lapic_is_integrated(void) |
| 193 | { |
Cyrill Gorcunov | 9c80386 | 2008-08-16 23:21:54 +0400 | [diff] [blame] | 194 | #ifdef CONFIG_X86_64 |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 195 | return 1; |
Cyrill Gorcunov | 9c80386 | 2008-08-16 23:21:54 +0400 | [diff] [blame] | 196 | #else |
| 197 | return APIC_INTEGRATED(lapic_get_version()); |
| 198 | #endif |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 199 | } |
| 200 | |
| 201 | /* |
| 202 | * Check, whether this is a modern or a first generation APIC |
| 203 | */ |
| 204 | static int modern_apic(void) |
| 205 | { |
| 206 | /* AMD systems use old APIC versions, so check the CPU */ |
| 207 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && |
| 208 | boot_cpu_data.x86 >= 0xf) |
| 209 | return 1; |
| 210 | return lapic_get_version() >= 0x14; |
| 211 | } |
| 212 | |
Cyrill Gorcunov | 274cfe5 | 2008-08-16 23:21:53 +0400 | [diff] [blame] | 213 | /* |
| 214 | * Paravirt kernels also might be using these below ops. So we still |
| 215 | * use generic apic_read()/apic_write(), which might be pointing to different |
| 216 | * ops in PARAVIRT case. |
| 217 | */ |
Suresh Siddha | 1b374e4 | 2008-07-10 11:16:49 -0700 | [diff] [blame] | 218 | void xapic_wait_icr_idle(void) |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 219 | { |
| 220 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) |
| 221 | cpu_relax(); |
| 222 | } |
| 223 | |
Suresh Siddha | 1b374e4 | 2008-07-10 11:16:49 -0700 | [diff] [blame] | 224 | u32 safe_xapic_wait_icr_idle(void) |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 225 | { |
| 226 | u32 send_status; |
| 227 | int timeout; |
| 228 | |
| 229 | timeout = 0; |
| 230 | do { |
| 231 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; |
| 232 | if (!send_status) |
| 233 | break; |
| 234 | udelay(100); |
| 235 | } while (timeout++ < 1000); |
| 236 | |
| 237 | return send_status; |
| 238 | } |
| 239 | |
Suresh Siddha | 1b374e4 | 2008-07-10 11:16:49 -0700 | [diff] [blame] | 240 | void xapic_icr_write(u32 low, u32 id) |
| 241 | { |
Cyrill Gorcunov | ed4e5ec | 2008-08-15 13:51:20 +0200 | [diff] [blame] | 242 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
Suresh Siddha | 1b374e4 | 2008-07-10 11:16:49 -0700 | [diff] [blame] | 243 | apic_write(APIC_ICR, low); |
| 244 | } |
| 245 | |
Jaswinder Singh Rajput | ec8c842 | 2008-12-30 22:46:36 +0530 | [diff] [blame] | 246 | static u64 xapic_icr_read(void) |
Suresh Siddha | 1b374e4 | 2008-07-10 11:16:49 -0700 | [diff] [blame] | 247 | { |
| 248 | u32 icr1, icr2; |
| 249 | |
| 250 | icr2 = apic_read(APIC_ICR2); |
| 251 | icr1 = apic_read(APIC_ICR); |
| 252 | |
Cyrill Gorcunov | cf9768d7 | 2008-08-16 23:21:55 +0400 | [diff] [blame] | 253 | return icr1 | ((u64)icr2 << 32); |
Suresh Siddha | 1b374e4 | 2008-07-10 11:16:49 -0700 | [diff] [blame] | 254 | } |
| 255 | |
| 256 | static struct apic_ops xapic_ops = { |
| 257 | .read = native_apic_mem_read, |
| 258 | .write = native_apic_mem_write, |
Suresh Siddha | 1b374e4 | 2008-07-10 11:16:49 -0700 | [diff] [blame] | 259 | .icr_read = xapic_icr_read, |
| 260 | .icr_write = xapic_icr_write, |
| 261 | .wait_icr_idle = xapic_wait_icr_idle, |
| 262 | .safe_wait_icr_idle = safe_xapic_wait_icr_idle, |
| 263 | }; |
| 264 | |
| 265 | struct apic_ops __read_mostly *apic_ops = &xapic_ops; |
Suresh Siddha | 1b374e4 | 2008-07-10 11:16:49 -0700 | [diff] [blame] | 266 | EXPORT_SYMBOL_GPL(apic_ops); |
| 267 | |
Yinghai Lu | 49899ea | 2008-08-24 02:01:47 -0700 | [diff] [blame] | 268 | #ifdef HAVE_X2APIC |
Suresh Siddha | 13c88fb5 | 2008-07-10 11:16:52 -0700 | [diff] [blame] | 269 | static void x2apic_wait_icr_idle(void) |
| 270 | { |
| 271 | /* no need to wait for icr idle in x2apic */ |
| 272 | return; |
| 273 | } |
| 274 | |
| 275 | static u32 safe_x2apic_wait_icr_idle(void) |
| 276 | { |
| 277 | /* no need to wait for icr idle in x2apic */ |
| 278 | return 0; |
| 279 | } |
| 280 | |
| 281 | void x2apic_icr_write(u32 low, u32 id) |
| 282 | { |
| 283 | wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); |
| 284 | } |
| 285 | |
Jaswinder Singh Rajput | ec8c842 | 2008-12-30 22:46:36 +0530 | [diff] [blame] | 286 | static u64 x2apic_icr_read(void) |
Suresh Siddha | 13c88fb5 | 2008-07-10 11:16:52 -0700 | [diff] [blame] | 287 | { |
| 288 | unsigned long val; |
| 289 | |
| 290 | rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); |
| 291 | return val; |
| 292 | } |
| 293 | |
| 294 | static struct apic_ops x2apic_ops = { |
| 295 | .read = native_apic_msr_read, |
| 296 | .write = native_apic_msr_write, |
Suresh Siddha | 13c88fb5 | 2008-07-10 11:16:52 -0700 | [diff] [blame] | 297 | .icr_read = x2apic_icr_read, |
| 298 | .icr_write = x2apic_icr_write, |
| 299 | .wait_icr_idle = x2apic_wait_icr_idle, |
| 300 | .safe_wait_icr_idle = safe_x2apic_wait_icr_idle, |
| 301 | }; |
Yinghai Lu | 49899ea | 2008-08-24 02:01:47 -0700 | [diff] [blame] | 302 | #endif |
Suresh Siddha | 13c88fb5 | 2008-07-10 11:16:52 -0700 | [diff] [blame] | 303 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 304 | /** |
| 305 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 |
| 306 | */ |
Jan Beulich | e942710 | 2008-01-30 13:31:24 +0100 | [diff] [blame] | 307 | void __cpuinit enable_NMI_through_LVT0(void) |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 308 | { |
| 309 | unsigned int v; |
| 310 | |
| 311 | /* unmask and set to NMI */ |
| 312 | v = APIC_DM_NMI; |
Cyrill Gorcunov | d4c63ec | 2008-07-24 13:52:29 +0200 | [diff] [blame] | 313 | |
| 314 | /* Level triggered for 82489DX (32bit mode) */ |
| 315 | if (!lapic_is_integrated()) |
| 316 | v |= APIC_LVT_LEVEL_TRIGGER; |
| 317 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 318 | apic_write(APIC_LVT0, v); |
| 319 | } |
| 320 | |
Cyrill Gorcunov | 7c37e48 | 2008-08-24 02:01:40 -0700 | [diff] [blame] | 321 | #ifdef CONFIG_X86_32 |
| 322 | /** |
| 323 | * get_physical_broadcast - Get number of physical broadcast IDs |
| 324 | */ |
| 325 | int get_physical_broadcast(void) |
| 326 | { |
| 327 | return modern_apic() ? 0xff : 0xf; |
| 328 | } |
| 329 | #endif |
| 330 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 331 | /** |
| 332 | * lapic_get_maxlvt - get the maximum number of local vector table entries |
| 333 | */ |
| 334 | int lapic_get_maxlvt(void) |
| 335 | { |
Cyrill Gorcunov | 36a028d | 2008-07-24 13:52:28 +0200 | [diff] [blame] | 336 | unsigned int v; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 337 | |
| 338 | v = apic_read(APIC_LVR); |
Cyrill Gorcunov | 36a028d | 2008-07-24 13:52:28 +0200 | [diff] [blame] | 339 | /* |
| 340 | * - we always have APIC integrated on 64bit mode |
| 341 | * - 82489DXs do not report # of LVT entries |
| 342 | */ |
| 343 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 344 | } |
| 345 | |
| 346 | /* |
Cyrill Gorcunov | 274cfe5 | 2008-08-16 23:21:53 +0400 | [diff] [blame] | 347 | * Local APIC timer |
| 348 | */ |
| 349 | |
Cyrill Gorcunov | c40aaec | 2008-08-18 20:45:55 +0400 | [diff] [blame] | 350 | /* Clock divisor */ |
Cyrill Gorcunov | c40aaec | 2008-08-18 20:45:55 +0400 | [diff] [blame] | 351 | #define APIC_DIVISOR 16 |
Cyrill Gorcunov | f07f4f9 | 2008-08-15 13:51:21 +0200 | [diff] [blame] | 352 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 353 | /* |
| 354 | * This function sets up the local APIC timer, with a timeout of |
| 355 | * 'clocks' APIC bus clock. During calibration we actually call |
| 356 | * this function twice on the boot CPU, once with a bogus timeout |
| 357 | * value, second time for real. The other (noncalibrating) CPUs |
| 358 | * call this function only once, with the real, calibrated value. |
| 359 | * |
| 360 | * We do reads before writes even if unnecessary, to get around the |
| 361 | * P5 APIC double write bug. |
| 362 | */ |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 363 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
| 364 | { |
| 365 | unsigned int lvtt_value, tmp_value; |
| 366 | |
| 367 | lvtt_value = LOCAL_TIMER_VECTOR; |
| 368 | if (!oneshot) |
| 369 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; |
Cyrill Gorcunov | f07f4f9 | 2008-08-15 13:51:21 +0200 | [diff] [blame] | 370 | if (!lapic_is_integrated()) |
| 371 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); |
| 372 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 373 | if (!irqen) |
| 374 | lvtt_value |= APIC_LVT_MASKED; |
| 375 | |
| 376 | apic_write(APIC_LVTT, lvtt_value); |
| 377 | |
| 378 | /* |
| 379 | * Divide PICLK by 16 |
| 380 | */ |
| 381 | tmp_value = apic_read(APIC_TDCR); |
Cyrill Gorcunov | c40aaec | 2008-08-18 20:45:55 +0400 | [diff] [blame] | 382 | apic_write(APIC_TDCR, |
| 383 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | |
| 384 | APIC_TDR_DIV_16); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 385 | |
| 386 | if (!oneshot) |
Cyrill Gorcunov | f07f4f9 | 2008-08-15 13:51:21 +0200 | [diff] [blame] | 387 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 388 | } |
| 389 | |
| 390 | /* |
Robert Richter | 7b83dae | 2008-01-30 13:30:40 +0100 | [diff] [blame] | 391 | * Setup extended LVT, AMD specific (K8, family 10h) |
| 392 | * |
| 393 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and |
| 394 | * MCE interrupts are supported. Thus MCE offset must be set to 0. |
Robert Richter | 286f571 | 2008-07-22 21:08:46 +0200 | [diff] [blame] | 395 | * |
| 396 | * If mask=1, the LVT entry does not generate interrupts while mask=0 |
| 397 | * enables the vector. See also the BKDGs. |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 398 | */ |
Robert Richter | 7b83dae | 2008-01-30 13:30:40 +0100 | [diff] [blame] | 399 | |
| 400 | #define APIC_EILVT_LVTOFF_MCE 0 |
| 401 | #define APIC_EILVT_LVTOFF_IBS 1 |
| 402 | |
| 403 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 404 | { |
Robert Richter | 7b83dae | 2008-01-30 13:30:40 +0100 | [diff] [blame] | 405 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 406 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; |
| 407 | |
| 408 | apic_write(reg, v); |
| 409 | } |
| 410 | |
Robert Richter | 7b83dae | 2008-01-30 13:30:40 +0100 | [diff] [blame] | 411 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) |
| 412 | { |
| 413 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); |
| 414 | return APIC_EILVT_LVTOFF_MCE; |
| 415 | } |
| 416 | |
| 417 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) |
| 418 | { |
| 419 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); |
| 420 | return APIC_EILVT_LVTOFF_IBS; |
| 421 | } |
Robert Richter | 6aa360e | 2008-07-23 15:28:14 +0200 | [diff] [blame] | 422 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs); |
Robert Richter | 7b83dae | 2008-01-30 13:30:40 +0100 | [diff] [blame] | 423 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 424 | /* |
| 425 | * Program the next event, relative to now |
| 426 | */ |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 427 | static int lapic_next_event(unsigned long delta, |
| 428 | struct clock_event_device *evt) |
| 429 | { |
| 430 | apic_write(APIC_TMICT, delta); |
| 431 | return 0; |
| 432 | } |
| 433 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 434 | /* |
| 435 | * Setup the lapic timer in periodic or oneshot mode |
| 436 | */ |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 437 | static void lapic_timer_setup(enum clock_event_mode mode, |
| 438 | struct clock_event_device *evt) |
| 439 | { |
| 440 | unsigned long flags; |
| 441 | unsigned int v; |
| 442 | |
| 443 | /* Lapic used as dummy for broadcast ? */ |
| 444 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) |
| 445 | return; |
| 446 | |
| 447 | local_irq_save(flags); |
| 448 | |
| 449 | switch (mode) { |
| 450 | case CLOCK_EVT_MODE_PERIODIC: |
| 451 | case CLOCK_EVT_MODE_ONESHOT: |
| 452 | __setup_APIC_LVTT(calibration_result, |
| 453 | mode != CLOCK_EVT_MODE_PERIODIC, 1); |
| 454 | break; |
| 455 | case CLOCK_EVT_MODE_UNUSED: |
| 456 | case CLOCK_EVT_MODE_SHUTDOWN: |
| 457 | v = apic_read(APIC_LVTT); |
| 458 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); |
| 459 | apic_write(APIC_LVTT, v); |
Thomas Gleixner | a98f8fd | 2008-11-06 01:13:39 +0100 | [diff] [blame] | 460 | apic_write(APIC_TMICT, 0xffffffff); |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 461 | break; |
| 462 | case CLOCK_EVT_MODE_RESUME: |
| 463 | /* Nothing to do here */ |
| 464 | break; |
| 465 | } |
| 466 | |
| 467 | local_irq_restore(flags); |
| 468 | } |
| 469 | |
| 470 | /* |
| 471 | * Local APIC timer broadcast function |
| 472 | */ |
Mike Travis | 9628937 | 2008-12-31 18:08:46 -0800 | [diff] [blame] | 473 | static void lapic_timer_broadcast(const struct cpumask *mask) |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 474 | { |
| 475 | #ifdef CONFIG_SMP |
Ingo Molnar | dac5f41 | 2009-01-28 15:42:24 +0100 | [diff] [blame] | 476 | apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 477 | #endif |
| 478 | } |
| 479 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 480 | /* |
| 481 | * Setup the local APIC timer for this CPU. Copy the initilized values |
| 482 | * of the boot CPU and register the clock event in the framework. |
| 483 | */ |
Cyrill Gorcunov | db4b552 | 2008-08-24 02:01:39 -0700 | [diff] [blame] | 484 | static void __cpuinit setup_APIC_timer(void) |
Fernando Luis VazquezCao | 8339e9f | 2007-05-02 19:27:17 +0200 | [diff] [blame] | 485 | { |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 486 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); |
| 487 | |
| 488 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
Rusty Russell | 320ab2b | 2008-12-13 21:20:26 +1030 | [diff] [blame] | 489 | levt->cpumask = cpumask_of(smp_processor_id()); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 490 | |
| 491 | clockevents_register_device(levt); |
Fernando Luis VazquezCao | 8339e9f | 2007-05-02 19:27:17 +0200 | [diff] [blame] | 492 | } |
| 493 | |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 494 | /* |
| 495 | * In this functions we calibrate APIC bus clocks to the external timer. |
| 496 | * |
| 497 | * We want to do the calibration only once since we want to have local timer |
| 498 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus |
| 499 | * frequency. |
| 500 | * |
| 501 | * This was previously done by reading the PIT/HPET and waiting for a wrap |
| 502 | * around to find out, that a tick has elapsed. I have a box, where the PIT |
| 503 | * readout is broken, so it never gets out of the wait loop again. This was |
| 504 | * also reported by others. |
| 505 | * |
| 506 | * Monitoring the jiffies value is inaccurate and the clockevents |
| 507 | * infrastructure allows us to do a simple substitution of the interrupt |
| 508 | * handler. |
| 509 | * |
| 510 | * The calibration routine also uses the pm_timer when possible, as the PIT |
| 511 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes |
| 512 | * back to normal later in the boot process). |
| 513 | */ |
| 514 | |
| 515 | #define LAPIC_CAL_LOOPS (HZ/10) |
| 516 | |
| 517 | static __initdata int lapic_cal_loops = -1; |
| 518 | static __initdata long lapic_cal_t1, lapic_cal_t2; |
| 519 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; |
| 520 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; |
| 521 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; |
| 522 | |
| 523 | /* |
| 524 | * Temporary interrupt handler. |
| 525 | */ |
| 526 | static void __init lapic_cal_handler(struct clock_event_device *dev) |
| 527 | { |
| 528 | unsigned long long tsc = 0; |
| 529 | long tapic = apic_read(APIC_TMCCT); |
| 530 | unsigned long pm = acpi_pm_read_early(); |
| 531 | |
| 532 | if (cpu_has_tsc) |
| 533 | rdtscll(tsc); |
| 534 | |
| 535 | switch (lapic_cal_loops++) { |
| 536 | case 0: |
| 537 | lapic_cal_t1 = tapic; |
| 538 | lapic_cal_tsc1 = tsc; |
| 539 | lapic_cal_pm1 = pm; |
| 540 | lapic_cal_j1 = jiffies; |
| 541 | break; |
| 542 | |
| 543 | case LAPIC_CAL_LOOPS: |
| 544 | lapic_cal_t2 = tapic; |
| 545 | lapic_cal_tsc2 = tsc; |
| 546 | if (pm < lapic_cal_pm1) |
| 547 | pm += ACPI_PM_OVRRUN; |
| 548 | lapic_cal_pm2 = pm; |
| 549 | lapic_cal_j2 = jiffies; |
| 550 | break; |
| 551 | } |
| 552 | } |
| 553 | |
Cyrill Gorcunov | b189892 | 2008-09-12 23:58:24 +0400 | [diff] [blame] | 554 | static int __init calibrate_by_pmtimer(long deltapm, long *delta) |
| 555 | { |
| 556 | const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; |
| 557 | const long pm_thresh = pm_100ms / 100; |
| 558 | unsigned long mult; |
| 559 | u64 res; |
| 560 | |
| 561 | #ifndef CONFIG_X86_PM_TIMER |
| 562 | return -1; |
| 563 | #endif |
| 564 | |
| 565 | apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm); |
| 566 | |
| 567 | /* Check, if the PM timer is available */ |
| 568 | if (!deltapm) |
| 569 | return -1; |
| 570 | |
| 571 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); |
| 572 | |
| 573 | if (deltapm > (pm_100ms - pm_thresh) && |
| 574 | deltapm < (pm_100ms + pm_thresh)) { |
| 575 | apic_printk(APIC_VERBOSE, "... PM timer result ok\n"); |
| 576 | } else { |
| 577 | res = (((u64)deltapm) * mult) >> 22; |
| 578 | do_div(res, 1000000); |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 579 | pr_warning("APIC calibration not consistent " |
Cyrill Gorcunov | b189892 | 2008-09-12 23:58:24 +0400 | [diff] [blame] | 580 | "with PM Timer: %ldms instead of 100ms\n", |
| 581 | (long)res); |
| 582 | /* Correct the lapic counter value */ |
| 583 | res = (((u64)(*delta)) * pm_100ms); |
| 584 | do_div(res, deltapm); |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 585 | pr_info("APIC delta adjusted to PM-Timer: " |
Cyrill Gorcunov | b189892 | 2008-09-12 23:58:24 +0400 | [diff] [blame] | 586 | "%lu (%ld)\n", (unsigned long)res, *delta); |
| 587 | *delta = (long)res; |
| 588 | } |
| 589 | |
| 590 | return 0; |
| 591 | } |
| 592 | |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 593 | static int __init calibrate_APIC_clock(void) |
| 594 | { |
| 595 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 596 | void (*real_handler)(struct clock_event_device *dev); |
| 597 | unsigned long deltaj; |
Cyrill Gorcunov | b189892 | 2008-09-12 23:58:24 +0400 | [diff] [blame] | 598 | long delta; |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 599 | int pm_referenced = 0; |
| 600 | |
| 601 | local_irq_disable(); |
| 602 | |
| 603 | /* Replace the global interrupt handler */ |
| 604 | real_handler = global_clock_event->event_handler; |
| 605 | global_clock_event->event_handler = lapic_cal_handler; |
| 606 | |
| 607 | /* |
Cyrill Gorcunov | 81608f3 | 2008-10-10 19:00:17 +0400 | [diff] [blame] | 608 | * Setup the APIC counter to maximum. There is no way the lapic |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 609 | * can underflow in the 100ms detection time frame |
| 610 | */ |
Cyrill Gorcunov | 81608f3 | 2008-10-10 19:00:17 +0400 | [diff] [blame] | 611 | __setup_APIC_LVTT(0xffffffff, 0, 0); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 612 | |
| 613 | /* Let the interrupts run */ |
| 614 | local_irq_enable(); |
| 615 | |
| 616 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) |
| 617 | cpu_relax(); |
| 618 | |
| 619 | local_irq_disable(); |
| 620 | |
| 621 | /* Restore the real event handler */ |
| 622 | global_clock_event->event_handler = real_handler; |
| 623 | |
| 624 | /* Build delta t1-t2 as apic timer counts down */ |
| 625 | delta = lapic_cal_t1 - lapic_cal_t2; |
| 626 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); |
| 627 | |
Cyrill Gorcunov | b189892 | 2008-09-12 23:58:24 +0400 | [diff] [blame] | 628 | /* we trust the PM based calibration if possible */ |
| 629 | pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, |
| 630 | &delta); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 631 | |
| 632 | /* Calculate the scaled math multiplication factor */ |
| 633 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, |
| 634 | lapic_clockevent.shift); |
| 635 | lapic_clockevent.max_delta_ns = |
| 636 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); |
| 637 | lapic_clockevent.min_delta_ns = |
| 638 | clockevent_delta2ns(0xF, &lapic_clockevent); |
| 639 | |
| 640 | calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; |
| 641 | |
| 642 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); |
| 643 | apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult); |
| 644 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", |
| 645 | calibration_result); |
| 646 | |
| 647 | if (cpu_has_tsc) { |
| 648 | delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); |
| 649 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " |
| 650 | "%ld.%04ld MHz.\n", |
| 651 | (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ), |
| 652 | (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ)); |
| 653 | } |
| 654 | |
| 655 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " |
| 656 | "%u.%04u MHz.\n", |
| 657 | calibration_result / (1000000 / HZ), |
| 658 | calibration_result % (1000000 / HZ)); |
| 659 | |
| 660 | /* |
| 661 | * Do a sanity check on the APIC calibration result |
| 662 | */ |
| 663 | if (calibration_result < (1000000 / HZ)) { |
| 664 | local_irq_enable(); |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 665 | pr_warning("APIC frequency too slow, disabling apic timer\n"); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 666 | return -1; |
| 667 | } |
| 668 | |
| 669 | levt->features &= ~CLOCK_EVT_FEAT_DUMMY; |
| 670 | |
Cyrill Gorcunov | b189892 | 2008-09-12 23:58:24 +0400 | [diff] [blame] | 671 | /* |
| 672 | * PM timer calibration failed or not turned on |
| 673 | * so lets try APIC timer based calibration |
| 674 | */ |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 675 | if (!pm_referenced) { |
| 676 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); |
| 677 | |
| 678 | /* |
| 679 | * Setup the apic timer manually |
| 680 | */ |
| 681 | levt->event_handler = lapic_cal_handler; |
| 682 | lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); |
| 683 | lapic_cal_loops = -1; |
| 684 | |
| 685 | /* Let the interrupts run */ |
| 686 | local_irq_enable(); |
| 687 | |
| 688 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) |
| 689 | cpu_relax(); |
| 690 | |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 691 | /* Stop the lapic timer */ |
| 692 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); |
| 693 | |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 694 | /* Jiffies delta */ |
| 695 | deltaj = lapic_cal_j2 - lapic_cal_j1; |
| 696 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); |
| 697 | |
| 698 | /* Check, if the jiffies result is consistent */ |
| 699 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) |
| 700 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); |
| 701 | else |
| 702 | levt->features |= CLOCK_EVT_FEAT_DUMMY; |
| 703 | } else |
| 704 | local_irq_enable(); |
| 705 | |
| 706 | if (levt->features & CLOCK_EVT_FEAT_DUMMY) { |
Jaswinder Singh Rajput | e423e33 | 2009-01-04 16:16:25 +0530 | [diff] [blame] | 707 | pr_warning("APIC timer disabled due to verification failure\n"); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 708 | return -1; |
| 709 | } |
| 710 | |
| 711 | return 0; |
| 712 | } |
| 713 | |
Hiroshi Shimamoto | e83a5fd | 2008-01-30 13:32:35 +0100 | [diff] [blame] | 714 | /* |
| 715 | * Setup the boot APIC |
| 716 | * |
| 717 | * Calibrate and verify the result. |
| 718 | */ |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 719 | void __init setup_boot_APIC_clock(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 720 | { |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 721 | /* |
Cyrill Gorcunov | 274cfe5 | 2008-08-16 23:21:53 +0400 | [diff] [blame] | 722 | * The local apic timer can be disabled via the kernel |
| 723 | * commandline or from the CPU detection code. Register the lapic |
| 724 | * timer as a dummy clock event source on SMP systems, so the |
| 725 | * broadcast mechanism is used. On UP systems simply ignore it. |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 726 | */ |
| 727 | if (disable_apic_timer) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 728 | pr_info("Disabling APIC timer\n"); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 729 | /* No broadcast on UP ! */ |
Thomas Gleixner | 9d09951 | 2008-01-30 13:33:04 +0100 | [diff] [blame] | 730 | if (num_possible_cpus() > 1) { |
| 731 | lapic_clockevent.mult = 1; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 732 | setup_APIC_timer(); |
Thomas Gleixner | 9d09951 | 2008-01-30 13:33:04 +0100 | [diff] [blame] | 733 | } |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 734 | return; |
| 735 | } |
Thomas Gleixner | 6935d1f | 2007-07-21 17:10:17 +0200 | [diff] [blame] | 736 | |
Cyrill Gorcunov | 274cfe5 | 2008-08-16 23:21:53 +0400 | [diff] [blame] | 737 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
| 738 | "calibrating APIC timer ...\n"); |
| 739 | |
Cyrill Gorcunov | 89b3b1f | 2008-07-15 21:02:54 +0400 | [diff] [blame] | 740 | if (calibrate_APIC_clock()) { |
Thomas Gleixner | c2b84b3 | 2008-01-30 13:33:04 +0100 | [diff] [blame] | 741 | /* No broadcast on UP ! */ |
| 742 | if (num_possible_cpus() > 1) |
| 743 | setup_APIC_timer(); |
| 744 | return; |
| 745 | } |
| 746 | |
| 747 | /* |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 748 | * If nmi_watchdog is set to IO_APIC, we need the |
| 749 | * PIT/HPET going. Otherwise register lapic as a dummy |
| 750 | * device. |
| 751 | */ |
| 752 | if (nmi_watchdog != NMI_IO_APIC) |
| 753 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; |
| 754 | else |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 755 | pr_warning("APIC timer registered as dummy," |
Cyrill Gorcunov | 116f570 | 2008-06-24 22:52:04 +0200 | [diff] [blame] | 756 | " due to nmi_watchdog=%d!\n", nmi_watchdog); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 757 | |
Cyrill Gorcunov | 274cfe5 | 2008-08-16 23:21:53 +0400 | [diff] [blame] | 758 | /* Setup the lapic or request the broadcast */ |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 759 | setup_APIC_timer(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 760 | } |
| 761 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 762 | void __cpuinit setup_secondary_APIC_clock(void) |
| 763 | { |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 764 | setup_APIC_timer(); |
| 765 | } |
| 766 | |
| 767 | /* |
| 768 | * The guts of the apic timer interrupt |
| 769 | */ |
| 770 | static void local_apic_timer_interrupt(void) |
| 771 | { |
| 772 | int cpu = smp_processor_id(); |
| 773 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); |
| 774 | |
| 775 | /* |
| 776 | * Normally we should not be here till LAPIC has been initialized but |
| 777 | * in some cases like kdump, its possible that there is a pending LAPIC |
| 778 | * timer interrupt from previous kernel's context and is delivered in |
| 779 | * new kernel the moment interrupts are enabled. |
| 780 | * |
| 781 | * Interrupts are enabled early and LAPIC is setup much later, hence |
| 782 | * its possible that when we get here evt->event_handler is NULL. |
| 783 | * Check for event_handler being NULL and discard the interrupt as |
| 784 | * spurious. |
| 785 | */ |
| 786 | if (!evt->event_handler) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 787 | pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 788 | /* Switch it off */ |
| 789 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); |
| 790 | return; |
| 791 | } |
| 792 | |
| 793 | /* |
| 794 | * the NMI deadlock-detector uses this. |
| 795 | */ |
Hiroshi Shimamoto | 915b0d0 | 2008-12-08 19:19:26 -0800 | [diff] [blame] | 796 | inc_irq_stat(apic_timer_irqs); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 797 | |
| 798 | evt->event_handler(evt); |
| 799 | } |
| 800 | |
| 801 | /* |
| 802 | * Local APIC timer interrupt. This is the most natural way for doing |
| 803 | * local interrupts, but local timer interrupts can be emulated by |
| 804 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] |
| 805 | * |
| 806 | * [ if a single-CPU system runs an SMP kernel then we call the local |
| 807 | * interrupt as well. Thus we cannot inline the local irq ... ] |
| 808 | */ |
Frederic Weisbecker | bcbc4f2 | 2008-12-09 23:54:20 +0100 | [diff] [blame] | 809 | void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 810 | { |
| 811 | struct pt_regs *old_regs = set_irq_regs(regs); |
| 812 | |
| 813 | /* |
| 814 | * NOTE! We'd better ACK the irq immediately, |
| 815 | * because timer handling can be slow. |
| 816 | */ |
| 817 | ack_APIC_irq(); |
| 818 | /* |
| 819 | * update_process_times() expects us to have done irq_enter(). |
| 820 | * Besides, if we don't timer interrupts ignore the global |
| 821 | * interrupt lock, which is the WrongThing (tm) to do. |
| 822 | */ |
| 823 | exit_idle(); |
| 824 | irq_enter(); |
| 825 | local_apic_timer_interrupt(); |
| 826 | irq_exit(); |
Cyrill Gorcunov | 274cfe5 | 2008-08-16 23:21:53 +0400 | [diff] [blame] | 827 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 828 | set_irq_regs(old_regs); |
| 829 | } |
| 830 | |
| 831 | int setup_profiling_timer(unsigned int multiplier) |
| 832 | { |
| 833 | return -EINVAL; |
| 834 | } |
| 835 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 836 | /* |
| 837 | * Local APIC start and shutdown |
| 838 | */ |
| 839 | |
| 840 | /** |
| 841 | * clear_local_APIC - shutdown the local APIC |
| 842 | * |
| 843 | * This is called, when a CPU is disabled and before rebooting, so the state of |
| 844 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS |
| 845 | * leftovers during boot. |
| 846 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 847 | void clear_local_APIC(void) |
| 848 | { |
Chuck Ebbert | 2584a82 | 2008-05-20 18:18:12 -0400 | [diff] [blame] | 849 | int maxlvt; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 850 | u32 v; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 851 | |
Andi Kleen | d343289 | 2008-01-30 13:33:17 +0100 | [diff] [blame] | 852 | /* APIC hasn't been mapped yet */ |
| 853 | if (!apic_phys) |
| 854 | return; |
| 855 | |
| 856 | maxlvt = lapic_get_maxlvt(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 857 | /* |
Siddha, Suresh B | 704fc59 | 2006-06-26 13:59:53 +0200 | [diff] [blame] | 858 | * Masking an LVT entry can trigger a local APIC error |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 859 | * if the vector is zero. Mask LVTERR first to prevent this. |
| 860 | */ |
| 861 | if (maxlvt >= 3) { |
| 862 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 863 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 864 | } |
| 865 | /* |
| 866 | * Careful: we have to set masks only first to deassert |
| 867 | * any level-triggered sources. |
| 868 | */ |
| 869 | v = apic_read(APIC_LVTT); |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 870 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 871 | v = apic_read(APIC_LVT0); |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 872 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 873 | v = apic_read(APIC_LVT1); |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 874 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 875 | if (maxlvt >= 4) { |
| 876 | v = apic_read(APIC_LVTPC); |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 877 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 878 | } |
| 879 | |
Cyrill Gorcunov | 6764014 | 2008-08-16 23:21:50 +0400 | [diff] [blame] | 880 | /* lets not touch this if we didn't frob it */ |
| 881 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL) |
| 882 | if (maxlvt >= 5) { |
| 883 | v = apic_read(APIC_LVTTHMR); |
| 884 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); |
| 885 | } |
| 886 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 887 | /* |
| 888 | * Clean APIC state for other OSs: |
| 889 | */ |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 890 | apic_write(APIC_LVTT, APIC_LVT_MASKED); |
| 891 | apic_write(APIC_LVT0, APIC_LVT_MASKED); |
| 892 | apic_write(APIC_LVT1, APIC_LVT_MASKED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 893 | if (maxlvt >= 3) |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 894 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 895 | if (maxlvt >= 4) |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 896 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); |
Cyrill Gorcunov | 6764014 | 2008-08-16 23:21:50 +0400 | [diff] [blame] | 897 | |
| 898 | /* Integrated APIC (!82489DX) ? */ |
| 899 | if (lapic_is_integrated()) { |
| 900 | if (maxlvt > 3) |
| 901 | /* Clear ESR due to Pentium errata 3AP and 11AP */ |
| 902 | apic_write(APIC_ESR, 0); |
| 903 | apic_read(APIC_ESR); |
| 904 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 905 | } |
| 906 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 907 | /** |
| 908 | * disable_local_APIC - clear and disable the local APIC |
| 909 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 910 | void disable_local_APIC(void) |
| 911 | { |
| 912 | unsigned int value; |
| 913 | |
Jan Beulich | a08c474 | 2009-01-14 12:28:51 +0000 | [diff] [blame] | 914 | /* APIC hasn't been mapped yet */ |
| 915 | if (!apic_phys) |
| 916 | return; |
| 917 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 918 | clear_local_APIC(); |
| 919 | |
| 920 | /* |
| 921 | * Disable APIC (implies clearing of registers |
| 922 | * for 82489DX!). |
| 923 | */ |
| 924 | value = apic_read(APIC_SPIV); |
| 925 | value &= ~APIC_SPIV_APIC_ENABLED; |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 926 | apic_write(APIC_SPIV, value); |
Cyrill Gorcunov | 990b183 | 2008-08-18 20:45:51 +0400 | [diff] [blame] | 927 | |
| 928 | #ifdef CONFIG_X86_32 |
| 929 | /* |
| 930 | * When LAPIC was disabled by the BIOS and enabled by the kernel, |
| 931 | * restore the disabled state. |
| 932 | */ |
| 933 | if (enabled_via_apicbase) { |
| 934 | unsigned int l, h; |
| 935 | |
| 936 | rdmsr(MSR_IA32_APICBASE, l, h); |
| 937 | l &= ~MSR_IA32_APICBASE_ENABLE; |
| 938 | wrmsr(MSR_IA32_APICBASE, l, h); |
| 939 | } |
| 940 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 941 | } |
| 942 | |
Cyrill Gorcunov | fe4024d | 2008-08-18 20:45:52 +0400 | [diff] [blame] | 943 | /* |
| 944 | * If Linux enabled the LAPIC against the BIOS default disable it down before |
| 945 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and |
| 946 | * not power-off. Additionally clear all LVT entries before disable_local_APIC |
| 947 | * for the case where Linux didn't enable the LAPIC. |
| 948 | */ |
Hiroshi Shimamoto | 9b7711f | 2007-10-19 18:21:11 -0700 | [diff] [blame] | 949 | void lapic_shutdown(void) |
| 950 | { |
| 951 | unsigned long flags; |
| 952 | |
| 953 | if (!cpu_has_apic) |
| 954 | return; |
| 955 | |
| 956 | local_irq_save(flags); |
| 957 | |
Cyrill Gorcunov | fe4024d | 2008-08-18 20:45:52 +0400 | [diff] [blame] | 958 | #ifdef CONFIG_X86_32 |
| 959 | if (!enabled_via_apicbase) |
| 960 | clear_local_APIC(); |
| 961 | else |
| 962 | #endif |
| 963 | disable_local_APIC(); |
| 964 | |
Hiroshi Shimamoto | 9b7711f | 2007-10-19 18:21:11 -0700 | [diff] [blame] | 965 | |
| 966 | local_irq_restore(flags); |
| 967 | } |
| 968 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 969 | /* |
| 970 | * This is to verify that we're looking at a real local APIC. |
| 971 | * Check these against your board if the CPUs aren't getting |
| 972 | * started for no apparent reason. |
| 973 | */ |
| 974 | int __init verify_local_APIC(void) |
| 975 | { |
| 976 | unsigned int reg0, reg1; |
| 977 | |
| 978 | /* |
| 979 | * The version register is read-only in a real APIC. |
| 980 | */ |
| 981 | reg0 = apic_read(APIC_LVR); |
| 982 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); |
| 983 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); |
| 984 | reg1 = apic_read(APIC_LVR); |
| 985 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); |
| 986 | |
| 987 | /* |
| 988 | * The two version reads above should print the same |
| 989 | * numbers. If the second one is different, then we |
| 990 | * poke at a non-APIC. |
| 991 | */ |
| 992 | if (reg1 != reg0) |
| 993 | return 0; |
| 994 | |
| 995 | /* |
| 996 | * Check if the version looks reasonably. |
| 997 | */ |
| 998 | reg1 = GET_APIC_VERSION(reg0); |
| 999 | if (reg1 == 0x00 || reg1 == 0xff) |
| 1000 | return 0; |
Thomas Gleixner | 37e650c | 2008-01-30 13:30:14 +0100 | [diff] [blame] | 1001 | reg1 = lapic_get_maxlvt(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1002 | if (reg1 < 0x02 || reg1 == 0xff) |
| 1003 | return 0; |
| 1004 | |
| 1005 | /* |
| 1006 | * The ID register is read/write in a real APIC. |
| 1007 | */ |
Suresh Siddha | 2d7a66d | 2008-07-11 14:24:19 -0700 | [diff] [blame] | 1008 | reg0 = apic_read(APIC_ID); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1009 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
Ingo Molnar | 5b81272 | 2009-01-28 14:59:17 +0100 | [diff] [blame] | 1010 | apic_write(APIC_ID, reg0 ^ apic->apic_id_mask); |
Suresh Siddha | 2d7a66d | 2008-07-11 14:24:19 -0700 | [diff] [blame] | 1011 | reg1 = apic_read(APIC_ID); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1012 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); |
| 1013 | apic_write(APIC_ID, reg0); |
Ingo Molnar | 5b81272 | 2009-01-28 14:59:17 +0100 | [diff] [blame] | 1014 | if (reg1 != (reg0 ^ apic->apic_id_mask)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1015 | return 0; |
| 1016 | |
| 1017 | /* |
| 1018 | * The next two are just to see if we have sane values. |
| 1019 | * They're only really relevant if we're in Virtual Wire |
| 1020 | * compatibility mode, but most boxes are anymore. |
| 1021 | */ |
| 1022 | reg0 = apic_read(APIC_LVT0); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1023 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1024 | reg1 = apic_read(APIC_LVT1); |
| 1025 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); |
| 1026 | |
| 1027 | return 1; |
| 1028 | } |
| 1029 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1030 | /** |
| 1031 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs |
| 1032 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1033 | void __init sync_Arb_IDs(void) |
| 1034 | { |
Cyrill Gorcunov | 296cb95 | 2008-08-15 13:51:23 +0200 | [diff] [blame] | 1035 | /* |
| 1036 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not |
| 1037 | * needed on AMD. |
| 1038 | */ |
| 1039 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1040 | return; |
| 1041 | |
| 1042 | /* |
| 1043 | * Wait for idle. |
| 1044 | */ |
| 1045 | apic_wait_icr_idle(); |
| 1046 | |
| 1047 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); |
Cyrill Gorcunov | 6f6da97 | 2008-08-15 23:05:19 +0400 | [diff] [blame] | 1048 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
| 1049 | APIC_INT_LEVELTRIG | APIC_DM_INIT); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1050 | } |
| 1051 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1052 | /* |
| 1053 | * An initial setup of the virtual wire mode. |
| 1054 | */ |
| 1055 | void __init init_bsp_APIC(void) |
| 1056 | { |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1057 | unsigned int value; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1058 | |
| 1059 | /* |
| 1060 | * Don't do the setup now if we have a SMP BIOS as the |
| 1061 | * through-I/O-APIC virtual wire mode might be active. |
| 1062 | */ |
| 1063 | if (smp_found_config || !cpu_has_apic) |
| 1064 | return; |
| 1065 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1066 | /* |
| 1067 | * Do not trust the local APIC being empty at bootup. |
| 1068 | */ |
| 1069 | clear_local_APIC(); |
| 1070 | |
| 1071 | /* |
| 1072 | * Enable APIC. |
| 1073 | */ |
| 1074 | value = apic_read(APIC_SPIV); |
| 1075 | value &= ~APIC_VECTOR_MASK; |
| 1076 | value |= APIC_SPIV_APIC_ENABLED; |
Cyrill Gorcunov | 638c041 | 2008-08-15 23:05:18 +0400 | [diff] [blame] | 1077 | |
| 1078 | #ifdef CONFIG_X86_32 |
| 1079 | /* This bit is reserved on P4/Xeon and should be cleared */ |
| 1080 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && |
| 1081 | (boot_cpu_data.x86 == 15)) |
| 1082 | value &= ~APIC_SPIV_FOCUS_DISABLED; |
| 1083 | else |
| 1084 | #endif |
| 1085 | value |= APIC_SPIV_FOCUS_DISABLED; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1086 | value |= SPURIOUS_APIC_VECTOR; |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1087 | apic_write(APIC_SPIV, value); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1088 | |
| 1089 | /* |
| 1090 | * Set up the virtual wire mode. |
| 1091 | */ |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1092 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1093 | value = APIC_DM_NMI; |
Cyrill Gorcunov | 638c041 | 2008-08-15 23:05:18 +0400 | [diff] [blame] | 1094 | if (!lapic_is_integrated()) /* 82489DX */ |
| 1095 | value |= APIC_LVT_LEVEL_TRIGGER; |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1096 | apic_write(APIC_LVT1, value); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1097 | } |
| 1098 | |
Cyrill Gorcunov | c43da2f | 2008-08-18 20:45:54 +0400 | [diff] [blame] | 1099 | static void __cpuinit lapic_setup_esr(void) |
| 1100 | { |
Cyrill Gorcunov | 9df08f1 | 2008-09-14 11:55:37 +0400 | [diff] [blame] | 1101 | unsigned int oldvalue, value, maxlvt; |
Cyrill Gorcunov | c43da2f | 2008-08-18 20:45:54 +0400 | [diff] [blame] | 1102 | |
Cyrill Gorcunov | 9df08f1 | 2008-09-14 11:55:37 +0400 | [diff] [blame] | 1103 | if (!lapic_is_integrated()) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1104 | pr_info("No ESR for 82489DX.\n"); |
Cyrill Gorcunov | 9df08f1 | 2008-09-14 11:55:37 +0400 | [diff] [blame] | 1105 | return; |
Cyrill Gorcunov | c43da2f | 2008-08-18 20:45:54 +0400 | [diff] [blame] | 1106 | } |
Cyrill Gorcunov | 9df08f1 | 2008-09-14 11:55:37 +0400 | [diff] [blame] | 1107 | |
Ingo Molnar | 08125d3 | 2009-01-28 05:08:44 +0100 | [diff] [blame] | 1108 | if (apic->disable_esr) { |
Cyrill Gorcunov | 9df08f1 | 2008-09-14 11:55:37 +0400 | [diff] [blame] | 1109 | /* |
| 1110 | * Something untraceable is creating bad interrupts on |
| 1111 | * secondary quads ... for the moment, just leave the |
| 1112 | * ESR disabled - we can't do anything useful with the |
| 1113 | * errors anyway - mbligh |
| 1114 | */ |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1115 | pr_info("Leaving ESR disabled.\n"); |
Cyrill Gorcunov | 9df08f1 | 2008-09-14 11:55:37 +0400 | [diff] [blame] | 1116 | return; |
| 1117 | } |
| 1118 | |
| 1119 | maxlvt = lapic_get_maxlvt(); |
| 1120 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
| 1121 | apic_write(APIC_ESR, 0); |
| 1122 | oldvalue = apic_read(APIC_ESR); |
| 1123 | |
| 1124 | /* enables sending errors */ |
| 1125 | value = ERROR_APIC_VECTOR; |
| 1126 | apic_write(APIC_LVTERR, value); |
| 1127 | |
| 1128 | /* |
| 1129 | * spec says clear errors after enabling vector. |
| 1130 | */ |
| 1131 | if (maxlvt > 3) |
| 1132 | apic_write(APIC_ESR, 0); |
| 1133 | value = apic_read(APIC_ESR); |
| 1134 | if (value != oldvalue) |
| 1135 | apic_printk(APIC_VERBOSE, "ESR value before enabling " |
| 1136 | "vector: 0x%08x after: 0x%08x\n", |
| 1137 | oldvalue, value); |
Cyrill Gorcunov | c43da2f | 2008-08-18 20:45:54 +0400 | [diff] [blame] | 1138 | } |
| 1139 | |
| 1140 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1141 | /** |
| 1142 | * setup_local_APIC - setup the local APIC |
| 1143 | */ |
| 1144 | void __cpuinit setup_local_APIC(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1145 | { |
Andi Kleen | 739f33b | 2008-01-30 13:30:40 +0100 | [diff] [blame] | 1146 | unsigned int value; |
Vivek Goyal | da7ed9f | 2006-03-25 16:31:16 +0100 | [diff] [blame] | 1147 | int i, j; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1148 | |
Jan Beulich | f118263 | 2009-01-14 12:27:35 +0000 | [diff] [blame] | 1149 | if (disable_apic) { |
Ingo Molnar | 5cdc5e9e | 2009-01-19 20:49:37 +0100 | [diff] [blame] | 1150 | #ifdef CONFIG_X86_IO_APIC |
Jan Beulich | f118263 | 2009-01-14 12:27:35 +0000 | [diff] [blame] | 1151 | disable_ioapic_setup(); |
Ingo Molnar | 5cdc5e9e | 2009-01-19 20:49:37 +0100 | [diff] [blame] | 1152 | #endif |
Jan Beulich | f118263 | 2009-01-14 12:27:35 +0000 | [diff] [blame] | 1153 | return; |
| 1154 | } |
| 1155 | |
Cyrill Gorcunov | 89c38c2 | 2008-08-24 02:01:43 -0700 | [diff] [blame] | 1156 | #ifdef CONFIG_X86_32 |
| 1157 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ |
Ingo Molnar | 08125d3 | 2009-01-28 05:08:44 +0100 | [diff] [blame] | 1158 | if (lapic_is_integrated() && apic->disable_esr) { |
Cyrill Gorcunov | 89c38c2 | 2008-08-24 02:01:43 -0700 | [diff] [blame] | 1159 | apic_write(APIC_ESR, 0); |
| 1160 | apic_write(APIC_ESR, 0); |
| 1161 | apic_write(APIC_ESR, 0); |
| 1162 | apic_write(APIC_ESR, 0); |
| 1163 | } |
| 1164 | #endif |
| 1165 | |
Jack Steiner | ac23d4e | 2008-03-28 14:12:16 -0500 | [diff] [blame] | 1166 | preempt_disable(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1167 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1168 | /* |
| 1169 | * Double-check whether this APIC is really registered. |
| 1170 | * This is meaningless in clustered apic mode, so we skip it. |
| 1171 | */ |
Ingo Molnar | 7ed248d | 2009-01-28 03:43:47 +0100 | [diff] [blame] | 1172 | if (!apic->apic_id_registered()) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1173 | BUG(); |
| 1174 | |
| 1175 | /* |
| 1176 | * Intel recommends to set DFR, LDR and TPR before enabling |
| 1177 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel |
| 1178 | * document number 292116). So here it goes... |
| 1179 | */ |
Ingo Molnar | a5c4329 | 2009-01-28 06:50:47 +0100 | [diff] [blame] | 1180 | apic->init_apic_ldr(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1181 | |
| 1182 | /* |
| 1183 | * Set Task Priority to 'accept all'. We never change this |
| 1184 | * later on. |
| 1185 | */ |
| 1186 | value = apic_read(APIC_TASKPRI); |
| 1187 | value &= ~APIC_TPRI_MASK; |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1188 | apic_write(APIC_TASKPRI, value); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1189 | |
| 1190 | /* |
Vivek Goyal | da7ed9f | 2006-03-25 16:31:16 +0100 | [diff] [blame] | 1191 | * After a crash, we no longer service the interrupts and a pending |
| 1192 | * interrupt from previous kernel might still have ISR bit set. |
| 1193 | * |
| 1194 | * Most probably by now CPU has serviced that pending interrupt and |
| 1195 | * it might not have done the ack_APIC_irq() because it thought, |
| 1196 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it |
| 1197 | * does not clear the ISR bit and cpu thinks it has already serivced |
| 1198 | * the interrupt. Hence a vector might get locked. It was noticed |
| 1199 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. |
| 1200 | */ |
| 1201 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { |
| 1202 | value = apic_read(APIC_ISR + i*0x10); |
| 1203 | for (j = 31; j >= 0; j--) { |
| 1204 | if (value & (1<<j)) |
| 1205 | ack_APIC_irq(); |
| 1206 | } |
| 1207 | } |
| 1208 | |
| 1209 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1210 | * Now that we are all set up, enable the APIC |
| 1211 | */ |
| 1212 | value = apic_read(APIC_SPIV); |
| 1213 | value &= ~APIC_VECTOR_MASK; |
| 1214 | /* |
| 1215 | * Enable APIC |
| 1216 | */ |
| 1217 | value |= APIC_SPIV_APIC_ENABLED; |
| 1218 | |
Cyrill Gorcunov | 89c38c2 | 2008-08-24 02:01:43 -0700 | [diff] [blame] | 1219 | #ifdef CONFIG_X86_32 |
| 1220 | /* |
| 1221 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with |
| 1222 | * certain networking cards. If high frequency interrupts are |
| 1223 | * happening on a particular IOAPIC pin, plus the IOAPIC routing |
| 1224 | * entry is masked/unmasked at a high rate as well then sooner or |
| 1225 | * later IOAPIC line gets 'stuck', no more interrupts are received |
| 1226 | * from the device. If focus CPU is disabled then the hang goes |
| 1227 | * away, oh well :-( |
| 1228 | * |
| 1229 | * [ This bug can be reproduced easily with a level-triggered |
| 1230 | * PCI Ne2000 networking cards and PII/PIII processors, dual |
| 1231 | * BX chipset. ] |
| 1232 | */ |
| 1233 | /* |
| 1234 | * Actually disabling the focus CPU check just makes the hang less |
| 1235 | * frequent as it makes the interrupt distributon model be more |
| 1236 | * like LRU than MRU (the short-term load is more even across CPUs). |
| 1237 | * See also the comment in end_level_ioapic_irq(). --macro |
| 1238 | */ |
| 1239 | |
| 1240 | /* |
| 1241 | * - enable focus processor (bit==0) |
| 1242 | * - 64bit mode always use processor focus |
| 1243 | * so no need to set it |
| 1244 | */ |
| 1245 | value &= ~APIC_SPIV_FOCUS_DISABLED; |
| 1246 | #endif |
Andi Kleen | 3f14c74 | 2006-09-26 10:52:29 +0200 | [diff] [blame] | 1247 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1248 | /* |
| 1249 | * Set spurious IRQ vector |
| 1250 | */ |
| 1251 | value |= SPURIOUS_APIC_VECTOR; |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1252 | apic_write(APIC_SPIV, value); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1253 | |
| 1254 | /* |
| 1255 | * Set up LVT0, LVT1: |
| 1256 | * |
| 1257 | * set up through-local-APIC on the BP's LINT0. This is not |
| 1258 | * strictly necessary in pure symmetric-IO mode, but sometimes |
| 1259 | * we delegate interrupts to the 8259A. |
| 1260 | */ |
| 1261 | /* |
| 1262 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro |
| 1263 | */ |
| 1264 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; |
Cyrill Gorcunov | 89c38c2 | 2008-08-24 02:01:43 -0700 | [diff] [blame] | 1265 | if (!smp_processor_id() && (pic_mode || !value)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1266 | value = APIC_DM_EXTINT; |
Chris Wright | bc1d99c | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 1267 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", |
Cyrill Gorcunov | 89c38c2 | 2008-08-24 02:01:43 -0700 | [diff] [blame] | 1268 | smp_processor_id()); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1269 | } else { |
| 1270 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; |
Chris Wright | bc1d99c | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 1271 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
Cyrill Gorcunov | 89c38c2 | 2008-08-24 02:01:43 -0700 | [diff] [blame] | 1272 | smp_processor_id()); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1273 | } |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1274 | apic_write(APIC_LVT0, value); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1275 | |
| 1276 | /* |
| 1277 | * only the BP should see the LINT1 NMI signal, obviously. |
| 1278 | */ |
| 1279 | if (!smp_processor_id()) |
| 1280 | value = APIC_DM_NMI; |
| 1281 | else |
| 1282 | value = APIC_DM_NMI | APIC_LVT_MASKED; |
Cyrill Gorcunov | 89c38c2 | 2008-08-24 02:01:43 -0700 | [diff] [blame] | 1283 | if (!lapic_is_integrated()) /* 82489DX */ |
| 1284 | value |= APIC_LVT_LEVEL_TRIGGER; |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1285 | apic_write(APIC_LVT1, value); |
Cyrill Gorcunov | 89c38c2 | 2008-08-24 02:01:43 -0700 | [diff] [blame] | 1286 | |
Jack Steiner | ac23d4e | 2008-03-28 14:12:16 -0500 | [diff] [blame] | 1287 | preempt_enable(); |
Andi Kleen | 739f33b | 2008-01-30 13:30:40 +0100 | [diff] [blame] | 1288 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1289 | |
Andi Kleen | 739f33b | 2008-01-30 13:30:40 +0100 | [diff] [blame] | 1290 | void __cpuinit end_local_APIC_setup(void) |
| 1291 | { |
| 1292 | lapic_setup_esr(); |
Cyrill Gorcunov | fa6b95f | 2008-08-18 20:45:58 +0400 | [diff] [blame] | 1293 | |
| 1294 | #ifdef CONFIG_X86_32 |
Cyrill Gorcunov | 1b4ee4e | 2008-08-18 23:12:33 +0400 | [diff] [blame] | 1295 | { |
| 1296 | unsigned int value; |
| 1297 | /* Disable the local apic timer */ |
| 1298 | value = apic_read(APIC_LVTT); |
| 1299 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); |
| 1300 | apic_write(APIC_LVTT, value); |
| 1301 | } |
Cyrill Gorcunov | fa6b95f | 2008-08-18 20:45:58 +0400 | [diff] [blame] | 1302 | #endif |
| 1303 | |
Don Zickus | f2802e7 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 1304 | setup_apic_nmi_watchdog(NULL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1305 | apic_pm_activate(); |
| 1306 | } |
| 1307 | |
Yinghai Lu | 49899ea | 2008-08-24 02:01:47 -0700 | [diff] [blame] | 1308 | #ifdef HAVE_X2APIC |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1309 | void check_x2apic(void) |
| 1310 | { |
| 1311 | int msr, msr2; |
| 1312 | |
| 1313 | rdmsr(MSR_IA32_APICBASE, msr, msr2); |
| 1314 | |
| 1315 | if (msr & X2APIC_ENABLE) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1316 | pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1317 | x2apic_preenabled = x2apic = 1; |
| 1318 | apic_ops = &x2apic_ops; |
| 1319 | } |
| 1320 | } |
| 1321 | |
| 1322 | void enable_x2apic(void) |
| 1323 | { |
| 1324 | int msr, msr2; |
| 1325 | |
| 1326 | rdmsr(MSR_IA32_APICBASE, msr, msr2); |
| 1327 | if (!(msr & X2APIC_ENABLE)) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1328 | pr_info("Enabling x2apic\n"); |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1329 | wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); |
| 1330 | } |
| 1331 | } |
| 1332 | |
Al Viro | 2236d25 | 2008-11-22 17:37:34 +0000 | [diff] [blame] | 1333 | void __init enable_IR_x2apic(void) |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1334 | { |
| 1335 | #ifdef CONFIG_INTR_REMAP |
| 1336 | int ret; |
| 1337 | unsigned long flags; |
| 1338 | |
| 1339 | if (!cpu_has_x2apic) |
| 1340 | return; |
| 1341 | |
| 1342 | if (!x2apic_preenabled && disable_x2apic) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1343 | pr_info("Skipped enabling x2apic and Interrupt-remapping " |
| 1344 | "because of nox2apic\n"); |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1345 | return; |
| 1346 | } |
| 1347 | |
| 1348 | if (x2apic_preenabled && disable_x2apic) |
| 1349 | panic("Bios already enabled x2apic, can't enforce nox2apic"); |
| 1350 | |
| 1351 | if (!x2apic_preenabled && skip_ioapic_setup) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1352 | pr_info("Skipped enabling x2apic and Interrupt-remapping " |
| 1353 | "because of skipping io-apic setup\n"); |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1354 | return; |
| 1355 | } |
| 1356 | |
| 1357 | ret = dmar_table_init(); |
| 1358 | if (ret) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1359 | pr_info("dmar_table_init() failed with %d:\n", ret); |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1360 | |
| 1361 | if (x2apic_preenabled) |
| 1362 | panic("x2apic enabled by bios. But IR enabling failed"); |
| 1363 | else |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1364 | pr_info("Not enabling x2apic,Intr-remapping\n"); |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1365 | return; |
| 1366 | } |
| 1367 | |
| 1368 | local_irq_save(flags); |
| 1369 | mask_8259A(); |
Cyrill Gorcunov | 5ffa4eb | 2008-09-18 23:37:57 +0400 | [diff] [blame] | 1370 | |
| 1371 | ret = save_mask_IO_APIC_setup(); |
| 1372 | if (ret) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1373 | pr_info("Saving IO-APIC state failed: %d\n", ret); |
Cyrill Gorcunov | 5ffa4eb | 2008-09-18 23:37:57 +0400 | [diff] [blame] | 1374 | goto end; |
| 1375 | } |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1376 | |
| 1377 | ret = enable_intr_remapping(1); |
| 1378 | |
| 1379 | if (ret && x2apic_preenabled) { |
| 1380 | local_irq_restore(flags); |
| 1381 | panic("x2apic enabled by bios. But IR enabling failed"); |
| 1382 | } |
| 1383 | |
| 1384 | if (ret) |
Cyrill Gorcunov | 5ffa4eb | 2008-09-18 23:37:57 +0400 | [diff] [blame] | 1385 | goto end_restore; |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1386 | |
| 1387 | if (!x2apic) { |
| 1388 | x2apic = 1; |
| 1389 | apic_ops = &x2apic_ops; |
| 1390 | enable_x2apic(); |
| 1391 | } |
Cyrill Gorcunov | 5ffa4eb | 2008-09-18 23:37:57 +0400 | [diff] [blame] | 1392 | |
| 1393 | end_restore: |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1394 | if (ret) |
| 1395 | /* |
| 1396 | * IR enabling failed |
| 1397 | */ |
| 1398 | restore_IO_APIC_setup(); |
| 1399 | else |
| 1400 | reinit_intr_remapped_IO_APIC(x2apic_preenabled); |
| 1401 | |
Cyrill Gorcunov | 5ffa4eb | 2008-09-18 23:37:57 +0400 | [diff] [blame] | 1402 | end: |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1403 | unmask_8259A(); |
| 1404 | local_irq_restore(flags); |
| 1405 | |
| 1406 | if (!ret) { |
| 1407 | if (!x2apic_preenabled) |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1408 | pr_info("Enabled x2apic and interrupt-remapping\n"); |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1409 | else |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1410 | pr_info("Enabled Interrupt-remapping\n"); |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1411 | } else |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1412 | pr_err("Failed to enable Interrupt-remapping and x2apic\n"); |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1413 | #else |
| 1414 | if (!cpu_has_x2apic) |
| 1415 | return; |
| 1416 | |
| 1417 | if (x2apic_preenabled) |
| 1418 | panic("x2apic enabled prior OS handover," |
| 1419 | " enable CONFIG_INTR_REMAP"); |
| 1420 | |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1421 | pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping " |
| 1422 | " and x2apic\n"); |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1423 | #endif |
| 1424 | |
| 1425 | return; |
| 1426 | } |
Yinghai Lu | 49899ea | 2008-08-24 02:01:47 -0700 | [diff] [blame] | 1427 | #endif /* HAVE_X2APIC */ |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1428 | |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1429 | #ifdef CONFIG_X86_64 |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1430 | /* |
| 1431 | * Detect and enable local APICs on non-SMP boards. |
| 1432 | * Original code written by Keir Fraser. |
| 1433 | * On AMD64 we trust the BIOS - if it says no APIC it is likely |
| 1434 | * not correctly set up (usually the APIC timer won't work etc.) |
| 1435 | */ |
| 1436 | static int __init detect_init_APIC(void) |
| 1437 | { |
| 1438 | if (!cpu_has_apic) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1439 | pr_info("No local APIC present\n"); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1440 | return -1; |
| 1441 | } |
| 1442 | |
| 1443 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; |
Glauber de Oliveira Costa | c70dcb7 | 2008-03-19 14:25:58 -0300 | [diff] [blame] | 1444 | boot_cpu_physical_apicid = 0; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1445 | return 0; |
| 1446 | } |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1447 | #else |
| 1448 | /* |
| 1449 | * Detect and initialize APIC |
| 1450 | */ |
| 1451 | static int __init detect_init_APIC(void) |
| 1452 | { |
| 1453 | u32 h, l, features; |
| 1454 | |
| 1455 | /* Disabled by kernel option? */ |
| 1456 | if (disable_apic) |
| 1457 | return -1; |
| 1458 | |
| 1459 | switch (boot_cpu_data.x86_vendor) { |
| 1460 | case X86_VENDOR_AMD: |
| 1461 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || |
| 1462 | (boot_cpu_data.x86 == 15)) |
| 1463 | break; |
| 1464 | goto no_apic; |
| 1465 | case X86_VENDOR_INTEL: |
| 1466 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || |
| 1467 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) |
| 1468 | break; |
| 1469 | goto no_apic; |
| 1470 | default: |
| 1471 | goto no_apic; |
| 1472 | } |
| 1473 | |
| 1474 | if (!cpu_has_apic) { |
| 1475 | /* |
| 1476 | * Over-ride BIOS and try to enable the local APIC only if |
| 1477 | * "lapic" specified. |
| 1478 | */ |
| 1479 | if (!force_enable_local_apic) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1480 | pr_info("Local APIC disabled by BIOS -- " |
| 1481 | "you can enable it with \"lapic\"\n"); |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1482 | return -1; |
| 1483 | } |
| 1484 | /* |
| 1485 | * Some BIOSes disable the local APIC in the APIC_BASE |
| 1486 | * MSR. This can only be done in software for Intel P6 or later |
| 1487 | * and AMD K7 (Model > 1) or later. |
| 1488 | */ |
| 1489 | rdmsr(MSR_IA32_APICBASE, l, h); |
| 1490 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1491 | pr_info("Local APIC disabled by BIOS -- reenabling.\n"); |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1492 | l &= ~MSR_IA32_APICBASE_BASE; |
| 1493 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; |
| 1494 | wrmsr(MSR_IA32_APICBASE, l, h); |
| 1495 | enabled_via_apicbase = 1; |
| 1496 | } |
| 1497 | } |
| 1498 | /* |
| 1499 | * The APIC feature bit should now be enabled |
| 1500 | * in `cpuid' |
| 1501 | */ |
| 1502 | features = cpuid_edx(1); |
| 1503 | if (!(features & (1 << X86_FEATURE_APIC))) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1504 | pr_warning("Could not enable APIC!\n"); |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1505 | return -1; |
| 1506 | } |
| 1507 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
| 1508 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; |
| 1509 | |
| 1510 | /* The BIOS may have set up the APIC at some other address */ |
| 1511 | rdmsr(MSR_IA32_APICBASE, l, h); |
| 1512 | if (l & MSR_IA32_APICBASE_ENABLE) |
| 1513 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; |
| 1514 | |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1515 | pr_info("Found and enabled local APIC!\n"); |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1516 | |
| 1517 | apic_pm_activate(); |
| 1518 | |
| 1519 | return 0; |
| 1520 | |
| 1521 | no_apic: |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1522 | pr_info("No local APIC present or hardware disabled\n"); |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1523 | return -1; |
| 1524 | } |
| 1525 | #endif |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1526 | |
Yinghai Lu | f28c0ae | 2008-08-24 02:01:49 -0700 | [diff] [blame] | 1527 | #ifdef CONFIG_X86_64 |
Yinghai Lu | 8643f9d | 2008-02-19 03:21:06 -0800 | [diff] [blame] | 1528 | void __init early_init_lapic_mapping(void) |
| 1529 | { |
Thomas Gleixner | 431ee79 | 2008-05-12 15:43:35 +0200 | [diff] [blame] | 1530 | unsigned long phys_addr; |
Yinghai Lu | 8643f9d | 2008-02-19 03:21:06 -0800 | [diff] [blame] | 1531 | |
| 1532 | /* |
| 1533 | * If no local APIC can be found then go out |
| 1534 | * : it means there is no mpatable and MADT |
| 1535 | */ |
| 1536 | if (!smp_found_config) |
| 1537 | return; |
| 1538 | |
Thomas Gleixner | 431ee79 | 2008-05-12 15:43:35 +0200 | [diff] [blame] | 1539 | phys_addr = mp_lapic_addr; |
Yinghai Lu | 8643f9d | 2008-02-19 03:21:06 -0800 | [diff] [blame] | 1540 | |
Thomas Gleixner | 431ee79 | 2008-05-12 15:43:35 +0200 | [diff] [blame] | 1541 | set_fixmap_nocache(FIX_APIC_BASE, phys_addr); |
Yinghai Lu | 8643f9d | 2008-02-19 03:21:06 -0800 | [diff] [blame] | 1542 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
Thomas Gleixner | 431ee79 | 2008-05-12 15:43:35 +0200 | [diff] [blame] | 1543 | APIC_BASE, phys_addr); |
Yinghai Lu | 8643f9d | 2008-02-19 03:21:06 -0800 | [diff] [blame] | 1544 | |
| 1545 | /* |
| 1546 | * Fetch the APIC ID of the BSP in case we have a |
| 1547 | * default configuration (or the MP table is broken). |
| 1548 | */ |
Yinghai Lu | 4c9961d | 2008-07-11 18:44:16 -0700 | [diff] [blame] | 1549 | boot_cpu_physical_apicid = read_apic_id(); |
Yinghai Lu | 8643f9d | 2008-02-19 03:21:06 -0800 | [diff] [blame] | 1550 | } |
Yinghai Lu | f28c0ae | 2008-08-24 02:01:49 -0700 | [diff] [blame] | 1551 | #endif |
Yinghai Lu | 8643f9d | 2008-02-19 03:21:06 -0800 | [diff] [blame] | 1552 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1553 | /** |
| 1554 | * init_apic_mappings - initialize APIC mappings |
| 1555 | */ |
| 1556 | void __init init_apic_mappings(void) |
| 1557 | { |
Yinghai Lu | 49899ea | 2008-08-24 02:01:47 -0700 | [diff] [blame] | 1558 | #ifdef HAVE_X2APIC |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1559 | if (x2apic) { |
Yinghai Lu | 4c9961d | 2008-07-11 18:44:16 -0700 | [diff] [blame] | 1560 | boot_cpu_physical_apicid = read_apic_id(); |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1561 | return; |
| 1562 | } |
Yinghai Lu | 49899ea | 2008-08-24 02:01:47 -0700 | [diff] [blame] | 1563 | #endif |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1564 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1565 | /* |
| 1566 | * If no local APIC can be found then set up a fake all |
| 1567 | * zeroes page to simulate the local APIC and another |
| 1568 | * one for the IO-APIC. |
| 1569 | */ |
| 1570 | if (!smp_found_config && detect_init_APIC()) { |
| 1571 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); |
| 1572 | apic_phys = __pa(apic_phys); |
| 1573 | } else |
| 1574 | apic_phys = mp_lapic_addr; |
| 1575 | |
| 1576 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); |
Yinghai Lu | 79c0969 | 2008-09-07 17:58:57 -0700 | [diff] [blame] | 1577 | apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1578 | APIC_BASE, apic_phys); |
| 1579 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1580 | /* |
| 1581 | * Fetch the APIC ID of the BSP in case we have a |
| 1582 | * default configuration (or the MP table is broken). |
| 1583 | */ |
Yinghai Lu | f28c0ae | 2008-08-24 02:01:49 -0700 | [diff] [blame] | 1584 | if (boot_cpu_physical_apicid == -1U) |
| 1585 | boot_cpu_physical_apicid = read_apic_id(); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1586 | } |
| 1587 | |
| 1588 | /* |
| 1589 | * This initializes the IO-APIC and APIC hardware if this is |
| 1590 | * a UP kernel. |
| 1591 | */ |
Cyrill Gorcunov | 1b313f4 | 2008-08-18 20:45:57 +0400 | [diff] [blame] | 1592 | int apic_version[MAX_APICS]; |
| 1593 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1594 | int __init APIC_init_uniprocessor(void) |
| 1595 | { |
| 1596 | if (disable_apic) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1597 | pr_info("Apic disabled\n"); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1598 | return -1; |
| 1599 | } |
Jan Beulich | f118263 | 2009-01-14 12:27:35 +0000 | [diff] [blame] | 1600 | #ifdef CONFIG_X86_64 |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1601 | if (!cpu_has_apic) { |
| 1602 | disable_apic = 1; |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1603 | pr_info("Apic disabled by BIOS\n"); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1604 | return -1; |
| 1605 | } |
Yinghai Lu | fa2bd35 | 2008-08-24 02:01:50 -0700 | [diff] [blame] | 1606 | #else |
| 1607 | if (!smp_found_config && !cpu_has_apic) |
| 1608 | return -1; |
| 1609 | |
| 1610 | /* |
| 1611 | * Complain if the BIOS pretends there is one. |
| 1612 | */ |
| 1613 | if (!cpu_has_apic && |
| 1614 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1615 | pr_err("BIOS bug, local APIC 0x%x not detected!...\n", |
| 1616 | boot_cpu_physical_apicid); |
Yinghai Lu | fa2bd35 | 2008-08-24 02:01:50 -0700 | [diff] [blame] | 1617 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
| 1618 | return -1; |
| 1619 | } |
| 1620 | #endif |
| 1621 | |
Yinghai Lu | 49899ea | 2008-08-24 02:01:47 -0700 | [diff] [blame] | 1622 | #ifdef HAVE_X2APIC |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1623 | enable_IR_x2apic(); |
Yinghai Lu | 49899ea | 2008-08-24 02:01:47 -0700 | [diff] [blame] | 1624 | #endif |
Yinghai Lu | fa2bd35 | 2008-08-24 02:01:50 -0700 | [diff] [blame] | 1625 | #ifdef CONFIG_X86_64 |
Ingo Molnar | 72ce016 | 2009-01-28 06:50:47 +0100 | [diff] [blame] | 1626 | default_setup_apic_routing(); |
Yinghai Lu | fa2bd35 | 2008-08-24 02:01:50 -0700 | [diff] [blame] | 1627 | #endif |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1628 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1629 | verify_local_APIC(); |
Glauber Costa | b584176 | 2008-05-28 13:38:28 -0300 | [diff] [blame] | 1630 | connect_bsp_APIC(); |
| 1631 | |
Yinghai Lu | fa2bd35 | 2008-08-24 02:01:50 -0700 | [diff] [blame] | 1632 | #ifdef CONFIG_X86_64 |
Glauber de Oliveira Costa | c70dcb7 | 2008-03-19 14:25:58 -0300 | [diff] [blame] | 1633 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); |
Yinghai Lu | fa2bd35 | 2008-08-24 02:01:50 -0700 | [diff] [blame] | 1634 | #else |
| 1635 | /* |
| 1636 | * Hack: In case of kdump, after a crash, kernel might be booting |
| 1637 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid |
| 1638 | * might be zero if read from MP tables. Get it from LAPIC. |
| 1639 | */ |
| 1640 | # ifdef CONFIG_CRASH_DUMP |
| 1641 | boot_cpu_physical_apicid = read_apic_id(); |
| 1642 | # endif |
| 1643 | #endif |
| 1644 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1645 | setup_local_APIC(); |
| 1646 | |
Yinghai Lu | fa2bd35 | 2008-08-24 02:01:50 -0700 | [diff] [blame] | 1647 | #ifdef CONFIG_X86_64 |
Andi Kleen | 739f33b | 2008-01-30 13:30:40 +0100 | [diff] [blame] | 1648 | /* |
| 1649 | * Now enable IO-APICs, actually call clear_IO_APIC |
| 1650 | * We need clear_IO_APIC before enabling vector on BP |
| 1651 | */ |
| 1652 | if (!skip_ioapic_setup && nr_ioapics) |
| 1653 | enable_IO_APIC(); |
Yinghai Lu | fa2bd35 | 2008-08-24 02:01:50 -0700 | [diff] [blame] | 1654 | #endif |
Andi Kleen | 739f33b | 2008-01-30 13:30:40 +0100 | [diff] [blame] | 1655 | |
Yinghai Lu | fa2bd35 | 2008-08-24 02:01:50 -0700 | [diff] [blame] | 1656 | #ifdef CONFIG_X86_IO_APIC |
Maciej W. Rozycki | acae7d9 | 2008-06-06 03:27:49 +0100 | [diff] [blame] | 1657 | if (!smp_found_config || skip_ioapic_setup || !nr_ioapics) |
Yinghai Lu | fa2bd35 | 2008-08-24 02:01:50 -0700 | [diff] [blame] | 1658 | #endif |
Maciej W. Rozycki | acae7d9 | 2008-06-06 03:27:49 +0100 | [diff] [blame] | 1659 | localise_nmi_watchdog(); |
Andi Kleen | 739f33b | 2008-01-30 13:30:40 +0100 | [diff] [blame] | 1660 | end_local_APIC_setup(); |
| 1661 | |
Yinghai Lu | fa2bd35 | 2008-08-24 02:01:50 -0700 | [diff] [blame] | 1662 | #ifdef CONFIG_X86_IO_APIC |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1663 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
| 1664 | setup_IO_APIC(); |
Yinghai Lu | fa2bd35 | 2008-08-24 02:01:50 -0700 | [diff] [blame] | 1665 | # ifdef CONFIG_X86_64 |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1666 | else |
| 1667 | nr_ioapics = 0; |
Yinghai Lu | fa2bd35 | 2008-08-24 02:01:50 -0700 | [diff] [blame] | 1668 | # endif |
| 1669 | #endif |
| 1670 | |
| 1671 | #ifdef CONFIG_X86_64 |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1672 | setup_boot_APIC_clock(); |
| 1673 | check_nmi_watchdog(); |
Yinghai Lu | fa2bd35 | 2008-08-24 02:01:50 -0700 | [diff] [blame] | 1674 | #else |
| 1675 | setup_boot_clock(); |
| 1676 | #endif |
| 1677 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1678 | return 0; |
| 1679 | } |
| 1680 | |
| 1681 | /* |
| 1682 | * Local APIC interrupts |
| 1683 | */ |
| 1684 | |
| 1685 | /* |
| 1686 | * This interrupt should _never_ happen with our APIC/SMP architecture |
| 1687 | */ |
Yinghai Lu | dc1528d | 2008-08-24 02:01:53 -0700 | [diff] [blame] | 1688 | void smp_spurious_interrupt(struct pt_regs *regs) |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1689 | { |
Yinghai Lu | dc1528d | 2008-08-24 02:01:53 -0700 | [diff] [blame] | 1690 | u32 v; |
| 1691 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1692 | exit_idle(); |
| 1693 | irq_enter(); |
| 1694 | /* |
| 1695 | * Check if this really is a spurious interrupt and ACK it |
| 1696 | * if it is a vectored one. Just in case... |
| 1697 | * Spurious interrupts should not be ACKed. |
| 1698 | */ |
| 1699 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
| 1700 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) |
| 1701 | ack_APIC_irq(); |
| 1702 | |
Hiroshi Shimamoto | 915b0d0 | 2008-12-08 19:19:26 -0800 | [diff] [blame] | 1703 | inc_irq_stat(irq_spurious_count); |
| 1704 | |
Yinghai Lu | dc1528d | 2008-08-24 02:01:53 -0700 | [diff] [blame] | 1705 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1706 | pr_info("spurious APIC interrupt on CPU#%d, " |
| 1707 | "should never happen.\n", smp_processor_id()); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1708 | irq_exit(); |
| 1709 | } |
| 1710 | |
| 1711 | /* |
| 1712 | * This interrupt should never happen with our APIC/SMP architecture |
| 1713 | */ |
Yinghai Lu | dc1528d | 2008-08-24 02:01:53 -0700 | [diff] [blame] | 1714 | void smp_error_interrupt(struct pt_regs *regs) |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1715 | { |
Yinghai Lu | dc1528d | 2008-08-24 02:01:53 -0700 | [diff] [blame] | 1716 | u32 v, v1; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1717 | |
| 1718 | exit_idle(); |
| 1719 | irq_enter(); |
| 1720 | /* First tickle the hardware, only then report what went on. -- REW */ |
| 1721 | v = apic_read(APIC_ESR); |
| 1722 | apic_write(APIC_ESR, 0); |
| 1723 | v1 = apic_read(APIC_ESR); |
| 1724 | ack_APIC_irq(); |
| 1725 | atomic_inc(&irq_err_count); |
| 1726 | |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1727 | /* |
| 1728 | * Here is what the APIC error bits mean: |
| 1729 | * 0: Send CS error |
| 1730 | * 1: Receive CS error |
| 1731 | * 2: Send accept error |
| 1732 | * 3: Receive accept error |
| 1733 | * 4: Reserved |
| 1734 | * 5: Send illegal vector |
| 1735 | * 6: Received illegal vector |
| 1736 | * 7: Illegal register address |
| 1737 | */ |
| 1738 | pr_debug("APIC error on CPU%d: %02x(%02x)\n", |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1739 | smp_processor_id(), v , v1); |
| 1740 | irq_exit(); |
| 1741 | } |
| 1742 | |
Glauber Costa | b584176 | 2008-05-28 13:38:28 -0300 | [diff] [blame] | 1743 | /** |
Cyrill Gorcunov | 36c9d67 | 2008-08-18 20:45:53 +0400 | [diff] [blame] | 1744 | * connect_bsp_APIC - attach the APIC to the interrupt system |
| 1745 | */ |
Glauber Costa | b584176 | 2008-05-28 13:38:28 -0300 | [diff] [blame] | 1746 | void __init connect_bsp_APIC(void) |
| 1747 | { |
Cyrill Gorcunov | 36c9d67 | 2008-08-18 20:45:53 +0400 | [diff] [blame] | 1748 | #ifdef CONFIG_X86_32 |
| 1749 | if (pic_mode) { |
| 1750 | /* |
| 1751 | * Do not trust the local APIC being empty at bootup. |
| 1752 | */ |
| 1753 | clear_local_APIC(); |
| 1754 | /* |
| 1755 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's |
| 1756 | * local APIC to INT and NMI lines. |
| 1757 | */ |
| 1758 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " |
| 1759 | "enabling APIC mode.\n"); |
| 1760 | outb(0x70, 0x22); |
| 1761 | outb(0x01, 0x23); |
| 1762 | } |
| 1763 | #endif |
Ingo Molnar | 4904033 | 2009-01-28 12:43:18 +0100 | [diff] [blame] | 1764 | if (apic->enable_apic_mode) |
| 1765 | apic->enable_apic_mode(); |
Glauber Costa | b584176 | 2008-05-28 13:38:28 -0300 | [diff] [blame] | 1766 | } |
| 1767 | |
Cyrill Gorcunov | 274cfe5 | 2008-08-16 23:21:53 +0400 | [diff] [blame] | 1768 | /** |
| 1769 | * disconnect_bsp_APIC - detach the APIC from the interrupt system |
| 1770 | * @virt_wire_setup: indicates, whether virtual wire mode is selected |
| 1771 | * |
| 1772 | * Virtual wire mode is necessary to deliver legacy interrupts even when the |
| 1773 | * APIC is disabled. |
| 1774 | */ |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1775 | void disconnect_bsp_APIC(int virt_wire_setup) |
| 1776 | { |
Cyrill Gorcunov | 1b4ee4e | 2008-08-18 23:12:33 +0400 | [diff] [blame] | 1777 | unsigned int value; |
| 1778 | |
Cyrill Gorcunov | c177b0b | 2008-08-18 20:45:56 +0400 | [diff] [blame] | 1779 | #ifdef CONFIG_X86_32 |
| 1780 | if (pic_mode) { |
| 1781 | /* |
| 1782 | * Put the board back into PIC mode (has an effect only on |
| 1783 | * certain older boards). Note that APIC interrupts, including |
| 1784 | * IPIs, won't work beyond this point! The only exception are |
| 1785 | * INIT IPIs. |
| 1786 | */ |
| 1787 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " |
| 1788 | "entering PIC mode.\n"); |
| 1789 | outb(0x70, 0x22); |
| 1790 | outb(0x00, 0x23); |
| 1791 | return; |
| 1792 | } |
| 1793 | #endif |
| 1794 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1795 | /* Go back to Virtual Wire compatibility mode */ |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1796 | |
| 1797 | /* For the spurious interrupt use vector F, and enable it */ |
| 1798 | value = apic_read(APIC_SPIV); |
| 1799 | value &= ~APIC_VECTOR_MASK; |
| 1800 | value |= APIC_SPIV_APIC_ENABLED; |
| 1801 | value |= 0xf; |
| 1802 | apic_write(APIC_SPIV, value); |
| 1803 | |
| 1804 | if (!virt_wire_setup) { |
| 1805 | /* |
| 1806 | * For LVT0 make it edge triggered, active high, |
| 1807 | * external and enabled |
| 1808 | */ |
| 1809 | value = apic_read(APIC_LVT0); |
| 1810 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | |
| 1811 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | |
| 1812 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); |
| 1813 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; |
| 1814 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); |
| 1815 | apic_write(APIC_LVT0, value); |
| 1816 | } else { |
| 1817 | /* Disable LVT0 */ |
| 1818 | apic_write(APIC_LVT0, APIC_LVT_MASKED); |
| 1819 | } |
| 1820 | |
Cyrill Gorcunov | c177b0b | 2008-08-18 20:45:56 +0400 | [diff] [blame] | 1821 | /* |
| 1822 | * For LVT1 make it edge triggered, active high, |
| 1823 | * nmi and enabled |
| 1824 | */ |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1825 | value = apic_read(APIC_LVT1); |
| 1826 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | |
| 1827 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | |
| 1828 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); |
| 1829 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; |
| 1830 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); |
| 1831 | apic_write(APIC_LVT1, value); |
| 1832 | } |
| 1833 | |
Alexey Starikovskiy | be8a568 | 2008-03-27 23:56:19 +0300 | [diff] [blame] | 1834 | void __cpuinit generic_processor_info(int apicid, int version) |
| 1835 | { |
| 1836 | int cpu; |
Alexey Starikovskiy | be8a568 | 2008-03-27 23:56:19 +0300 | [diff] [blame] | 1837 | |
Cyrill Gorcunov | 1b313f4 | 2008-08-18 20:45:57 +0400 | [diff] [blame] | 1838 | /* |
| 1839 | * Validate version |
| 1840 | */ |
| 1841 | if (version == 0x0) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1842 | pr_warning("BIOS bug, APIC version is 0 for CPU#%d! " |
Mike Travis | 3b11ce7 | 2008-12-17 15:21:39 -0800 | [diff] [blame] | 1843 | "fixing up to 0x10. (tell your hw vendor)\n", |
| 1844 | version); |
Cyrill Gorcunov | 1b313f4 | 2008-08-18 20:45:57 +0400 | [diff] [blame] | 1845 | version = 0x10; |
| 1846 | } |
| 1847 | apic_version[apicid] = version; |
| 1848 | |
Mike Travis | 3b11ce7 | 2008-12-17 15:21:39 -0800 | [diff] [blame] | 1849 | if (num_processors >= nr_cpu_ids) { |
| 1850 | int max = nr_cpu_ids; |
| 1851 | int thiscpu = max + disabled_cpus; |
| 1852 | |
| 1853 | pr_warning( |
| 1854 | "ACPI: NR_CPUS/possible_cpus limit of %i reached." |
| 1855 | " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); |
| 1856 | |
| 1857 | disabled_cpus++; |
Alexey Starikovskiy | be8a568 | 2008-03-27 23:56:19 +0300 | [diff] [blame] | 1858 | return; |
| 1859 | } |
| 1860 | |
| 1861 | num_processors++; |
Mike Travis | 3b11ce7 | 2008-12-17 15:21:39 -0800 | [diff] [blame] | 1862 | cpu = cpumask_next_zero(-1, cpu_present_mask); |
Alexey Starikovskiy | be8a568 | 2008-03-27 23:56:19 +0300 | [diff] [blame] | 1863 | |
Mike Travis | cef30b3 | 2009-01-16 15:58:13 -0800 | [diff] [blame] | 1864 | if (version != apic_version[boot_cpu_physical_apicid]) |
| 1865 | WARN_ONCE(1, |
| 1866 | "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n", |
| 1867 | apic_version[boot_cpu_physical_apicid], cpu, version); |
| 1868 | |
Alexey Starikovskiy | be8a568 | 2008-03-27 23:56:19 +0300 | [diff] [blame] | 1869 | physid_set(apicid, phys_cpu_present_map); |
| 1870 | if (apicid == boot_cpu_physical_apicid) { |
| 1871 | /* |
| 1872 | * x86_bios_cpu_apicid is required to have processors listed |
| 1873 | * in same order as logical cpu numbers. Hence the first |
| 1874 | * entry is BSP, and so on. |
| 1875 | */ |
| 1876 | cpu = 0; |
| 1877 | } |
Yinghai Lu | e0da336 | 2008-06-08 18:29:22 -0700 | [diff] [blame] | 1878 | if (apicid > max_physical_apicid) |
| 1879 | max_physical_apicid = apicid; |
| 1880 | |
Cyrill Gorcunov | 1b313f4 | 2008-08-18 20:45:57 +0400 | [diff] [blame] | 1881 | #ifdef CONFIG_X86_32 |
| 1882 | /* |
| 1883 | * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y |
| 1884 | * but we need to work other dependencies like SMP_SUSPEND etc |
| 1885 | * before this can be done without some confusion. |
| 1886 | * if (CPU_HOTPLUG_ENABLED || num_processors > 8) |
| 1887 | * - Ashok Raj <ashok.raj@intel.com> |
| 1888 | */ |
| 1889 | if (max_physical_apicid >= 8) { |
| 1890 | switch (boot_cpu_data.x86_vendor) { |
| 1891 | case X86_VENDOR_INTEL: |
| 1892 | if (!APIC_XAPIC(version)) { |
| 1893 | def_to_bigsmp = 0; |
| 1894 | break; |
| 1895 | } |
| 1896 | /* If P4 and above fall through */ |
| 1897 | case X86_VENDOR_AMD: |
| 1898 | def_to_bigsmp = 1; |
| 1899 | } |
| 1900 | } |
| 1901 | #endif |
| 1902 | |
| 1903 | #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64) |
Tejun Heo | f10fcd4 | 2009-01-13 20:41:34 +0900 | [diff] [blame] | 1904 | early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; |
| 1905 | early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; |
Cyrill Gorcunov | 1b313f4 | 2008-08-18 20:45:57 +0400 | [diff] [blame] | 1906 | #endif |
Alexey Starikovskiy | be8a568 | 2008-03-27 23:56:19 +0300 | [diff] [blame] | 1907 | |
Mike Travis | 1de88cd | 2008-12-16 17:34:02 -0800 | [diff] [blame] | 1908 | set_cpu_possible(cpu, true); |
| 1909 | set_cpu_present(cpu, true); |
Alexey Starikovskiy | be8a568 | 2008-03-27 23:56:19 +0300 | [diff] [blame] | 1910 | } |
| 1911 | |
Suresh Siddha | 0c81c74 | 2008-07-10 11:16:48 -0700 | [diff] [blame] | 1912 | int hard_smp_processor_id(void) |
| 1913 | { |
| 1914 | return read_apic_id(); |
| 1915 | } |
Ingo Molnar | 1dcdd3d | 2009-01-28 17:55:37 +0100 | [diff] [blame^] | 1916 | |
| 1917 | void default_init_apic_ldr(void) |
| 1918 | { |
| 1919 | unsigned long val; |
| 1920 | |
| 1921 | apic_write(APIC_DFR, APIC_DFR_VALUE); |
| 1922 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; |
| 1923 | val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); |
| 1924 | apic_write(APIC_LDR, val); |
| 1925 | } |
| 1926 | |
| 1927 | #ifdef CONFIG_X86_32 |
| 1928 | int default_apicid_to_node(int logical_apicid) |
| 1929 | { |
| 1930 | #ifdef CONFIG_SMP |
| 1931 | return apicid_2_node[hard_smp_processor_id()]; |
| 1932 | #else |
| 1933 | return 0; |
| 1934 | #endif |
| 1935 | } |
Yinghai Lu | 3491998 | 2008-08-24 02:01:48 -0700 | [diff] [blame] | 1936 | #endif |
Suresh Siddha | 0c81c74 | 2008-07-10 11:16:48 -0700 | [diff] [blame] | 1937 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1938 | /* |
| 1939 | * Power management |
| 1940 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1941 | #ifdef CONFIG_PM |
| 1942 | |
| 1943 | static struct { |
Cyrill Gorcunov | 274cfe5 | 2008-08-16 23:21:53 +0400 | [diff] [blame] | 1944 | /* |
| 1945 | * 'active' is true if the local APIC was enabled by us and |
| 1946 | * not the BIOS; this signifies that we are also responsible |
| 1947 | * for disabling it before entering apm/acpi suspend |
| 1948 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1949 | int active; |
| 1950 | /* r/w apic fields */ |
| 1951 | unsigned int apic_id; |
| 1952 | unsigned int apic_taskpri; |
| 1953 | unsigned int apic_ldr; |
| 1954 | unsigned int apic_dfr; |
| 1955 | unsigned int apic_spiv; |
| 1956 | unsigned int apic_lvtt; |
| 1957 | unsigned int apic_lvtpc; |
| 1958 | unsigned int apic_lvt0; |
| 1959 | unsigned int apic_lvt1; |
| 1960 | unsigned int apic_lvterr; |
| 1961 | unsigned int apic_tmict; |
| 1962 | unsigned int apic_tdcr; |
| 1963 | unsigned int apic_thmr; |
| 1964 | } apic_pm_state; |
| 1965 | |
Pavel Machek | 0b9c33a | 2005-04-16 15:25:31 -0700 | [diff] [blame] | 1966 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1967 | { |
| 1968 | unsigned long flags; |
Karsten Wiese | f990fff | 2006-12-07 02:14:11 +0100 | [diff] [blame] | 1969 | int maxlvt; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1970 | |
| 1971 | if (!apic_pm_state.active) |
| 1972 | return 0; |
| 1973 | |
Thomas Gleixner | 37e650c | 2008-01-30 13:30:14 +0100 | [diff] [blame] | 1974 | maxlvt = lapic_get_maxlvt(); |
Karsten Wiese | f990fff | 2006-12-07 02:14:11 +0100 | [diff] [blame] | 1975 | |
Suresh Siddha | 2d7a66d | 2008-07-11 14:24:19 -0700 | [diff] [blame] | 1976 | apic_pm_state.apic_id = apic_read(APIC_ID); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1977 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
| 1978 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); |
| 1979 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); |
| 1980 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); |
| 1981 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); |
Karsten Wiese | f990fff | 2006-12-07 02:14:11 +0100 | [diff] [blame] | 1982 | if (maxlvt >= 4) |
| 1983 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1984 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); |
| 1985 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); |
| 1986 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); |
| 1987 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); |
| 1988 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); |
Cyrill Gorcunov | 24968cf | 2008-08-16 23:21:52 +0400 | [diff] [blame] | 1989 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
Karsten Wiese | f990fff | 2006-12-07 02:14:11 +0100 | [diff] [blame] | 1990 | if (maxlvt >= 5) |
| 1991 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); |
| 1992 | #endif |
Cyrill Gorcunov | 24968cf | 2008-08-16 23:21:52 +0400 | [diff] [blame] | 1993 | |
Fernando Luis Vázquez Cao | 2b94ab2 | 2006-09-26 10:52:33 +0200 | [diff] [blame] | 1994 | local_irq_save(flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1995 | disable_local_APIC(); |
| 1996 | local_irq_restore(flags); |
| 1997 | return 0; |
| 1998 | } |
| 1999 | |
| 2000 | static int lapic_resume(struct sys_device *dev) |
| 2001 | { |
| 2002 | unsigned int l, h; |
| 2003 | unsigned long flags; |
Karsten Wiese | f990fff | 2006-12-07 02:14:11 +0100 | [diff] [blame] | 2004 | int maxlvt; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2005 | |
| 2006 | if (!apic_pm_state.active) |
| 2007 | return 0; |
| 2008 | |
Thomas Gleixner | 37e650c | 2008-01-30 13:30:14 +0100 | [diff] [blame] | 2009 | maxlvt = lapic_get_maxlvt(); |
Karsten Wiese | f990fff | 2006-12-07 02:14:11 +0100 | [diff] [blame] | 2010 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2011 | local_irq_save(flags); |
Cyrill Gorcunov | 92206c9 | 2008-08-16 23:21:51 +0400 | [diff] [blame] | 2012 | |
Yinghai Lu | 49899ea | 2008-08-24 02:01:47 -0700 | [diff] [blame] | 2013 | #ifdef HAVE_X2APIC |
Cyrill Gorcunov | 92206c9 | 2008-08-16 23:21:51 +0400 | [diff] [blame] | 2014 | if (x2apic) |
| 2015 | enable_x2apic(); |
| 2016 | else |
| 2017 | #endif |
Yinghai Lu | d5e629a | 2008-08-17 21:12:27 -0700 | [diff] [blame] | 2018 | { |
Cyrill Gorcunov | 92206c9 | 2008-08-16 23:21:51 +0400 | [diff] [blame] | 2019 | /* |
| 2020 | * Make sure the APICBASE points to the right address |
| 2021 | * |
| 2022 | * FIXME! This will be wrong if we ever support suspend on |
| 2023 | * SMP! We'll need to do this as part of the CPU restore! |
| 2024 | */ |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 2025 | rdmsr(MSR_IA32_APICBASE, l, h); |
| 2026 | l &= ~MSR_IA32_APICBASE_BASE; |
| 2027 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; |
| 2028 | wrmsr(MSR_IA32_APICBASE, l, h); |
Yinghai Lu | d5e629a | 2008-08-17 21:12:27 -0700 | [diff] [blame] | 2029 | } |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 2030 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2031 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
| 2032 | apic_write(APIC_ID, apic_pm_state.apic_id); |
| 2033 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); |
| 2034 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); |
| 2035 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); |
| 2036 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); |
| 2037 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); |
| 2038 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); |
Cyrill Gorcunov | 92206c9 | 2008-08-16 23:21:51 +0400 | [diff] [blame] | 2039 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
Karsten Wiese | f990fff | 2006-12-07 02:14:11 +0100 | [diff] [blame] | 2040 | if (maxlvt >= 5) |
| 2041 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); |
| 2042 | #endif |
| 2043 | if (maxlvt >= 4) |
| 2044 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2045 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); |
| 2046 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); |
| 2047 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); |
| 2048 | apic_write(APIC_ESR, 0); |
| 2049 | apic_read(APIC_ESR); |
| 2050 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); |
| 2051 | apic_write(APIC_ESR, 0); |
| 2052 | apic_read(APIC_ESR); |
Cyrill Gorcunov | 92206c9 | 2008-08-16 23:21:51 +0400 | [diff] [blame] | 2053 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2054 | local_irq_restore(flags); |
Cyrill Gorcunov | 92206c9 | 2008-08-16 23:21:51 +0400 | [diff] [blame] | 2055 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2056 | return 0; |
| 2057 | } |
| 2058 | |
Cyrill Gorcunov | 274cfe5 | 2008-08-16 23:21:53 +0400 | [diff] [blame] | 2059 | /* |
| 2060 | * This device has no shutdown method - fully functioning local APICs |
| 2061 | * are needed on every CPU up until machine_halt/restart/poweroff. |
| 2062 | */ |
| 2063 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2064 | static struct sysdev_class lapic_sysclass = { |
Kay Sievers | af5ca3f | 2007-12-20 02:09:39 +0100 | [diff] [blame] | 2065 | .name = "lapic", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2066 | .resume = lapic_resume, |
| 2067 | .suspend = lapic_suspend, |
| 2068 | }; |
| 2069 | |
| 2070 | static struct sys_device device_lapic = { |
Hiroshi Shimamoto | e83a5fd | 2008-01-30 13:32:35 +0100 | [diff] [blame] | 2071 | .id = 0, |
| 2072 | .cls = &lapic_sysclass, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2073 | }; |
| 2074 | |
Ashok Raj | e6982c6 | 2005-06-25 14:54:58 -0700 | [diff] [blame] | 2075 | static void __cpuinit apic_pm_activate(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2076 | { |
| 2077 | apic_pm_state.active = 1; |
| 2078 | } |
| 2079 | |
| 2080 | static int __init init_lapic_sysfs(void) |
| 2081 | { |
| 2082 | int error; |
Hiroshi Shimamoto | e83a5fd | 2008-01-30 13:32:35 +0100 | [diff] [blame] | 2083 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2084 | if (!cpu_has_apic) |
| 2085 | return 0; |
| 2086 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ |
Hiroshi Shimamoto | e83a5fd | 2008-01-30 13:32:35 +0100 | [diff] [blame] | 2087 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2088 | error = sysdev_class_register(&lapic_sysclass); |
| 2089 | if (!error) |
| 2090 | error = sysdev_register(&device_lapic); |
| 2091 | return error; |
| 2092 | } |
| 2093 | device_initcall(init_lapic_sysfs); |
| 2094 | |
| 2095 | #else /* CONFIG_PM */ |
| 2096 | |
| 2097 | static void apic_pm_activate(void) { } |
| 2098 | |
| 2099 | #endif /* CONFIG_PM */ |
| 2100 | |
Yinghai Lu | f28c0ae | 2008-08-24 02:01:49 -0700 | [diff] [blame] | 2101 | #ifdef CONFIG_X86_64 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2102 | /* |
Vojtech Pavlik | f8bf3c6 | 2006-06-26 13:58:23 +0200 | [diff] [blame] | 2103 | * apic_is_clustered_box() -- Check if we can expect good TSC |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2104 | * |
| 2105 | * Thus far, the major user of this is IBM's Summit2 series: |
| 2106 | * |
Linus Torvalds | 637029c | 2006-02-27 20:41:56 -0800 | [diff] [blame] | 2107 | * Clustered boxes may have unsynced TSC problems if they are |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2108 | * multi-chassis. Use available data to take a good guess. |
| 2109 | * If in doubt, go HPET. |
| 2110 | */ |
Vojtech Pavlik | f8bf3c6 | 2006-06-26 13:58:23 +0200 | [diff] [blame] | 2111 | __cpuinit int apic_is_clustered_box(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2112 | { |
| 2113 | int i, clusters, zeros; |
| 2114 | unsigned id; |
Yinghai Lu | 322850a | 2008-02-23 21:48:42 -0800 | [diff] [blame] | 2115 | u16 *bios_cpu_apicid; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2116 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); |
| 2117 | |
Yinghai Lu | 322850a | 2008-02-23 21:48:42 -0800 | [diff] [blame] | 2118 | /* |
| 2119 | * there is not this kind of box with AMD CPU yet. |
| 2120 | * Some AMD box with quadcore cpu and 8 sockets apicid |
| 2121 | * will be [4, 0x23] or [8, 0x27] could be thought to |
Yinghai Lu | f8fffa4 | 2008-02-24 21:36:28 -0800 | [diff] [blame] | 2122 | * vsmp box still need checking... |
Yinghai Lu | 322850a | 2008-02-23 21:48:42 -0800 | [diff] [blame] | 2123 | */ |
Ravikiran G Thirumalai | 1cb6848 | 2008-03-20 00:45:08 -0700 | [diff] [blame] | 2124 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box()) |
Yinghai Lu | 322850a | 2008-02-23 21:48:42 -0800 | [diff] [blame] | 2125 | return 0; |
| 2126 | |
Mike Travis | 23ca4bb | 2008-05-12 21:21:12 +0200 | [diff] [blame] | 2127 | bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); |
Suresh Siddha | 376ec33 | 2005-05-16 21:53:32 -0700 | [diff] [blame] | 2128 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2129 | |
Mike Travis | 168ef54 | 2008-12-16 17:34:01 -0800 | [diff] [blame] | 2130 | for (i = 0; i < nr_cpu_ids; i++) { |
travis@sgi.com | e8c10ef | 2008-01-30 13:33:12 +0100 | [diff] [blame] | 2131 | /* are we being called early in kernel startup? */ |
Mike Travis | 693e3c5 | 2008-01-30 13:33:14 +0100 | [diff] [blame] | 2132 | if (bios_cpu_apicid) { |
| 2133 | id = bios_cpu_apicid[i]; |
Jaswinder Singh Rajput | e423e33 | 2009-01-04 16:16:25 +0530 | [diff] [blame] | 2134 | } else if (i < nr_cpu_ids) { |
travis@sgi.com | e8c10ef | 2008-01-30 13:33:12 +0100 | [diff] [blame] | 2135 | if (cpu_present(i)) |
| 2136 | id = per_cpu(x86_bios_cpu_apicid, i); |
| 2137 | else |
| 2138 | continue; |
Jaswinder Singh Rajput | e423e33 | 2009-01-04 16:16:25 +0530 | [diff] [blame] | 2139 | } else |
travis@sgi.com | e8c10ef | 2008-01-30 13:33:12 +0100 | [diff] [blame] | 2140 | break; |
| 2141 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2142 | if (id != BAD_APICID) |
| 2143 | __set_bit(APIC_CLUSTERID(id), clustermap); |
| 2144 | } |
| 2145 | |
| 2146 | /* Problem: Partially populated chassis may not have CPUs in some of |
| 2147 | * the APIC clusters they have been allocated. Only present CPUs have |
travis@sgi.com | 602a54a | 2008-01-30 13:33:21 +0100 | [diff] [blame] | 2148 | * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. |
| 2149 | * Since clusters are allocated sequentially, count zeros only if |
| 2150 | * they are bounded by ones. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2151 | */ |
| 2152 | clusters = 0; |
| 2153 | zeros = 0; |
| 2154 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { |
| 2155 | if (test_bit(i, clustermap)) { |
| 2156 | clusters += 1 + zeros; |
| 2157 | zeros = 0; |
| 2158 | } else |
| 2159 | ++zeros; |
| 2160 | } |
| 2161 | |
Ravikiran G Thirumalai | 1cb6848 | 2008-03-20 00:45:08 -0700 | [diff] [blame] | 2162 | /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are |
| 2163 | * not guaranteed to be synced between boards |
| 2164 | */ |
| 2165 | if (is_vsmp_box() && clusters > 1) |
| 2166 | return 1; |
| 2167 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2168 | /* |
Vojtech Pavlik | f8bf3c6 | 2006-06-26 13:58:23 +0200 | [diff] [blame] | 2169 | * If clusters > 2, then should be multi-chassis. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2170 | * May have to revisit this when multi-core + hyperthreaded CPUs come |
| 2171 | * out, but AFAIK this will work even for them. |
| 2172 | */ |
| 2173 | return (clusters > 2); |
| 2174 | } |
Yinghai Lu | f28c0ae | 2008-08-24 02:01:49 -0700 | [diff] [blame] | 2175 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2176 | |
| 2177 | /* |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 2178 | * APIC command line parameters |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2179 | */ |
Cyrill Gorcunov | 789fa73 | 2008-08-18 20:46:01 +0400 | [diff] [blame] | 2180 | static int __init setup_disableapic(char *arg) |
Thomas Gleixner | 6935d1f | 2007-07-21 17:10:17 +0200 | [diff] [blame] | 2181 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2182 | disable_apic = 1; |
Yinghai Lu | 9175fc0 | 2008-07-21 01:38:14 -0700 | [diff] [blame] | 2183 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
Andi Kleen | 2c8c0e6 | 2006-09-26 10:52:32 +0200 | [diff] [blame] | 2184 | return 0; |
| 2185 | } |
| 2186 | early_param("disableapic", setup_disableapic); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2187 | |
Andi Kleen | 2c8c0e6 | 2006-09-26 10:52:32 +0200 | [diff] [blame] | 2188 | /* same as disableapic, for compatibility */ |
Cyrill Gorcunov | 789fa73 | 2008-08-18 20:46:01 +0400 | [diff] [blame] | 2189 | static int __init setup_nolapic(char *arg) |
Thomas Gleixner | 6935d1f | 2007-07-21 17:10:17 +0200 | [diff] [blame] | 2190 | { |
Cyrill Gorcunov | 789fa73 | 2008-08-18 20:46:01 +0400 | [diff] [blame] | 2191 | return setup_disableapic(arg); |
Thomas Gleixner | 6935d1f | 2007-07-21 17:10:17 +0200 | [diff] [blame] | 2192 | } |
Andi Kleen | 2c8c0e6 | 2006-09-26 10:52:32 +0200 | [diff] [blame] | 2193 | early_param("nolapic", setup_nolapic); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2194 | |
Linus Torvalds | 2e7c283 | 2007-03-23 11:32:31 -0700 | [diff] [blame] | 2195 | static int __init parse_lapic_timer_c2_ok(char *arg) |
| 2196 | { |
| 2197 | local_apic_timer_c2_ok = 1; |
| 2198 | return 0; |
| 2199 | } |
| 2200 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); |
| 2201 | |
Cyrill Gorcunov | 36fef09 | 2008-08-15 13:51:20 +0200 | [diff] [blame] | 2202 | static int __init parse_disable_apic_timer(char *arg) |
Thomas Gleixner | 6935d1f | 2007-07-21 17:10:17 +0200 | [diff] [blame] | 2203 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2204 | disable_apic_timer = 1; |
Cyrill Gorcunov | 36fef09 | 2008-08-15 13:51:20 +0200 | [diff] [blame] | 2205 | return 0; |
Thomas Gleixner | 6935d1f | 2007-07-21 17:10:17 +0200 | [diff] [blame] | 2206 | } |
Cyrill Gorcunov | 36fef09 | 2008-08-15 13:51:20 +0200 | [diff] [blame] | 2207 | early_param("noapictimer", parse_disable_apic_timer); |
| 2208 | |
| 2209 | static int __init parse_nolapic_timer(char *arg) |
| 2210 | { |
| 2211 | disable_apic_timer = 1; |
| 2212 | return 0; |
| 2213 | } |
| 2214 | early_param("nolapic_timer", parse_nolapic_timer); |
Andi Kleen | 73dea47 | 2006-02-03 21:50:50 +0100 | [diff] [blame] | 2215 | |
Cyrill Gorcunov | 79af9be | 2008-08-18 20:46:00 +0400 | [diff] [blame] | 2216 | static int __init apic_set_verbosity(char *arg) |
| 2217 | { |
| 2218 | if (!arg) { |
| 2219 | #ifdef CONFIG_X86_64 |
| 2220 | skip_ioapic_setup = 0; |
Cyrill Gorcunov | 79af9be | 2008-08-18 20:46:00 +0400 | [diff] [blame] | 2221 | return 0; |
| 2222 | #endif |
| 2223 | return -EINVAL; |
| 2224 | } |
| 2225 | |
| 2226 | if (strcmp("debug", arg) == 0) |
| 2227 | apic_verbosity = APIC_DEBUG; |
| 2228 | else if (strcmp("verbose", arg) == 0) |
| 2229 | apic_verbosity = APIC_VERBOSE; |
| 2230 | else { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 2231 | pr_warning("APIC Verbosity level %s not recognised" |
Cyrill Gorcunov | 79af9be | 2008-08-18 20:46:00 +0400 | [diff] [blame] | 2232 | " use apic=verbose or apic=debug\n", arg); |
| 2233 | return -EINVAL; |
| 2234 | } |
| 2235 | |
| 2236 | return 0; |
| 2237 | } |
| 2238 | early_param("apic", apic_set_verbosity); |
| 2239 | |
Yinghai Lu | 1e934dd | 2008-02-22 13:37:26 -0800 | [diff] [blame] | 2240 | static int __init lapic_insert_resource(void) |
| 2241 | { |
| 2242 | if (!apic_phys) |
| 2243 | return -1; |
| 2244 | |
| 2245 | /* Put local APIC into the resource map. */ |
| 2246 | lapic_resource.start = apic_phys; |
| 2247 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; |
| 2248 | insert_resource(&iomem_resource, &lapic_resource); |
| 2249 | |
| 2250 | return 0; |
| 2251 | } |
| 2252 | |
| 2253 | /* |
| 2254 | * need call insert after e820_reserve_resources() |
| 2255 | * that is using request_resource |
| 2256 | */ |
| 2257 | late_initcall(lapic_insert_resource); |