blob: 41a0ba34d6b2009cccc8beb169d350cd64955542 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Local APIC handling, local APIC timers
3 *
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
5 *
6 * Fixes
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
9 * and Rolf G. Tews
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
13 * Pavel Machek and
14 * Mikael Pettersson : PM converted to driver model.
15 */
16
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#include <linux/init.h>
18
19#include <linux/mm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070020#include <linux/delay.h>
21#include <linux/bootmem.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070022#include <linux/interrupt.h>
23#include <linux/mc146818rtc.h>
24#include <linux/kernel_stat.h>
25#include <linux/sysdev.h>
Aaron Durbin39928722006-12-07 02:14:01 +010026#include <linux/ioport.h>
Yinghai Lu773763d2008-08-24 02:01:52 -070027#include <linux/cpu.h>
Thomas Gleixnerba7eda42007-10-12 23:04:07 +020028#include <linux/clockchips.h>
Thomas Gleixner70a20022008-01-30 13:30:18 +010029#include <linux/acpi_pmtmr.h>
Hiroshi Shimamotoe83a5fd2008-01-30 13:32:35 +010030#include <linux/module.h>
Yinghai Lu773763d2008-08-24 02:01:52 -070031#include <linux/dmi.h>
Suresh Siddha6e1cb382008-07-10 11:16:58 -070032#include <linux/dmar.h>
Frederic Weisbeckerbcbc4f22008-12-09 23:54:20 +010033#include <linux/ftrace.h>
Jaswinder Singh Rajpute423e332009-01-04 16:16:25 +053034#include <linux/smp.h>
35#include <linux/nmi.h>
36#include <linux/timex.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070037
38#include <asm/atomic.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070039#include <asm/mtrr.h>
40#include <asm/mpspec.h>
Yinghai Luefa25592008-08-19 20:50:36 -070041#include <asm/desc.h>
Yinghai Lu773763d2008-08-24 02:01:52 -070042#include <asm/arch_hooks.h>
Hiroshi Shimamotoe83a5fd2008-01-30 13:32:35 +010043#include <asm/hpet.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070044#include <asm/pgalloc.h>
Yinghai Lu773763d2008-08-24 02:01:52 -070045#include <asm/i8253.h>
Andi Kleen95833c82006-01-11 22:44:36 +010046#include <asm/idle.h>
Andi Kleen73dea472006-02-03 21:50:50 +010047#include <asm/proto.h>
Andi Kleen2c8c0e62006-09-26 10:52:32 +020048#include <asm/apic.h>
Suresh Siddha6e1cb382008-07-10 11:16:58 -070049#include <asm/i8259.h>
Jaswinder Singh Rajput2bc13792009-01-11 20:34:47 +053050#include <asm/smp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070051
Yinghai Lu773763d2008-08-24 02:01:52 -070052#include <mach_ipi.h>
Glauber Costa5af55732008-03-25 13:28:56 -030053
Cyrill Gorcunov80e56092008-08-24 02:01:42 -070054/*
55 * Sanity check
56 */
57#if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
58# error SPURIOUS_APIC_VECTOR definition error
59#endif
60
Brian Gerstec70de82009-01-27 12:56:47 +090061unsigned int num_processors;
62unsigned disabled_cpus __cpuinitdata;
63/* Processor that is doing the boot up */
64unsigned int boot_cpu_physical_apicid = -1U;
65EXPORT_SYMBOL(boot_cpu_physical_apicid);
66unsigned int max_physical_apicid;
67
68/* Bitmask of physically existing CPUs */
69physid_mask_t phys_cpu_present_map;
70
71/*
72 * Map cpu index to physical APIC ID
73 */
74DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID);
75DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID);
76EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
77EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
78
Yinghai Lub3c51172008-08-24 02:01:46 -070079#ifdef CONFIG_X86_32
80/*
81 * Knob to control our willingness to enable the local APIC.
82 *
83 * +1=force-enable
84 */
85static int force_enable_local_apic;
86/*
87 * APIC command line parameters
88 */
89static int __init parse_lapic(char *arg)
90{
91 force_enable_local_apic = 1;
92 return 0;
93}
94early_param("lapic", parse_lapic);
Yinghai Luf28c0ae2008-08-24 02:01:49 -070095/* Local APIC was disabled by the BIOS and enabled by the kernel */
96static int enabled_via_apicbase;
97
Yinghai Lub3c51172008-08-24 02:01:46 -070098#endif
99
100#ifdef CONFIG_X86_64
Chris Wrightbc1d99c2007-10-12 23:04:23 +0200101static int apic_calibrate_pmtmr __initdata;
Yinghai Lub3c51172008-08-24 02:01:46 -0700102static __init int setup_apicpmtimer(char *s)
103{
104 apic_calibrate_pmtmr = 1;
105 notsc_setup(NULL);
106 return 0;
107}
108__setup("apicpmtimer", setup_apicpmtimer);
109#endif
110
Yinghai Lu49899ea2008-08-24 02:01:47 -0700111#ifdef CONFIG_X86_64
112#define HAVE_X2APIC
113#endif
114
115#ifdef HAVE_X2APIC
Suresh Siddha89027d32008-07-10 11:16:56 -0700116int x2apic;
Suresh Siddha6e1cb382008-07-10 11:16:58 -0700117/* x2apic enabled before OS handover */
Jaswinder Singhb6b301a2008-12-23 21:52:33 +0530118static int x2apic_preenabled;
119static int disable_x2apic;
Yinghai Lu49899ea2008-08-24 02:01:47 -0700120static __init int setup_nox2apic(char *str)
121{
122 disable_x2apic = 1;
123 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
124 return 0;
125}
126early_param("nox2apic", setup_nox2apic);
127#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700128
Yinghai Lub3c51172008-08-24 02:01:46 -0700129unsigned long mp_lapic_addr;
130int disable_apic;
131/* Disable local APIC timer from the kernel commandline or via dmi quirk */
132static int disable_apic_timer __cpuinitdata;
Hiroshi Shimamotoe83a5fd2008-01-30 13:32:35 +0100133/* Local APIC timer works in C2 */
Linus Torvalds2e7c2832007-03-23 11:32:31 -0700134int local_apic_timer_c2_ok;
135EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
136
Yinghai Luefa25592008-08-19 20:50:36 -0700137int first_system_vector = 0xfe;
138
Hiroshi Shimamotoe83a5fd2008-01-30 13:32:35 +0100139/*
140 * Debug level, exported for io_apic.c
141 */
Maciej W. Rozyckibaa13182008-07-14 18:44:51 +0100142unsigned int apic_verbosity;
Hiroshi Shimamotoe83a5fd2008-01-30 13:32:35 +0100143
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -0700144int pic_mode;
145
Alexey Starikovskiybab4b272008-05-19 19:47:03 +0400146/* Have we found an MP table */
147int smp_found_config;
148
Aaron Durbin39928722006-12-07 02:14:01 +0100149static struct resource lapic_resource = {
150 .name = "Local APIC",
151 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
152};
153
Thomas Gleixnerd03030e2007-10-12 23:04:06 +0200154static unsigned int calibration_result;
155
Thomas Gleixnerba7eda42007-10-12 23:04:07 +0200156static int lapic_next_event(unsigned long delta,
157 struct clock_event_device *evt);
158static void lapic_timer_setup(enum clock_event_mode mode,
159 struct clock_event_device *evt);
Mike Travis96289372008-12-31 18:08:46 -0800160static void lapic_timer_broadcast(const struct cpumask *mask);
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100161static void apic_pm_activate(void);
Thomas Gleixnerba7eda42007-10-12 23:04:07 +0200162
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +0400163/*
164 * The local apic timer can be used for any function which is CPU local.
165 */
Thomas Gleixnerba7eda42007-10-12 23:04:07 +0200166static struct clock_event_device lapic_clockevent = {
167 .name = "lapic",
168 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
169 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
170 .shift = 32,
171 .set_mode = lapic_timer_setup,
172 .set_next_event = lapic_next_event,
173 .broadcast = lapic_timer_broadcast,
174 .rating = 100,
175 .irq = -1,
176};
177static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
178
Andi Kleend3432892008-01-30 13:33:17 +0100179static unsigned long apic_phys;
180
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100181/*
182 * Get the LAPIC version
183 */
184static inline int lapic_get_version(void)
185{
186 return GET_APIC_VERSION(apic_read(APIC_LVR));
187}
188
189/*
Cyrill Gorcunov9c803862008-08-16 23:21:54 +0400190 * Check, if the APIC is integrated or a separate chip
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100191 */
192static inline int lapic_is_integrated(void)
193{
Cyrill Gorcunov9c803862008-08-16 23:21:54 +0400194#ifdef CONFIG_X86_64
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100195 return 1;
Cyrill Gorcunov9c803862008-08-16 23:21:54 +0400196#else
197 return APIC_INTEGRATED(lapic_get_version());
198#endif
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100199}
200
201/*
202 * Check, whether this is a modern or a first generation APIC
203 */
204static int modern_apic(void)
205{
206 /* AMD systems use old APIC versions, so check the CPU */
207 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
208 boot_cpu_data.x86 >= 0xf)
209 return 1;
210 return lapic_get_version() >= 0x14;
211}
212
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +0400213/*
214 * Paravirt kernels also might be using these below ops. So we still
215 * use generic apic_read()/apic_write(), which might be pointing to different
216 * ops in PARAVIRT case.
217 */
Suresh Siddha1b374e42008-07-10 11:16:49 -0700218void xapic_wait_icr_idle(void)
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100219{
220 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
221 cpu_relax();
222}
223
Suresh Siddha1b374e42008-07-10 11:16:49 -0700224u32 safe_xapic_wait_icr_idle(void)
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100225{
226 u32 send_status;
227 int timeout;
228
229 timeout = 0;
230 do {
231 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
232 if (!send_status)
233 break;
234 udelay(100);
235 } while (timeout++ < 1000);
236
237 return send_status;
238}
239
Suresh Siddha1b374e42008-07-10 11:16:49 -0700240void xapic_icr_write(u32 low, u32 id)
241{
Cyrill Gorcunoved4e5ec2008-08-15 13:51:20 +0200242 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
Suresh Siddha1b374e42008-07-10 11:16:49 -0700243 apic_write(APIC_ICR, low);
244}
245
Jaswinder Singh Rajputec8c8422008-12-30 22:46:36 +0530246static u64 xapic_icr_read(void)
Suresh Siddha1b374e42008-07-10 11:16:49 -0700247{
248 u32 icr1, icr2;
249
250 icr2 = apic_read(APIC_ICR2);
251 icr1 = apic_read(APIC_ICR);
252
Cyrill Gorcunovcf9768d72008-08-16 23:21:55 +0400253 return icr1 | ((u64)icr2 << 32);
Suresh Siddha1b374e42008-07-10 11:16:49 -0700254}
255
256static struct apic_ops xapic_ops = {
257 .read = native_apic_mem_read,
258 .write = native_apic_mem_write,
Suresh Siddha1b374e42008-07-10 11:16:49 -0700259 .icr_read = xapic_icr_read,
260 .icr_write = xapic_icr_write,
261 .wait_icr_idle = xapic_wait_icr_idle,
262 .safe_wait_icr_idle = safe_xapic_wait_icr_idle,
263};
264
265struct apic_ops __read_mostly *apic_ops = &xapic_ops;
Suresh Siddha1b374e42008-07-10 11:16:49 -0700266EXPORT_SYMBOL_GPL(apic_ops);
267
Yinghai Lu49899ea2008-08-24 02:01:47 -0700268#ifdef HAVE_X2APIC
Suresh Siddha13c88fb52008-07-10 11:16:52 -0700269static void x2apic_wait_icr_idle(void)
270{
271 /* no need to wait for icr idle in x2apic */
272 return;
273}
274
275static u32 safe_x2apic_wait_icr_idle(void)
276{
277 /* no need to wait for icr idle in x2apic */
278 return 0;
279}
280
281void x2apic_icr_write(u32 low, u32 id)
282{
283 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
284}
285
Jaswinder Singh Rajputec8c8422008-12-30 22:46:36 +0530286static u64 x2apic_icr_read(void)
Suresh Siddha13c88fb52008-07-10 11:16:52 -0700287{
288 unsigned long val;
289
290 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
291 return val;
292}
293
294static struct apic_ops x2apic_ops = {
295 .read = native_apic_msr_read,
296 .write = native_apic_msr_write,
Suresh Siddha13c88fb52008-07-10 11:16:52 -0700297 .icr_read = x2apic_icr_read,
298 .icr_write = x2apic_icr_write,
299 .wait_icr_idle = x2apic_wait_icr_idle,
300 .safe_wait_icr_idle = safe_x2apic_wait_icr_idle,
301};
Yinghai Lu49899ea2008-08-24 02:01:47 -0700302#endif
Suresh Siddha13c88fb52008-07-10 11:16:52 -0700303
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100304/**
305 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
306 */
Jan Beuliche9427102008-01-30 13:31:24 +0100307void __cpuinit enable_NMI_through_LVT0(void)
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100308{
309 unsigned int v;
310
311 /* unmask and set to NMI */
312 v = APIC_DM_NMI;
Cyrill Gorcunovd4c63ec2008-07-24 13:52:29 +0200313
314 /* Level triggered for 82489DX (32bit mode) */
315 if (!lapic_is_integrated())
316 v |= APIC_LVT_LEVEL_TRIGGER;
317
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100318 apic_write(APIC_LVT0, v);
319}
320
Cyrill Gorcunov7c37e482008-08-24 02:01:40 -0700321#ifdef CONFIG_X86_32
322/**
323 * get_physical_broadcast - Get number of physical broadcast IDs
324 */
325int get_physical_broadcast(void)
326{
327 return modern_apic() ? 0xff : 0xf;
328}
329#endif
330
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100331/**
332 * lapic_get_maxlvt - get the maximum number of local vector table entries
333 */
334int lapic_get_maxlvt(void)
335{
Cyrill Gorcunov36a028d2008-07-24 13:52:28 +0200336 unsigned int v;
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100337
338 v = apic_read(APIC_LVR);
Cyrill Gorcunov36a028d2008-07-24 13:52:28 +0200339 /*
340 * - we always have APIC integrated on 64bit mode
341 * - 82489DXs do not report # of LVT entries
342 */
343 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100344}
345
346/*
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +0400347 * Local APIC timer
348 */
349
Cyrill Gorcunovc40aaec2008-08-18 20:45:55 +0400350/* Clock divisor */
Cyrill Gorcunovc40aaec2008-08-18 20:45:55 +0400351#define APIC_DIVISOR 16
Cyrill Gorcunovf07f4f92008-08-15 13:51:21 +0200352
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100353/*
354 * This function sets up the local APIC timer, with a timeout of
355 * 'clocks' APIC bus clock. During calibration we actually call
356 * this function twice on the boot CPU, once with a bogus timeout
357 * value, second time for real. The other (noncalibrating) CPUs
358 * call this function only once, with the real, calibrated value.
359 *
360 * We do reads before writes even if unnecessary, to get around the
361 * P5 APIC double write bug.
362 */
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100363static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
364{
365 unsigned int lvtt_value, tmp_value;
366
367 lvtt_value = LOCAL_TIMER_VECTOR;
368 if (!oneshot)
369 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
Cyrill Gorcunovf07f4f92008-08-15 13:51:21 +0200370 if (!lapic_is_integrated())
371 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
372
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100373 if (!irqen)
374 lvtt_value |= APIC_LVT_MASKED;
375
376 apic_write(APIC_LVTT, lvtt_value);
377
378 /*
379 * Divide PICLK by 16
380 */
381 tmp_value = apic_read(APIC_TDCR);
Cyrill Gorcunovc40aaec2008-08-18 20:45:55 +0400382 apic_write(APIC_TDCR,
383 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
384 APIC_TDR_DIV_16);
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100385
386 if (!oneshot)
Cyrill Gorcunovf07f4f92008-08-15 13:51:21 +0200387 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100388}
389
390/*
Robert Richter7b83dae2008-01-30 13:30:40 +0100391 * Setup extended LVT, AMD specific (K8, family 10h)
392 *
393 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
394 * MCE interrupts are supported. Thus MCE offset must be set to 0.
Robert Richter286f5712008-07-22 21:08:46 +0200395 *
396 * If mask=1, the LVT entry does not generate interrupts while mask=0
397 * enables the vector. See also the BKDGs.
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100398 */
Robert Richter7b83dae2008-01-30 13:30:40 +0100399
400#define APIC_EILVT_LVTOFF_MCE 0
401#define APIC_EILVT_LVTOFF_IBS 1
402
403static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100404{
Robert Richter7b83dae2008-01-30 13:30:40 +0100405 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100406 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
407
408 apic_write(reg, v);
409}
410
Robert Richter7b83dae2008-01-30 13:30:40 +0100411u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
412{
413 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
414 return APIC_EILVT_LVTOFF_MCE;
415}
416
417u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
418{
419 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
420 return APIC_EILVT_LVTOFF_IBS;
421}
Robert Richter6aa360e2008-07-23 15:28:14 +0200422EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);
Robert Richter7b83dae2008-01-30 13:30:40 +0100423
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100424/*
425 * Program the next event, relative to now
426 */
Thomas Gleixnerba7eda42007-10-12 23:04:07 +0200427static int lapic_next_event(unsigned long delta,
428 struct clock_event_device *evt)
429{
430 apic_write(APIC_TMICT, delta);
431 return 0;
432}
433
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100434/*
435 * Setup the lapic timer in periodic or oneshot mode
436 */
Thomas Gleixnerba7eda42007-10-12 23:04:07 +0200437static void lapic_timer_setup(enum clock_event_mode mode,
438 struct clock_event_device *evt)
439{
440 unsigned long flags;
441 unsigned int v;
442
443 /* Lapic used as dummy for broadcast ? */
444 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
445 return;
446
447 local_irq_save(flags);
448
449 switch (mode) {
450 case CLOCK_EVT_MODE_PERIODIC:
451 case CLOCK_EVT_MODE_ONESHOT:
452 __setup_APIC_LVTT(calibration_result,
453 mode != CLOCK_EVT_MODE_PERIODIC, 1);
454 break;
455 case CLOCK_EVT_MODE_UNUSED:
456 case CLOCK_EVT_MODE_SHUTDOWN:
457 v = apic_read(APIC_LVTT);
458 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
459 apic_write(APIC_LVTT, v);
Thomas Gleixnera98f8fd2008-11-06 01:13:39 +0100460 apic_write(APIC_TMICT, 0xffffffff);
Thomas Gleixnerba7eda42007-10-12 23:04:07 +0200461 break;
462 case CLOCK_EVT_MODE_RESUME:
463 /* Nothing to do here */
464 break;
465 }
466
467 local_irq_restore(flags);
468}
469
470/*
471 * Local APIC timer broadcast function
472 */
Mike Travis96289372008-12-31 18:08:46 -0800473static void lapic_timer_broadcast(const struct cpumask *mask)
Thomas Gleixnerba7eda42007-10-12 23:04:07 +0200474{
475#ifdef CONFIG_SMP
Ingo Molnardac5f412009-01-28 15:42:24 +0100476 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
Thomas Gleixnerba7eda42007-10-12 23:04:07 +0200477#endif
478}
479
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100480/*
481 * Setup the local APIC timer for this CPU. Copy the initilized values
482 * of the boot CPU and register the clock event in the framework.
483 */
Cyrill Gorcunovdb4b5522008-08-24 02:01:39 -0700484static void __cpuinit setup_APIC_timer(void)
Fernando Luis VazquezCao8339e9f2007-05-02 19:27:17 +0200485{
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100486 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
487
488 memcpy(levt, &lapic_clockevent, sizeof(*levt));
Rusty Russell320ab2b2008-12-13 21:20:26 +1030489 levt->cpumask = cpumask_of(smp_processor_id());
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100490
491 clockevents_register_device(levt);
Fernando Luis VazquezCao8339e9f2007-05-02 19:27:17 +0200492}
493
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700494/*
495 * In this functions we calibrate APIC bus clocks to the external timer.
496 *
497 * We want to do the calibration only once since we want to have local timer
498 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
499 * frequency.
500 *
501 * This was previously done by reading the PIT/HPET and waiting for a wrap
502 * around to find out, that a tick has elapsed. I have a box, where the PIT
503 * readout is broken, so it never gets out of the wait loop again. This was
504 * also reported by others.
505 *
506 * Monitoring the jiffies value is inaccurate and the clockevents
507 * infrastructure allows us to do a simple substitution of the interrupt
508 * handler.
509 *
510 * The calibration routine also uses the pm_timer when possible, as the PIT
511 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
512 * back to normal later in the boot process).
513 */
514
515#define LAPIC_CAL_LOOPS (HZ/10)
516
517static __initdata int lapic_cal_loops = -1;
518static __initdata long lapic_cal_t1, lapic_cal_t2;
519static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
520static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
521static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
522
523/*
524 * Temporary interrupt handler.
525 */
526static void __init lapic_cal_handler(struct clock_event_device *dev)
527{
528 unsigned long long tsc = 0;
529 long tapic = apic_read(APIC_TMCCT);
530 unsigned long pm = acpi_pm_read_early();
531
532 if (cpu_has_tsc)
533 rdtscll(tsc);
534
535 switch (lapic_cal_loops++) {
536 case 0:
537 lapic_cal_t1 = tapic;
538 lapic_cal_tsc1 = tsc;
539 lapic_cal_pm1 = pm;
540 lapic_cal_j1 = jiffies;
541 break;
542
543 case LAPIC_CAL_LOOPS:
544 lapic_cal_t2 = tapic;
545 lapic_cal_tsc2 = tsc;
546 if (pm < lapic_cal_pm1)
547 pm += ACPI_PM_OVRRUN;
548 lapic_cal_pm2 = pm;
549 lapic_cal_j2 = jiffies;
550 break;
551 }
552}
553
Cyrill Gorcunovb1898922008-09-12 23:58:24 +0400554static int __init calibrate_by_pmtimer(long deltapm, long *delta)
555{
556 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
557 const long pm_thresh = pm_100ms / 100;
558 unsigned long mult;
559 u64 res;
560
561#ifndef CONFIG_X86_PM_TIMER
562 return -1;
563#endif
564
565 apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm);
566
567 /* Check, if the PM timer is available */
568 if (!deltapm)
569 return -1;
570
571 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
572
573 if (deltapm > (pm_100ms - pm_thresh) &&
574 deltapm < (pm_100ms + pm_thresh)) {
575 apic_printk(APIC_VERBOSE, "... PM timer result ok\n");
576 } else {
577 res = (((u64)deltapm) * mult) >> 22;
578 do_div(res, 1000000);
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +0100579 pr_warning("APIC calibration not consistent "
Cyrill Gorcunovb1898922008-09-12 23:58:24 +0400580 "with PM Timer: %ldms instead of 100ms\n",
581 (long)res);
582 /* Correct the lapic counter value */
583 res = (((u64)(*delta)) * pm_100ms);
584 do_div(res, deltapm);
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +0100585 pr_info("APIC delta adjusted to PM-Timer: "
Cyrill Gorcunovb1898922008-09-12 23:58:24 +0400586 "%lu (%ld)\n", (unsigned long)res, *delta);
587 *delta = (long)res;
588 }
589
590 return 0;
591}
592
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700593static int __init calibrate_APIC_clock(void)
594{
595 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700596 void (*real_handler)(struct clock_event_device *dev);
597 unsigned long deltaj;
Cyrill Gorcunovb1898922008-09-12 23:58:24 +0400598 long delta;
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700599 int pm_referenced = 0;
600
601 local_irq_disable();
602
603 /* Replace the global interrupt handler */
604 real_handler = global_clock_event->event_handler;
605 global_clock_event->event_handler = lapic_cal_handler;
606
607 /*
Cyrill Gorcunov81608f32008-10-10 19:00:17 +0400608 * Setup the APIC counter to maximum. There is no way the lapic
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700609 * can underflow in the 100ms detection time frame
610 */
Cyrill Gorcunov81608f32008-10-10 19:00:17 +0400611 __setup_APIC_LVTT(0xffffffff, 0, 0);
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700612
613 /* Let the interrupts run */
614 local_irq_enable();
615
616 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
617 cpu_relax();
618
619 local_irq_disable();
620
621 /* Restore the real event handler */
622 global_clock_event->event_handler = real_handler;
623
624 /* Build delta t1-t2 as apic timer counts down */
625 delta = lapic_cal_t1 - lapic_cal_t2;
626 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
627
Cyrill Gorcunovb1898922008-09-12 23:58:24 +0400628 /* we trust the PM based calibration if possible */
629 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
630 &delta);
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700631
632 /* Calculate the scaled math multiplication factor */
633 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
634 lapic_clockevent.shift);
635 lapic_clockevent.max_delta_ns =
636 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
637 lapic_clockevent.min_delta_ns =
638 clockevent_delta2ns(0xF, &lapic_clockevent);
639
640 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
641
642 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
643 apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult);
644 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
645 calibration_result);
646
647 if (cpu_has_tsc) {
648 delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
649 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
650 "%ld.%04ld MHz.\n",
651 (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ),
652 (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ));
653 }
654
655 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
656 "%u.%04u MHz.\n",
657 calibration_result / (1000000 / HZ),
658 calibration_result % (1000000 / HZ));
659
660 /*
661 * Do a sanity check on the APIC calibration result
662 */
663 if (calibration_result < (1000000 / HZ)) {
664 local_irq_enable();
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +0100665 pr_warning("APIC frequency too slow, disabling apic timer\n");
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700666 return -1;
667 }
668
669 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
670
Cyrill Gorcunovb1898922008-09-12 23:58:24 +0400671 /*
672 * PM timer calibration failed or not turned on
673 * so lets try APIC timer based calibration
674 */
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700675 if (!pm_referenced) {
676 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
677
678 /*
679 * Setup the apic timer manually
680 */
681 levt->event_handler = lapic_cal_handler;
682 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
683 lapic_cal_loops = -1;
684
685 /* Let the interrupts run */
686 local_irq_enable();
687
688 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
689 cpu_relax();
690
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700691 /* Stop the lapic timer */
692 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
693
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700694 /* Jiffies delta */
695 deltaj = lapic_cal_j2 - lapic_cal_j1;
696 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
697
698 /* Check, if the jiffies result is consistent */
699 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
700 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
701 else
702 levt->features |= CLOCK_EVT_FEAT_DUMMY;
703 } else
704 local_irq_enable();
705
706 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
Jaswinder Singh Rajpute423e332009-01-04 16:16:25 +0530707 pr_warning("APIC timer disabled due to verification failure\n");
Yinghai Lu2f04fa82008-08-24 02:01:54 -0700708 return -1;
709 }
710
711 return 0;
712}
713
Hiroshi Shimamotoe83a5fd2008-01-30 13:32:35 +0100714/*
715 * Setup the boot APIC
716 *
717 * Calibrate and verify the result.
718 */
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100719void __init setup_boot_APIC_clock(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700720{
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100721 /*
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +0400722 * The local apic timer can be disabled via the kernel
723 * commandline or from the CPU detection code. Register the lapic
724 * timer as a dummy clock event source on SMP systems, so the
725 * broadcast mechanism is used. On UP systems simply ignore it.
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100726 */
727 if (disable_apic_timer) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +0100728 pr_info("Disabling APIC timer\n");
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100729 /* No broadcast on UP ! */
Thomas Gleixner9d099512008-01-30 13:33:04 +0100730 if (num_possible_cpus() > 1) {
731 lapic_clockevent.mult = 1;
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100732 setup_APIC_timer();
Thomas Gleixner9d099512008-01-30 13:33:04 +0100733 }
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100734 return;
735 }
Thomas Gleixner6935d1f2007-07-21 17:10:17 +0200736
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +0400737 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
738 "calibrating APIC timer ...\n");
739
Cyrill Gorcunov89b3b1f2008-07-15 21:02:54 +0400740 if (calibrate_APIC_clock()) {
Thomas Gleixnerc2b84b32008-01-30 13:33:04 +0100741 /* No broadcast on UP ! */
742 if (num_possible_cpus() > 1)
743 setup_APIC_timer();
744 return;
745 }
746
747 /*
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100748 * If nmi_watchdog is set to IO_APIC, we need the
749 * PIT/HPET going. Otherwise register lapic as a dummy
750 * device.
751 */
752 if (nmi_watchdog != NMI_IO_APIC)
753 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
754 else
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +0100755 pr_warning("APIC timer registered as dummy,"
Cyrill Gorcunov116f5702008-06-24 22:52:04 +0200756 " due to nmi_watchdog=%d!\n", nmi_watchdog);
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100757
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +0400758 /* Setup the lapic or request the broadcast */
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100759 setup_APIC_timer();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700760}
761
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100762void __cpuinit setup_secondary_APIC_clock(void)
763{
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100764 setup_APIC_timer();
765}
766
767/*
768 * The guts of the apic timer interrupt
769 */
770static void local_apic_timer_interrupt(void)
771{
772 int cpu = smp_processor_id();
773 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
774
775 /*
776 * Normally we should not be here till LAPIC has been initialized but
777 * in some cases like kdump, its possible that there is a pending LAPIC
778 * timer interrupt from previous kernel's context and is delivered in
779 * new kernel the moment interrupts are enabled.
780 *
781 * Interrupts are enabled early and LAPIC is setup much later, hence
782 * its possible that when we get here evt->event_handler is NULL.
783 * Check for event_handler being NULL and discard the interrupt as
784 * spurious.
785 */
786 if (!evt->event_handler) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +0100787 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100788 /* Switch it off */
789 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
790 return;
791 }
792
793 /*
794 * the NMI deadlock-detector uses this.
795 */
Hiroshi Shimamoto915b0d02008-12-08 19:19:26 -0800796 inc_irq_stat(apic_timer_irqs);
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100797
798 evt->event_handler(evt);
799}
800
801/*
802 * Local APIC timer interrupt. This is the most natural way for doing
803 * local interrupts, but local timer interrupts can be emulated by
804 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
805 *
806 * [ if a single-CPU system runs an SMP kernel then we call the local
807 * interrupt as well. Thus we cannot inline the local irq ... ]
808 */
Frederic Weisbeckerbcbc4f22008-12-09 23:54:20 +0100809void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100810{
811 struct pt_regs *old_regs = set_irq_regs(regs);
812
813 /*
814 * NOTE! We'd better ACK the irq immediately,
815 * because timer handling can be slow.
816 */
817 ack_APIC_irq();
818 /*
819 * update_process_times() expects us to have done irq_enter().
820 * Besides, if we don't timer interrupts ignore the global
821 * interrupt lock, which is the WrongThing (tm) to do.
822 */
823 exit_idle();
824 irq_enter();
825 local_apic_timer_interrupt();
826 irq_exit();
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +0400827
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100828 set_irq_regs(old_regs);
829}
830
831int setup_profiling_timer(unsigned int multiplier)
832{
833 return -EINVAL;
834}
835
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100836/*
837 * Local APIC start and shutdown
838 */
839
840/**
841 * clear_local_APIC - shutdown the local APIC
842 *
843 * This is called, when a CPU is disabled and before rebooting, so the state of
844 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
845 * leftovers during boot.
846 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700847void clear_local_APIC(void)
848{
Chuck Ebbert2584a822008-05-20 18:18:12 -0400849 int maxlvt;
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100850 u32 v;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700851
Andi Kleend3432892008-01-30 13:33:17 +0100852 /* APIC hasn't been mapped yet */
853 if (!apic_phys)
854 return;
855
856 maxlvt = lapic_get_maxlvt();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700857 /*
Siddha, Suresh B704fc592006-06-26 13:59:53 +0200858 * Masking an LVT entry can trigger a local APIC error
Linus Torvalds1da177e2005-04-16 15:20:36 -0700859 * if the vector is zero. Mask LVTERR first to prevent this.
860 */
861 if (maxlvt >= 3) {
862 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
Andi Kleen11a8e772006-01-11 22:46:51 +0100863 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700864 }
865 /*
866 * Careful: we have to set masks only first to deassert
867 * any level-triggered sources.
868 */
869 v = apic_read(APIC_LVTT);
Andi Kleen11a8e772006-01-11 22:46:51 +0100870 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700871 v = apic_read(APIC_LVT0);
Andi Kleen11a8e772006-01-11 22:46:51 +0100872 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700873 v = apic_read(APIC_LVT1);
Andi Kleen11a8e772006-01-11 22:46:51 +0100874 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700875 if (maxlvt >= 4) {
876 v = apic_read(APIC_LVTPC);
Andi Kleen11a8e772006-01-11 22:46:51 +0100877 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700878 }
879
Cyrill Gorcunov67640142008-08-16 23:21:50 +0400880 /* lets not touch this if we didn't frob it */
881#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
882 if (maxlvt >= 5) {
883 v = apic_read(APIC_LVTTHMR);
884 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
885 }
886#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700887 /*
888 * Clean APIC state for other OSs:
889 */
Andi Kleen11a8e772006-01-11 22:46:51 +0100890 apic_write(APIC_LVTT, APIC_LVT_MASKED);
891 apic_write(APIC_LVT0, APIC_LVT_MASKED);
892 apic_write(APIC_LVT1, APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700893 if (maxlvt >= 3)
Andi Kleen11a8e772006-01-11 22:46:51 +0100894 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700895 if (maxlvt >= 4)
Andi Kleen11a8e772006-01-11 22:46:51 +0100896 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
Cyrill Gorcunov67640142008-08-16 23:21:50 +0400897
898 /* Integrated APIC (!82489DX) ? */
899 if (lapic_is_integrated()) {
900 if (maxlvt > 3)
901 /* Clear ESR due to Pentium errata 3AP and 11AP */
902 apic_write(APIC_ESR, 0);
903 apic_read(APIC_ESR);
904 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700905}
906
Thomas Gleixner0e078e22008-01-30 13:30:20 +0100907/**
908 * disable_local_APIC - clear and disable the local APIC
909 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700910void disable_local_APIC(void)
911{
912 unsigned int value;
913
Jan Beulicha08c4742009-01-14 12:28:51 +0000914 /* APIC hasn't been mapped yet */
915 if (!apic_phys)
916 return;
917
Linus Torvalds1da177e2005-04-16 15:20:36 -0700918 clear_local_APIC();
919
920 /*
921 * Disable APIC (implies clearing of registers
922 * for 82489DX!).
923 */
924 value = apic_read(APIC_SPIV);
925 value &= ~APIC_SPIV_APIC_ENABLED;
Andi Kleen11a8e772006-01-11 22:46:51 +0100926 apic_write(APIC_SPIV, value);
Cyrill Gorcunov990b1832008-08-18 20:45:51 +0400927
928#ifdef CONFIG_X86_32
929 /*
930 * When LAPIC was disabled by the BIOS and enabled by the kernel,
931 * restore the disabled state.
932 */
933 if (enabled_via_apicbase) {
934 unsigned int l, h;
935
936 rdmsr(MSR_IA32_APICBASE, l, h);
937 l &= ~MSR_IA32_APICBASE_ENABLE;
938 wrmsr(MSR_IA32_APICBASE, l, h);
939 }
940#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700941}
942
Cyrill Gorcunovfe4024d2008-08-18 20:45:52 +0400943/*
944 * If Linux enabled the LAPIC against the BIOS default disable it down before
945 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
946 * not power-off. Additionally clear all LVT entries before disable_local_APIC
947 * for the case where Linux didn't enable the LAPIC.
948 */
Hiroshi Shimamoto9b7711f2007-10-19 18:21:11 -0700949void lapic_shutdown(void)
950{
951 unsigned long flags;
952
953 if (!cpu_has_apic)
954 return;
955
956 local_irq_save(flags);
957
Cyrill Gorcunovfe4024d2008-08-18 20:45:52 +0400958#ifdef CONFIG_X86_32
959 if (!enabled_via_apicbase)
960 clear_local_APIC();
961 else
962#endif
963 disable_local_APIC();
964
Hiroshi Shimamoto9b7711f2007-10-19 18:21:11 -0700965
966 local_irq_restore(flags);
967}
968
Linus Torvalds1da177e2005-04-16 15:20:36 -0700969/*
970 * This is to verify that we're looking at a real local APIC.
971 * Check these against your board if the CPUs aren't getting
972 * started for no apparent reason.
973 */
974int __init verify_local_APIC(void)
975{
976 unsigned int reg0, reg1;
977
978 /*
979 * The version register is read-only in a real APIC.
980 */
981 reg0 = apic_read(APIC_LVR);
982 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
983 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
984 reg1 = apic_read(APIC_LVR);
985 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
986
987 /*
988 * The two version reads above should print the same
989 * numbers. If the second one is different, then we
990 * poke at a non-APIC.
991 */
992 if (reg1 != reg0)
993 return 0;
994
995 /*
996 * Check if the version looks reasonably.
997 */
998 reg1 = GET_APIC_VERSION(reg0);
999 if (reg1 == 0x00 || reg1 == 0xff)
1000 return 0;
Thomas Gleixner37e650c2008-01-30 13:30:14 +01001001 reg1 = lapic_get_maxlvt();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001002 if (reg1 < 0x02 || reg1 == 0xff)
1003 return 0;
1004
1005 /*
1006 * The ID register is read/write in a real APIC.
1007 */
Suresh Siddha2d7a66d2008-07-11 14:24:19 -07001008 reg0 = apic_read(APIC_ID);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001009 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
Ingo Molnar5b812722009-01-28 14:59:17 +01001010 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask);
Suresh Siddha2d7a66d2008-07-11 14:24:19 -07001011 reg1 = apic_read(APIC_ID);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001012 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
1013 apic_write(APIC_ID, reg0);
Ingo Molnar5b812722009-01-28 14:59:17 +01001014 if (reg1 != (reg0 ^ apic->apic_id_mask))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001015 return 0;
1016
1017 /*
1018 * The next two are just to see if we have sane values.
1019 * They're only really relevant if we're in Virtual Wire
1020 * compatibility mode, but most boxes are anymore.
1021 */
1022 reg0 = apic_read(APIC_LVT0);
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001023 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001024 reg1 = apic_read(APIC_LVT1);
1025 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
1026
1027 return 1;
1028}
1029
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001030/**
1031 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1032 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001033void __init sync_Arb_IDs(void)
1034{
Cyrill Gorcunov296cb952008-08-15 13:51:23 +02001035 /*
1036 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1037 * needed on AMD.
1038 */
1039 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001040 return;
1041
1042 /*
1043 * Wait for idle.
1044 */
1045 apic_wait_icr_idle();
1046
1047 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
Cyrill Gorcunov6f6da972008-08-15 23:05:19 +04001048 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1049 APIC_INT_LEVELTRIG | APIC_DM_INIT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001050}
1051
Linus Torvalds1da177e2005-04-16 15:20:36 -07001052/*
1053 * An initial setup of the virtual wire mode.
1054 */
1055void __init init_bsp_APIC(void)
1056{
Andi Kleen11a8e772006-01-11 22:46:51 +01001057 unsigned int value;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001058
1059 /*
1060 * Don't do the setup now if we have a SMP BIOS as the
1061 * through-I/O-APIC virtual wire mode might be active.
1062 */
1063 if (smp_found_config || !cpu_has_apic)
1064 return;
1065
Linus Torvalds1da177e2005-04-16 15:20:36 -07001066 /*
1067 * Do not trust the local APIC being empty at bootup.
1068 */
1069 clear_local_APIC();
1070
1071 /*
1072 * Enable APIC.
1073 */
1074 value = apic_read(APIC_SPIV);
1075 value &= ~APIC_VECTOR_MASK;
1076 value |= APIC_SPIV_APIC_ENABLED;
Cyrill Gorcunov638c0412008-08-15 23:05:18 +04001077
1078#ifdef CONFIG_X86_32
1079 /* This bit is reserved on P4/Xeon and should be cleared */
1080 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1081 (boot_cpu_data.x86 == 15))
1082 value &= ~APIC_SPIV_FOCUS_DISABLED;
1083 else
1084#endif
1085 value |= APIC_SPIV_FOCUS_DISABLED;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001086 value |= SPURIOUS_APIC_VECTOR;
Andi Kleen11a8e772006-01-11 22:46:51 +01001087 apic_write(APIC_SPIV, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001088
1089 /*
1090 * Set up the virtual wire mode.
1091 */
Andi Kleen11a8e772006-01-11 22:46:51 +01001092 apic_write(APIC_LVT0, APIC_DM_EXTINT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001093 value = APIC_DM_NMI;
Cyrill Gorcunov638c0412008-08-15 23:05:18 +04001094 if (!lapic_is_integrated()) /* 82489DX */
1095 value |= APIC_LVT_LEVEL_TRIGGER;
Andi Kleen11a8e772006-01-11 22:46:51 +01001096 apic_write(APIC_LVT1, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001097}
1098
Cyrill Gorcunovc43da2f2008-08-18 20:45:54 +04001099static void __cpuinit lapic_setup_esr(void)
1100{
Cyrill Gorcunov9df08f12008-09-14 11:55:37 +04001101 unsigned int oldvalue, value, maxlvt;
Cyrill Gorcunovc43da2f2008-08-18 20:45:54 +04001102
Cyrill Gorcunov9df08f12008-09-14 11:55:37 +04001103 if (!lapic_is_integrated()) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001104 pr_info("No ESR for 82489DX.\n");
Cyrill Gorcunov9df08f12008-09-14 11:55:37 +04001105 return;
Cyrill Gorcunovc43da2f2008-08-18 20:45:54 +04001106 }
Cyrill Gorcunov9df08f12008-09-14 11:55:37 +04001107
Ingo Molnar08125d32009-01-28 05:08:44 +01001108 if (apic->disable_esr) {
Cyrill Gorcunov9df08f12008-09-14 11:55:37 +04001109 /*
1110 * Something untraceable is creating bad interrupts on
1111 * secondary quads ... for the moment, just leave the
1112 * ESR disabled - we can't do anything useful with the
1113 * errors anyway - mbligh
1114 */
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001115 pr_info("Leaving ESR disabled.\n");
Cyrill Gorcunov9df08f12008-09-14 11:55:37 +04001116 return;
1117 }
1118
1119 maxlvt = lapic_get_maxlvt();
1120 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1121 apic_write(APIC_ESR, 0);
1122 oldvalue = apic_read(APIC_ESR);
1123
1124 /* enables sending errors */
1125 value = ERROR_APIC_VECTOR;
1126 apic_write(APIC_LVTERR, value);
1127
1128 /*
1129 * spec says clear errors after enabling vector.
1130 */
1131 if (maxlvt > 3)
1132 apic_write(APIC_ESR, 0);
1133 value = apic_read(APIC_ESR);
1134 if (value != oldvalue)
1135 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1136 "vector: 0x%08x after: 0x%08x\n",
1137 oldvalue, value);
Cyrill Gorcunovc43da2f2008-08-18 20:45:54 +04001138}
1139
1140
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001141/**
1142 * setup_local_APIC - setup the local APIC
1143 */
1144void __cpuinit setup_local_APIC(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001145{
Andi Kleen739f33b2008-01-30 13:30:40 +01001146 unsigned int value;
Vivek Goyalda7ed9f2006-03-25 16:31:16 +01001147 int i, j;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001148
Jan Beulichf1182632009-01-14 12:27:35 +00001149 if (disable_apic) {
Ingo Molnar5cdc5e9e2009-01-19 20:49:37 +01001150#ifdef CONFIG_X86_IO_APIC
Jan Beulichf1182632009-01-14 12:27:35 +00001151 disable_ioapic_setup();
Ingo Molnar5cdc5e9e2009-01-19 20:49:37 +01001152#endif
Jan Beulichf1182632009-01-14 12:27:35 +00001153 return;
1154 }
1155
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -07001156#ifdef CONFIG_X86_32
1157 /* Pound the ESR really hard over the head with a big hammer - mbligh */
Ingo Molnar08125d32009-01-28 05:08:44 +01001158 if (lapic_is_integrated() && apic->disable_esr) {
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -07001159 apic_write(APIC_ESR, 0);
1160 apic_write(APIC_ESR, 0);
1161 apic_write(APIC_ESR, 0);
1162 apic_write(APIC_ESR, 0);
1163 }
1164#endif
1165
Jack Steinerac23d4e2008-03-28 14:12:16 -05001166 preempt_disable();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001167
Linus Torvalds1da177e2005-04-16 15:20:36 -07001168 /*
1169 * Double-check whether this APIC is really registered.
1170 * This is meaningless in clustered apic mode, so we skip it.
1171 */
Ingo Molnar7ed248d2009-01-28 03:43:47 +01001172 if (!apic->apic_id_registered())
Linus Torvalds1da177e2005-04-16 15:20:36 -07001173 BUG();
1174
1175 /*
1176 * Intel recommends to set DFR, LDR and TPR before enabling
1177 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1178 * document number 292116). So here it goes...
1179 */
Ingo Molnara5c43292009-01-28 06:50:47 +01001180 apic->init_apic_ldr();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001181
1182 /*
1183 * Set Task Priority to 'accept all'. We never change this
1184 * later on.
1185 */
1186 value = apic_read(APIC_TASKPRI);
1187 value &= ~APIC_TPRI_MASK;
Andi Kleen11a8e772006-01-11 22:46:51 +01001188 apic_write(APIC_TASKPRI, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001189
1190 /*
Vivek Goyalda7ed9f2006-03-25 16:31:16 +01001191 * After a crash, we no longer service the interrupts and a pending
1192 * interrupt from previous kernel might still have ISR bit set.
1193 *
1194 * Most probably by now CPU has serviced that pending interrupt and
1195 * it might not have done the ack_APIC_irq() because it thought,
1196 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1197 * does not clear the ISR bit and cpu thinks it has already serivced
1198 * the interrupt. Hence a vector might get locked. It was noticed
1199 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1200 */
1201 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1202 value = apic_read(APIC_ISR + i*0x10);
1203 for (j = 31; j >= 0; j--) {
1204 if (value & (1<<j))
1205 ack_APIC_irq();
1206 }
1207 }
1208
1209 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001210 * Now that we are all set up, enable the APIC
1211 */
1212 value = apic_read(APIC_SPIV);
1213 value &= ~APIC_VECTOR_MASK;
1214 /*
1215 * Enable APIC
1216 */
1217 value |= APIC_SPIV_APIC_ENABLED;
1218
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -07001219#ifdef CONFIG_X86_32
1220 /*
1221 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1222 * certain networking cards. If high frequency interrupts are
1223 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1224 * entry is masked/unmasked at a high rate as well then sooner or
1225 * later IOAPIC line gets 'stuck', no more interrupts are received
1226 * from the device. If focus CPU is disabled then the hang goes
1227 * away, oh well :-(
1228 *
1229 * [ This bug can be reproduced easily with a level-triggered
1230 * PCI Ne2000 networking cards and PII/PIII processors, dual
1231 * BX chipset. ]
1232 */
1233 /*
1234 * Actually disabling the focus CPU check just makes the hang less
1235 * frequent as it makes the interrupt distributon model be more
1236 * like LRU than MRU (the short-term load is more even across CPUs).
1237 * See also the comment in end_level_ioapic_irq(). --macro
1238 */
1239
1240 /*
1241 * - enable focus processor (bit==0)
1242 * - 64bit mode always use processor focus
1243 * so no need to set it
1244 */
1245 value &= ~APIC_SPIV_FOCUS_DISABLED;
1246#endif
Andi Kleen3f14c742006-09-26 10:52:29 +02001247
Linus Torvalds1da177e2005-04-16 15:20:36 -07001248 /*
1249 * Set spurious IRQ vector
1250 */
1251 value |= SPURIOUS_APIC_VECTOR;
Andi Kleen11a8e772006-01-11 22:46:51 +01001252 apic_write(APIC_SPIV, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001253
1254 /*
1255 * Set up LVT0, LVT1:
1256 *
1257 * set up through-local-APIC on the BP's LINT0. This is not
1258 * strictly necessary in pure symmetric-IO mode, but sometimes
1259 * we delegate interrupts to the 8259A.
1260 */
1261 /*
1262 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1263 */
1264 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -07001265 if (!smp_processor_id() && (pic_mode || !value)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001266 value = APIC_DM_EXTINT;
Chris Wrightbc1d99c2007-10-12 23:04:23 +02001267 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -07001268 smp_processor_id());
Linus Torvalds1da177e2005-04-16 15:20:36 -07001269 } else {
1270 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
Chris Wrightbc1d99c2007-10-12 23:04:23 +02001271 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -07001272 smp_processor_id());
Linus Torvalds1da177e2005-04-16 15:20:36 -07001273 }
Andi Kleen11a8e772006-01-11 22:46:51 +01001274 apic_write(APIC_LVT0, value);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001275
1276 /*
1277 * only the BP should see the LINT1 NMI signal, obviously.
1278 */
1279 if (!smp_processor_id())
1280 value = APIC_DM_NMI;
1281 else
1282 value = APIC_DM_NMI | APIC_LVT_MASKED;
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -07001283 if (!lapic_is_integrated()) /* 82489DX */
1284 value |= APIC_LVT_LEVEL_TRIGGER;
Andi Kleen11a8e772006-01-11 22:46:51 +01001285 apic_write(APIC_LVT1, value);
Cyrill Gorcunov89c38c22008-08-24 02:01:43 -07001286
Jack Steinerac23d4e2008-03-28 14:12:16 -05001287 preempt_enable();
Andi Kleen739f33b2008-01-30 13:30:40 +01001288}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001289
Andi Kleen739f33b2008-01-30 13:30:40 +01001290void __cpuinit end_local_APIC_setup(void)
1291{
1292 lapic_setup_esr();
Cyrill Gorcunovfa6b95f2008-08-18 20:45:58 +04001293
1294#ifdef CONFIG_X86_32
Cyrill Gorcunov1b4ee4e2008-08-18 23:12:33 +04001295 {
1296 unsigned int value;
1297 /* Disable the local apic timer */
1298 value = apic_read(APIC_LVTT);
1299 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1300 apic_write(APIC_LVTT, value);
1301 }
Cyrill Gorcunovfa6b95f2008-08-18 20:45:58 +04001302#endif
1303
Don Zickusf2802e72006-09-26 10:52:26 +02001304 setup_apic_nmi_watchdog(NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001305 apic_pm_activate();
1306}
1307
Yinghai Lu49899ea2008-08-24 02:01:47 -07001308#ifdef HAVE_X2APIC
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001309void check_x2apic(void)
1310{
1311 int msr, msr2;
1312
1313 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1314
1315 if (msr & X2APIC_ENABLE) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001316 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001317 x2apic_preenabled = x2apic = 1;
1318 apic_ops = &x2apic_ops;
1319 }
1320}
1321
1322void enable_x2apic(void)
1323{
1324 int msr, msr2;
1325
1326 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1327 if (!(msr & X2APIC_ENABLE)) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001328 pr_info("Enabling x2apic\n");
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001329 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
1330 }
1331}
1332
Al Viro2236d252008-11-22 17:37:34 +00001333void __init enable_IR_x2apic(void)
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001334{
1335#ifdef CONFIG_INTR_REMAP
1336 int ret;
1337 unsigned long flags;
1338
1339 if (!cpu_has_x2apic)
1340 return;
1341
1342 if (!x2apic_preenabled && disable_x2apic) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001343 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1344 "because of nox2apic\n");
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001345 return;
1346 }
1347
1348 if (x2apic_preenabled && disable_x2apic)
1349 panic("Bios already enabled x2apic, can't enforce nox2apic");
1350
1351 if (!x2apic_preenabled && skip_ioapic_setup) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001352 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1353 "because of skipping io-apic setup\n");
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001354 return;
1355 }
1356
1357 ret = dmar_table_init();
1358 if (ret) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001359 pr_info("dmar_table_init() failed with %d:\n", ret);
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001360
1361 if (x2apic_preenabled)
1362 panic("x2apic enabled by bios. But IR enabling failed");
1363 else
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001364 pr_info("Not enabling x2apic,Intr-remapping\n");
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001365 return;
1366 }
1367
1368 local_irq_save(flags);
1369 mask_8259A();
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +04001370
1371 ret = save_mask_IO_APIC_setup();
1372 if (ret) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001373 pr_info("Saving IO-APIC state failed: %d\n", ret);
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +04001374 goto end;
1375 }
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001376
1377 ret = enable_intr_remapping(1);
1378
1379 if (ret && x2apic_preenabled) {
1380 local_irq_restore(flags);
1381 panic("x2apic enabled by bios. But IR enabling failed");
1382 }
1383
1384 if (ret)
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +04001385 goto end_restore;
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001386
1387 if (!x2apic) {
1388 x2apic = 1;
1389 apic_ops = &x2apic_ops;
1390 enable_x2apic();
1391 }
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +04001392
1393end_restore:
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001394 if (ret)
1395 /*
1396 * IR enabling failed
1397 */
1398 restore_IO_APIC_setup();
1399 else
1400 reinit_intr_remapped_IO_APIC(x2apic_preenabled);
1401
Cyrill Gorcunov5ffa4eb2008-09-18 23:37:57 +04001402end:
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001403 unmask_8259A();
1404 local_irq_restore(flags);
1405
1406 if (!ret) {
1407 if (!x2apic_preenabled)
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001408 pr_info("Enabled x2apic and interrupt-remapping\n");
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001409 else
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001410 pr_info("Enabled Interrupt-remapping\n");
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001411 } else
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001412 pr_err("Failed to enable Interrupt-remapping and x2apic\n");
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001413#else
1414 if (!cpu_has_x2apic)
1415 return;
1416
1417 if (x2apic_preenabled)
1418 panic("x2apic enabled prior OS handover,"
1419 " enable CONFIG_INTR_REMAP");
1420
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001421 pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1422 " and x2apic\n");
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001423#endif
1424
1425 return;
1426}
Yinghai Lu49899ea2008-08-24 02:01:47 -07001427#endif /* HAVE_X2APIC */
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001428
Yinghai Lube7a6562008-08-24 02:01:51 -07001429#ifdef CONFIG_X86_64
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001430/*
1431 * Detect and enable local APICs on non-SMP boards.
1432 * Original code written by Keir Fraser.
1433 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1434 * not correctly set up (usually the APIC timer won't work etc.)
1435 */
1436static int __init detect_init_APIC(void)
1437{
1438 if (!cpu_has_apic) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001439 pr_info("No local APIC present\n");
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001440 return -1;
1441 }
1442
1443 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
Glauber de Oliveira Costac70dcb72008-03-19 14:25:58 -03001444 boot_cpu_physical_apicid = 0;
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001445 return 0;
1446}
Yinghai Lube7a6562008-08-24 02:01:51 -07001447#else
1448/*
1449 * Detect and initialize APIC
1450 */
1451static int __init detect_init_APIC(void)
1452{
1453 u32 h, l, features;
1454
1455 /* Disabled by kernel option? */
1456 if (disable_apic)
1457 return -1;
1458
1459 switch (boot_cpu_data.x86_vendor) {
1460 case X86_VENDOR_AMD:
1461 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1462 (boot_cpu_data.x86 == 15))
1463 break;
1464 goto no_apic;
1465 case X86_VENDOR_INTEL:
1466 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1467 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1468 break;
1469 goto no_apic;
1470 default:
1471 goto no_apic;
1472 }
1473
1474 if (!cpu_has_apic) {
1475 /*
1476 * Over-ride BIOS and try to enable the local APIC only if
1477 * "lapic" specified.
1478 */
1479 if (!force_enable_local_apic) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001480 pr_info("Local APIC disabled by BIOS -- "
1481 "you can enable it with \"lapic\"\n");
Yinghai Lube7a6562008-08-24 02:01:51 -07001482 return -1;
1483 }
1484 /*
1485 * Some BIOSes disable the local APIC in the APIC_BASE
1486 * MSR. This can only be done in software for Intel P6 or later
1487 * and AMD K7 (Model > 1) or later.
1488 */
1489 rdmsr(MSR_IA32_APICBASE, l, h);
1490 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001491 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
Yinghai Lube7a6562008-08-24 02:01:51 -07001492 l &= ~MSR_IA32_APICBASE_BASE;
1493 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
1494 wrmsr(MSR_IA32_APICBASE, l, h);
1495 enabled_via_apicbase = 1;
1496 }
1497 }
1498 /*
1499 * The APIC feature bit should now be enabled
1500 * in `cpuid'
1501 */
1502 features = cpuid_edx(1);
1503 if (!(features & (1 << X86_FEATURE_APIC))) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001504 pr_warning("Could not enable APIC!\n");
Yinghai Lube7a6562008-08-24 02:01:51 -07001505 return -1;
1506 }
1507 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1508 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1509
1510 /* The BIOS may have set up the APIC at some other address */
1511 rdmsr(MSR_IA32_APICBASE, l, h);
1512 if (l & MSR_IA32_APICBASE_ENABLE)
1513 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1514
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001515 pr_info("Found and enabled local APIC!\n");
Yinghai Lube7a6562008-08-24 02:01:51 -07001516
1517 apic_pm_activate();
1518
1519 return 0;
1520
1521no_apic:
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001522 pr_info("No local APIC present or hardware disabled\n");
Yinghai Lube7a6562008-08-24 02:01:51 -07001523 return -1;
1524}
1525#endif
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001526
Yinghai Luf28c0ae2008-08-24 02:01:49 -07001527#ifdef CONFIG_X86_64
Yinghai Lu8643f9d2008-02-19 03:21:06 -08001528void __init early_init_lapic_mapping(void)
1529{
Thomas Gleixner431ee792008-05-12 15:43:35 +02001530 unsigned long phys_addr;
Yinghai Lu8643f9d2008-02-19 03:21:06 -08001531
1532 /*
1533 * If no local APIC can be found then go out
1534 * : it means there is no mpatable and MADT
1535 */
1536 if (!smp_found_config)
1537 return;
1538
Thomas Gleixner431ee792008-05-12 15:43:35 +02001539 phys_addr = mp_lapic_addr;
Yinghai Lu8643f9d2008-02-19 03:21:06 -08001540
Thomas Gleixner431ee792008-05-12 15:43:35 +02001541 set_fixmap_nocache(FIX_APIC_BASE, phys_addr);
Yinghai Lu8643f9d2008-02-19 03:21:06 -08001542 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
Thomas Gleixner431ee792008-05-12 15:43:35 +02001543 APIC_BASE, phys_addr);
Yinghai Lu8643f9d2008-02-19 03:21:06 -08001544
1545 /*
1546 * Fetch the APIC ID of the BSP in case we have a
1547 * default configuration (or the MP table is broken).
1548 */
Yinghai Lu4c9961d2008-07-11 18:44:16 -07001549 boot_cpu_physical_apicid = read_apic_id();
Yinghai Lu8643f9d2008-02-19 03:21:06 -08001550}
Yinghai Luf28c0ae2008-08-24 02:01:49 -07001551#endif
Yinghai Lu8643f9d2008-02-19 03:21:06 -08001552
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001553/**
1554 * init_apic_mappings - initialize APIC mappings
1555 */
1556void __init init_apic_mappings(void)
1557{
Yinghai Lu49899ea2008-08-24 02:01:47 -07001558#ifdef HAVE_X2APIC
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001559 if (x2apic) {
Yinghai Lu4c9961d2008-07-11 18:44:16 -07001560 boot_cpu_physical_apicid = read_apic_id();
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001561 return;
1562 }
Yinghai Lu49899ea2008-08-24 02:01:47 -07001563#endif
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001564
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001565 /*
1566 * If no local APIC can be found then set up a fake all
1567 * zeroes page to simulate the local APIC and another
1568 * one for the IO-APIC.
1569 */
1570 if (!smp_found_config && detect_init_APIC()) {
1571 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
1572 apic_phys = __pa(apic_phys);
1573 } else
1574 apic_phys = mp_lapic_addr;
1575
1576 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
Yinghai Lu79c09692008-09-07 17:58:57 -07001577 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n",
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001578 APIC_BASE, apic_phys);
1579
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001580 /*
1581 * Fetch the APIC ID of the BSP in case we have a
1582 * default configuration (or the MP table is broken).
1583 */
Yinghai Luf28c0ae2008-08-24 02:01:49 -07001584 if (boot_cpu_physical_apicid == -1U)
1585 boot_cpu_physical_apicid = read_apic_id();
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001586}
1587
1588/*
1589 * This initializes the IO-APIC and APIC hardware if this is
1590 * a UP kernel.
1591 */
Cyrill Gorcunov1b313f42008-08-18 20:45:57 +04001592int apic_version[MAX_APICS];
1593
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001594int __init APIC_init_uniprocessor(void)
1595{
1596 if (disable_apic) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001597 pr_info("Apic disabled\n");
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001598 return -1;
1599 }
Jan Beulichf1182632009-01-14 12:27:35 +00001600#ifdef CONFIG_X86_64
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001601 if (!cpu_has_apic) {
1602 disable_apic = 1;
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001603 pr_info("Apic disabled by BIOS\n");
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001604 return -1;
1605 }
Yinghai Lufa2bd352008-08-24 02:01:50 -07001606#else
1607 if (!smp_found_config && !cpu_has_apic)
1608 return -1;
1609
1610 /*
1611 * Complain if the BIOS pretends there is one.
1612 */
1613 if (!cpu_has_apic &&
1614 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001615 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1616 boot_cpu_physical_apicid);
Yinghai Lufa2bd352008-08-24 02:01:50 -07001617 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1618 return -1;
1619 }
1620#endif
1621
Yinghai Lu49899ea2008-08-24 02:01:47 -07001622#ifdef HAVE_X2APIC
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001623 enable_IR_x2apic();
Yinghai Lu49899ea2008-08-24 02:01:47 -07001624#endif
Yinghai Lufa2bd352008-08-24 02:01:50 -07001625#ifdef CONFIG_X86_64
Ingo Molnar72ce0162009-01-28 06:50:47 +01001626 default_setup_apic_routing();
Yinghai Lufa2bd352008-08-24 02:01:50 -07001627#endif
Suresh Siddha6e1cb382008-07-10 11:16:58 -07001628
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001629 verify_local_APIC();
Glauber Costab5841762008-05-28 13:38:28 -03001630 connect_bsp_APIC();
1631
Yinghai Lufa2bd352008-08-24 02:01:50 -07001632#ifdef CONFIG_X86_64
Glauber de Oliveira Costac70dcb72008-03-19 14:25:58 -03001633 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
Yinghai Lufa2bd352008-08-24 02:01:50 -07001634#else
1635 /*
1636 * Hack: In case of kdump, after a crash, kernel might be booting
1637 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1638 * might be zero if read from MP tables. Get it from LAPIC.
1639 */
1640# ifdef CONFIG_CRASH_DUMP
1641 boot_cpu_physical_apicid = read_apic_id();
1642# endif
1643#endif
1644 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001645 setup_local_APIC();
1646
Yinghai Lufa2bd352008-08-24 02:01:50 -07001647#ifdef CONFIG_X86_64
Andi Kleen739f33b2008-01-30 13:30:40 +01001648 /*
1649 * Now enable IO-APICs, actually call clear_IO_APIC
1650 * We need clear_IO_APIC before enabling vector on BP
1651 */
1652 if (!skip_ioapic_setup && nr_ioapics)
1653 enable_IO_APIC();
Yinghai Lufa2bd352008-08-24 02:01:50 -07001654#endif
Andi Kleen739f33b2008-01-30 13:30:40 +01001655
Yinghai Lufa2bd352008-08-24 02:01:50 -07001656#ifdef CONFIG_X86_IO_APIC
Maciej W. Rozyckiacae7d92008-06-06 03:27:49 +01001657 if (!smp_found_config || skip_ioapic_setup || !nr_ioapics)
Yinghai Lufa2bd352008-08-24 02:01:50 -07001658#endif
Maciej W. Rozyckiacae7d92008-06-06 03:27:49 +01001659 localise_nmi_watchdog();
Andi Kleen739f33b2008-01-30 13:30:40 +01001660 end_local_APIC_setup();
1661
Yinghai Lufa2bd352008-08-24 02:01:50 -07001662#ifdef CONFIG_X86_IO_APIC
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001663 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1664 setup_IO_APIC();
Yinghai Lufa2bd352008-08-24 02:01:50 -07001665# ifdef CONFIG_X86_64
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001666 else
1667 nr_ioapics = 0;
Yinghai Lufa2bd352008-08-24 02:01:50 -07001668# endif
1669#endif
1670
1671#ifdef CONFIG_X86_64
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001672 setup_boot_APIC_clock();
1673 check_nmi_watchdog();
Yinghai Lufa2bd352008-08-24 02:01:50 -07001674#else
1675 setup_boot_clock();
1676#endif
1677
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001678 return 0;
1679}
1680
1681/*
1682 * Local APIC interrupts
1683 */
1684
1685/*
1686 * This interrupt should _never_ happen with our APIC/SMP architecture
1687 */
Yinghai Ludc1528d2008-08-24 02:01:53 -07001688void smp_spurious_interrupt(struct pt_regs *regs)
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001689{
Yinghai Ludc1528d2008-08-24 02:01:53 -07001690 u32 v;
1691
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001692 exit_idle();
1693 irq_enter();
1694 /*
1695 * Check if this really is a spurious interrupt and ACK it
1696 * if it is a vectored one. Just in case...
1697 * Spurious interrupts should not be ACKed.
1698 */
1699 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1700 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1701 ack_APIC_irq();
1702
Hiroshi Shimamoto915b0d02008-12-08 19:19:26 -08001703 inc_irq_stat(irq_spurious_count);
1704
Yinghai Ludc1528d2008-08-24 02:01:53 -07001705 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001706 pr_info("spurious APIC interrupt on CPU#%d, "
1707 "should never happen.\n", smp_processor_id());
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001708 irq_exit();
1709}
1710
1711/*
1712 * This interrupt should never happen with our APIC/SMP architecture
1713 */
Yinghai Ludc1528d2008-08-24 02:01:53 -07001714void smp_error_interrupt(struct pt_regs *regs)
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001715{
Yinghai Ludc1528d2008-08-24 02:01:53 -07001716 u32 v, v1;
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001717
1718 exit_idle();
1719 irq_enter();
1720 /* First tickle the hardware, only then report what went on. -- REW */
1721 v = apic_read(APIC_ESR);
1722 apic_write(APIC_ESR, 0);
1723 v1 = apic_read(APIC_ESR);
1724 ack_APIC_irq();
1725 atomic_inc(&irq_err_count);
1726
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001727 /*
1728 * Here is what the APIC error bits mean:
1729 * 0: Send CS error
1730 * 1: Receive CS error
1731 * 2: Send accept error
1732 * 3: Receive accept error
1733 * 4: Reserved
1734 * 5: Send illegal vector
1735 * 6: Received illegal vector
1736 * 7: Illegal register address
1737 */
1738 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001739 smp_processor_id(), v , v1);
1740 irq_exit();
1741}
1742
Glauber Costab5841762008-05-28 13:38:28 -03001743/**
Cyrill Gorcunov36c9d672008-08-18 20:45:53 +04001744 * connect_bsp_APIC - attach the APIC to the interrupt system
1745 */
Glauber Costab5841762008-05-28 13:38:28 -03001746void __init connect_bsp_APIC(void)
1747{
Cyrill Gorcunov36c9d672008-08-18 20:45:53 +04001748#ifdef CONFIG_X86_32
1749 if (pic_mode) {
1750 /*
1751 * Do not trust the local APIC being empty at bootup.
1752 */
1753 clear_local_APIC();
1754 /*
1755 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1756 * local APIC to INT and NMI lines.
1757 */
1758 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1759 "enabling APIC mode.\n");
1760 outb(0x70, 0x22);
1761 outb(0x01, 0x23);
1762 }
1763#endif
Ingo Molnar49040332009-01-28 12:43:18 +01001764 if (apic->enable_apic_mode)
1765 apic->enable_apic_mode();
Glauber Costab5841762008-05-28 13:38:28 -03001766}
1767
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +04001768/**
1769 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1770 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1771 *
1772 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1773 * APIC is disabled.
1774 */
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001775void disconnect_bsp_APIC(int virt_wire_setup)
1776{
Cyrill Gorcunov1b4ee4e2008-08-18 23:12:33 +04001777 unsigned int value;
1778
Cyrill Gorcunovc177b0b2008-08-18 20:45:56 +04001779#ifdef CONFIG_X86_32
1780 if (pic_mode) {
1781 /*
1782 * Put the board back into PIC mode (has an effect only on
1783 * certain older boards). Note that APIC interrupts, including
1784 * IPIs, won't work beyond this point! The only exception are
1785 * INIT IPIs.
1786 */
1787 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1788 "entering PIC mode.\n");
1789 outb(0x70, 0x22);
1790 outb(0x00, 0x23);
1791 return;
1792 }
1793#endif
1794
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001795 /* Go back to Virtual Wire compatibility mode */
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001796
1797 /* For the spurious interrupt use vector F, and enable it */
1798 value = apic_read(APIC_SPIV);
1799 value &= ~APIC_VECTOR_MASK;
1800 value |= APIC_SPIV_APIC_ENABLED;
1801 value |= 0xf;
1802 apic_write(APIC_SPIV, value);
1803
1804 if (!virt_wire_setup) {
1805 /*
1806 * For LVT0 make it edge triggered, active high,
1807 * external and enabled
1808 */
1809 value = apic_read(APIC_LVT0);
1810 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1811 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1812 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1813 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1814 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1815 apic_write(APIC_LVT0, value);
1816 } else {
1817 /* Disable LVT0 */
1818 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1819 }
1820
Cyrill Gorcunovc177b0b2008-08-18 20:45:56 +04001821 /*
1822 * For LVT1 make it edge triggered, active high,
1823 * nmi and enabled
1824 */
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001825 value = apic_read(APIC_LVT1);
1826 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1827 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1828 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1829 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1830 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1831 apic_write(APIC_LVT1, value);
1832}
1833
Alexey Starikovskiybe8a5682008-03-27 23:56:19 +03001834void __cpuinit generic_processor_info(int apicid, int version)
1835{
1836 int cpu;
Alexey Starikovskiybe8a5682008-03-27 23:56:19 +03001837
Cyrill Gorcunov1b313f42008-08-18 20:45:57 +04001838 /*
1839 * Validate version
1840 */
1841 if (version == 0x0) {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01001842 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
Mike Travis3b11ce72008-12-17 15:21:39 -08001843 "fixing up to 0x10. (tell your hw vendor)\n",
1844 version);
Cyrill Gorcunov1b313f42008-08-18 20:45:57 +04001845 version = 0x10;
1846 }
1847 apic_version[apicid] = version;
1848
Mike Travis3b11ce72008-12-17 15:21:39 -08001849 if (num_processors >= nr_cpu_ids) {
1850 int max = nr_cpu_ids;
1851 int thiscpu = max + disabled_cpus;
1852
1853 pr_warning(
1854 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1855 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
1856
1857 disabled_cpus++;
Alexey Starikovskiybe8a5682008-03-27 23:56:19 +03001858 return;
1859 }
1860
1861 num_processors++;
Mike Travis3b11ce72008-12-17 15:21:39 -08001862 cpu = cpumask_next_zero(-1, cpu_present_mask);
Alexey Starikovskiybe8a5682008-03-27 23:56:19 +03001863
Mike Traviscef30b32009-01-16 15:58:13 -08001864 if (version != apic_version[boot_cpu_physical_apicid])
1865 WARN_ONCE(1,
1866 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1867 apic_version[boot_cpu_physical_apicid], cpu, version);
1868
Alexey Starikovskiybe8a5682008-03-27 23:56:19 +03001869 physid_set(apicid, phys_cpu_present_map);
1870 if (apicid == boot_cpu_physical_apicid) {
1871 /*
1872 * x86_bios_cpu_apicid is required to have processors listed
1873 * in same order as logical cpu numbers. Hence the first
1874 * entry is BSP, and so on.
1875 */
1876 cpu = 0;
1877 }
Yinghai Lue0da3362008-06-08 18:29:22 -07001878 if (apicid > max_physical_apicid)
1879 max_physical_apicid = apicid;
1880
Cyrill Gorcunov1b313f42008-08-18 20:45:57 +04001881#ifdef CONFIG_X86_32
1882 /*
1883 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1884 * but we need to work other dependencies like SMP_SUSPEND etc
1885 * before this can be done without some confusion.
1886 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1887 * - Ashok Raj <ashok.raj@intel.com>
1888 */
1889 if (max_physical_apicid >= 8) {
1890 switch (boot_cpu_data.x86_vendor) {
1891 case X86_VENDOR_INTEL:
1892 if (!APIC_XAPIC(version)) {
1893 def_to_bigsmp = 0;
1894 break;
1895 }
1896 /* If P4 and above fall through */
1897 case X86_VENDOR_AMD:
1898 def_to_bigsmp = 1;
1899 }
1900 }
1901#endif
1902
1903#if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
Tejun Heof10fcd42009-01-13 20:41:34 +09001904 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1905 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
Cyrill Gorcunov1b313f42008-08-18 20:45:57 +04001906#endif
Alexey Starikovskiybe8a5682008-03-27 23:56:19 +03001907
Mike Travis1de88cd2008-12-16 17:34:02 -08001908 set_cpu_possible(cpu, true);
1909 set_cpu_present(cpu, true);
Alexey Starikovskiybe8a5682008-03-27 23:56:19 +03001910}
1911
Suresh Siddha0c81c742008-07-10 11:16:48 -07001912int hard_smp_processor_id(void)
1913{
1914 return read_apic_id();
1915}
Ingo Molnar1dcdd3d2009-01-28 17:55:37 +01001916
1917void default_init_apic_ldr(void)
1918{
1919 unsigned long val;
1920
1921 apic_write(APIC_DFR, APIC_DFR_VALUE);
1922 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
1923 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
1924 apic_write(APIC_LDR, val);
1925}
1926
1927#ifdef CONFIG_X86_32
1928int default_apicid_to_node(int logical_apicid)
1929{
1930#ifdef CONFIG_SMP
1931 return apicid_2_node[hard_smp_processor_id()];
1932#else
1933 return 0;
1934#endif
1935}
Yinghai Lu34919982008-08-24 02:01:48 -07001936#endif
Suresh Siddha0c81c742008-07-10 11:16:48 -07001937
Thomas Gleixner0e078e22008-01-30 13:30:20 +01001938/*
1939 * Power management
1940 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001941#ifdef CONFIG_PM
1942
1943static struct {
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +04001944 /*
1945 * 'active' is true if the local APIC was enabled by us and
1946 * not the BIOS; this signifies that we are also responsible
1947 * for disabling it before entering apm/acpi suspend
1948 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001949 int active;
1950 /* r/w apic fields */
1951 unsigned int apic_id;
1952 unsigned int apic_taskpri;
1953 unsigned int apic_ldr;
1954 unsigned int apic_dfr;
1955 unsigned int apic_spiv;
1956 unsigned int apic_lvtt;
1957 unsigned int apic_lvtpc;
1958 unsigned int apic_lvt0;
1959 unsigned int apic_lvt1;
1960 unsigned int apic_lvterr;
1961 unsigned int apic_tmict;
1962 unsigned int apic_tdcr;
1963 unsigned int apic_thmr;
1964} apic_pm_state;
1965
Pavel Machek0b9c33a2005-04-16 15:25:31 -07001966static int lapic_suspend(struct sys_device *dev, pm_message_t state)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001967{
1968 unsigned long flags;
Karsten Wiesef990fff2006-12-07 02:14:11 +01001969 int maxlvt;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001970
1971 if (!apic_pm_state.active)
1972 return 0;
1973
Thomas Gleixner37e650c2008-01-30 13:30:14 +01001974 maxlvt = lapic_get_maxlvt();
Karsten Wiesef990fff2006-12-07 02:14:11 +01001975
Suresh Siddha2d7a66d2008-07-11 14:24:19 -07001976 apic_pm_state.apic_id = apic_read(APIC_ID);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001977 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1978 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1979 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1980 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1981 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
Karsten Wiesef990fff2006-12-07 02:14:11 +01001982 if (maxlvt >= 4)
1983 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001984 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1985 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1986 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1987 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1988 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
Cyrill Gorcunov24968cf2008-08-16 23:21:52 +04001989#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
Karsten Wiesef990fff2006-12-07 02:14:11 +01001990 if (maxlvt >= 5)
1991 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1992#endif
Cyrill Gorcunov24968cf2008-08-16 23:21:52 +04001993
Fernando Luis Vázquez Cao2b94ab22006-09-26 10:52:33 +02001994 local_irq_save(flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001995 disable_local_APIC();
1996 local_irq_restore(flags);
1997 return 0;
1998}
1999
2000static int lapic_resume(struct sys_device *dev)
2001{
2002 unsigned int l, h;
2003 unsigned long flags;
Karsten Wiesef990fff2006-12-07 02:14:11 +01002004 int maxlvt;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002005
2006 if (!apic_pm_state.active)
2007 return 0;
2008
Thomas Gleixner37e650c2008-01-30 13:30:14 +01002009 maxlvt = lapic_get_maxlvt();
Karsten Wiesef990fff2006-12-07 02:14:11 +01002010
Linus Torvalds1da177e2005-04-16 15:20:36 -07002011 local_irq_save(flags);
Cyrill Gorcunov92206c92008-08-16 23:21:51 +04002012
Yinghai Lu49899ea2008-08-24 02:01:47 -07002013#ifdef HAVE_X2APIC
Cyrill Gorcunov92206c92008-08-16 23:21:51 +04002014 if (x2apic)
2015 enable_x2apic();
2016 else
2017#endif
Yinghai Lud5e629a2008-08-17 21:12:27 -07002018 {
Cyrill Gorcunov92206c92008-08-16 23:21:51 +04002019 /*
2020 * Make sure the APICBASE points to the right address
2021 *
2022 * FIXME! This will be wrong if we ever support suspend on
2023 * SMP! We'll need to do this as part of the CPU restore!
2024 */
Suresh Siddha6e1cb382008-07-10 11:16:58 -07002025 rdmsr(MSR_IA32_APICBASE, l, h);
2026 l &= ~MSR_IA32_APICBASE_BASE;
2027 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2028 wrmsr(MSR_IA32_APICBASE, l, h);
Yinghai Lud5e629a2008-08-17 21:12:27 -07002029 }
Suresh Siddha6e1cb382008-07-10 11:16:58 -07002030
Linus Torvalds1da177e2005-04-16 15:20:36 -07002031 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2032 apic_write(APIC_ID, apic_pm_state.apic_id);
2033 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2034 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2035 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2036 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2037 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2038 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
Cyrill Gorcunov92206c92008-08-16 23:21:51 +04002039#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
Karsten Wiesef990fff2006-12-07 02:14:11 +01002040 if (maxlvt >= 5)
2041 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2042#endif
2043 if (maxlvt >= 4)
2044 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002045 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2046 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2047 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2048 apic_write(APIC_ESR, 0);
2049 apic_read(APIC_ESR);
2050 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2051 apic_write(APIC_ESR, 0);
2052 apic_read(APIC_ESR);
Cyrill Gorcunov92206c92008-08-16 23:21:51 +04002053
Linus Torvalds1da177e2005-04-16 15:20:36 -07002054 local_irq_restore(flags);
Cyrill Gorcunov92206c92008-08-16 23:21:51 +04002055
Linus Torvalds1da177e2005-04-16 15:20:36 -07002056 return 0;
2057}
2058
Cyrill Gorcunov274cfe52008-08-16 23:21:53 +04002059/*
2060 * This device has no shutdown method - fully functioning local APICs
2061 * are needed on every CPU up until machine_halt/restart/poweroff.
2062 */
2063
Linus Torvalds1da177e2005-04-16 15:20:36 -07002064static struct sysdev_class lapic_sysclass = {
Kay Sieversaf5ca3f2007-12-20 02:09:39 +01002065 .name = "lapic",
Linus Torvalds1da177e2005-04-16 15:20:36 -07002066 .resume = lapic_resume,
2067 .suspend = lapic_suspend,
2068};
2069
2070static struct sys_device device_lapic = {
Hiroshi Shimamotoe83a5fd2008-01-30 13:32:35 +01002071 .id = 0,
2072 .cls = &lapic_sysclass,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002073};
2074
Ashok Raje6982c62005-06-25 14:54:58 -07002075static void __cpuinit apic_pm_activate(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002076{
2077 apic_pm_state.active = 1;
2078}
2079
2080static int __init init_lapic_sysfs(void)
2081{
2082 int error;
Hiroshi Shimamotoe83a5fd2008-01-30 13:32:35 +01002083
Linus Torvalds1da177e2005-04-16 15:20:36 -07002084 if (!cpu_has_apic)
2085 return 0;
2086 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
Hiroshi Shimamotoe83a5fd2008-01-30 13:32:35 +01002087
Linus Torvalds1da177e2005-04-16 15:20:36 -07002088 error = sysdev_class_register(&lapic_sysclass);
2089 if (!error)
2090 error = sysdev_register(&device_lapic);
2091 return error;
2092}
2093device_initcall(init_lapic_sysfs);
2094
2095#else /* CONFIG_PM */
2096
2097static void apic_pm_activate(void) { }
2098
2099#endif /* CONFIG_PM */
2100
Yinghai Luf28c0ae2008-08-24 02:01:49 -07002101#ifdef CONFIG_X86_64
Linus Torvalds1da177e2005-04-16 15:20:36 -07002102/*
Vojtech Pavlikf8bf3c62006-06-26 13:58:23 +02002103 * apic_is_clustered_box() -- Check if we can expect good TSC
Linus Torvalds1da177e2005-04-16 15:20:36 -07002104 *
2105 * Thus far, the major user of this is IBM's Summit2 series:
2106 *
Linus Torvalds637029c2006-02-27 20:41:56 -08002107 * Clustered boxes may have unsynced TSC problems if they are
Linus Torvalds1da177e2005-04-16 15:20:36 -07002108 * multi-chassis. Use available data to take a good guess.
2109 * If in doubt, go HPET.
2110 */
Vojtech Pavlikf8bf3c62006-06-26 13:58:23 +02002111__cpuinit int apic_is_clustered_box(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002112{
2113 int i, clusters, zeros;
2114 unsigned id;
Yinghai Lu322850a2008-02-23 21:48:42 -08002115 u16 *bios_cpu_apicid;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002116 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
2117
Yinghai Lu322850a2008-02-23 21:48:42 -08002118 /*
2119 * there is not this kind of box with AMD CPU yet.
2120 * Some AMD box with quadcore cpu and 8 sockets apicid
2121 * will be [4, 0x23] or [8, 0x27] could be thought to
Yinghai Luf8fffa42008-02-24 21:36:28 -08002122 * vsmp box still need checking...
Yinghai Lu322850a2008-02-23 21:48:42 -08002123 */
Ravikiran G Thirumalai1cb68482008-03-20 00:45:08 -07002124 if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
Yinghai Lu322850a2008-02-23 21:48:42 -08002125 return 0;
2126
Mike Travis23ca4bb2008-05-12 21:21:12 +02002127 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
Suresh Siddha376ec332005-05-16 21:53:32 -07002128 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002129
Mike Travis168ef542008-12-16 17:34:01 -08002130 for (i = 0; i < nr_cpu_ids; i++) {
travis@sgi.come8c10ef2008-01-30 13:33:12 +01002131 /* are we being called early in kernel startup? */
Mike Travis693e3c52008-01-30 13:33:14 +01002132 if (bios_cpu_apicid) {
2133 id = bios_cpu_apicid[i];
Jaswinder Singh Rajpute423e332009-01-04 16:16:25 +05302134 } else if (i < nr_cpu_ids) {
travis@sgi.come8c10ef2008-01-30 13:33:12 +01002135 if (cpu_present(i))
2136 id = per_cpu(x86_bios_cpu_apicid, i);
2137 else
2138 continue;
Jaswinder Singh Rajpute423e332009-01-04 16:16:25 +05302139 } else
travis@sgi.come8c10ef2008-01-30 13:33:12 +01002140 break;
2141
Linus Torvalds1da177e2005-04-16 15:20:36 -07002142 if (id != BAD_APICID)
2143 __set_bit(APIC_CLUSTERID(id), clustermap);
2144 }
2145
2146 /* Problem: Partially populated chassis may not have CPUs in some of
2147 * the APIC clusters they have been allocated. Only present CPUs have
travis@sgi.com602a54a2008-01-30 13:33:21 +01002148 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2149 * Since clusters are allocated sequentially, count zeros only if
2150 * they are bounded by ones.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002151 */
2152 clusters = 0;
2153 zeros = 0;
2154 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
2155 if (test_bit(i, clustermap)) {
2156 clusters += 1 + zeros;
2157 zeros = 0;
2158 } else
2159 ++zeros;
2160 }
2161
Ravikiran G Thirumalai1cb68482008-03-20 00:45:08 -07002162 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2163 * not guaranteed to be synced between boards
2164 */
2165 if (is_vsmp_box() && clusters > 1)
2166 return 1;
2167
Linus Torvalds1da177e2005-04-16 15:20:36 -07002168 /*
Vojtech Pavlikf8bf3c62006-06-26 13:58:23 +02002169 * If clusters > 2, then should be multi-chassis.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002170 * May have to revisit this when multi-core + hyperthreaded CPUs come
2171 * out, but AFAIK this will work even for them.
2172 */
2173 return (clusters > 2);
2174}
Yinghai Luf28c0ae2008-08-24 02:01:49 -07002175#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002176
2177/*
Thomas Gleixner0e078e22008-01-30 13:30:20 +01002178 * APIC command line parameters
Linus Torvalds1da177e2005-04-16 15:20:36 -07002179 */
Cyrill Gorcunov789fa732008-08-18 20:46:01 +04002180static int __init setup_disableapic(char *arg)
Thomas Gleixner6935d1f2007-07-21 17:10:17 +02002181{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002182 disable_apic = 1;
Yinghai Lu9175fc02008-07-21 01:38:14 -07002183 setup_clear_cpu_cap(X86_FEATURE_APIC);
Andi Kleen2c8c0e62006-09-26 10:52:32 +02002184 return 0;
2185}
2186early_param("disableapic", setup_disableapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002187
Andi Kleen2c8c0e62006-09-26 10:52:32 +02002188/* same as disableapic, for compatibility */
Cyrill Gorcunov789fa732008-08-18 20:46:01 +04002189static int __init setup_nolapic(char *arg)
Thomas Gleixner6935d1f2007-07-21 17:10:17 +02002190{
Cyrill Gorcunov789fa732008-08-18 20:46:01 +04002191 return setup_disableapic(arg);
Thomas Gleixner6935d1f2007-07-21 17:10:17 +02002192}
Andi Kleen2c8c0e62006-09-26 10:52:32 +02002193early_param("nolapic", setup_nolapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002194
Linus Torvalds2e7c2832007-03-23 11:32:31 -07002195static int __init parse_lapic_timer_c2_ok(char *arg)
2196{
2197 local_apic_timer_c2_ok = 1;
2198 return 0;
2199}
2200early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2201
Cyrill Gorcunov36fef092008-08-15 13:51:20 +02002202static int __init parse_disable_apic_timer(char *arg)
Thomas Gleixner6935d1f2007-07-21 17:10:17 +02002203{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002204 disable_apic_timer = 1;
Cyrill Gorcunov36fef092008-08-15 13:51:20 +02002205 return 0;
Thomas Gleixner6935d1f2007-07-21 17:10:17 +02002206}
Cyrill Gorcunov36fef092008-08-15 13:51:20 +02002207early_param("noapictimer", parse_disable_apic_timer);
2208
2209static int __init parse_nolapic_timer(char *arg)
2210{
2211 disable_apic_timer = 1;
2212 return 0;
2213}
2214early_param("nolapic_timer", parse_nolapic_timer);
Andi Kleen73dea472006-02-03 21:50:50 +01002215
Cyrill Gorcunov79af9be2008-08-18 20:46:00 +04002216static int __init apic_set_verbosity(char *arg)
2217{
2218 if (!arg) {
2219#ifdef CONFIG_X86_64
2220 skip_ioapic_setup = 0;
Cyrill Gorcunov79af9be2008-08-18 20:46:00 +04002221 return 0;
2222#endif
2223 return -EINVAL;
2224 }
2225
2226 if (strcmp("debug", arg) == 0)
2227 apic_verbosity = APIC_DEBUG;
2228 else if (strcmp("verbose", arg) == 0)
2229 apic_verbosity = APIC_VERBOSE;
2230 else {
Cyrill Gorcunovba21ebb2008-11-10 09:16:41 +01002231 pr_warning("APIC Verbosity level %s not recognised"
Cyrill Gorcunov79af9be2008-08-18 20:46:00 +04002232 " use apic=verbose or apic=debug\n", arg);
2233 return -EINVAL;
2234 }
2235
2236 return 0;
2237}
2238early_param("apic", apic_set_verbosity);
2239
Yinghai Lu1e934dd2008-02-22 13:37:26 -08002240static int __init lapic_insert_resource(void)
2241{
2242 if (!apic_phys)
2243 return -1;
2244
2245 /* Put local APIC into the resource map. */
2246 lapic_resource.start = apic_phys;
2247 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2248 insert_resource(&iomem_resource, &lapic_resource);
2249
2250 return 0;
2251}
2252
2253/*
2254 * need call insert after e820_reserve_resources()
2255 * that is using request_resource
2256 */
2257late_initcall(lapic_insert_resource);