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Tony Lindgren1dbae812005-11-10 14:26:51 +00001/*
2 * linux/arch/arm/mach-omap2/timer-gp.c
3 *
4 * OMAP2 GP timer support.
5 *
Kevin Hilman5a3a3882007-11-12 23:24:02 -08006 * Update to use new clocksource/clockevent layers
7 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
8 * Copyright (C) 2007 MontaVista Software, Inc.
9 *
10 * Original driver:
Tony Lindgren1dbae812005-11-10 14:26:51 +000011 * Copyright (C) 2005 Nokia Corporation
12 * Author: Paul Mundt <paul.mundt@nokia.com>
Jan Engelhardt96de0e22007-10-19 23:21:04 +020013 * Juha Yrjölä <juha.yrjola@nokia.com>
Timo Teras77900a22006-06-26 16:16:12 -070014 * OMAP Dual-mode timer framework support by Timo Teras
Tony Lindgren1dbae812005-11-10 14:26:51 +000015 *
16 * Some parts based off of TI's 24xx code:
17 *
18 * Copyright (C) 2004 Texas Instruments, Inc.
19 *
20 * Roughly modelled after the OMAP1 MPU timer code.
21 *
22 * This file is subject to the terms and conditions of the GNU General Public
23 * License. See the file "COPYING" in the main directory of this archive
24 * for more details.
25 */
26#include <linux/init.h>
27#include <linux/time.h>
28#include <linux/interrupt.h>
29#include <linux/err.h>
Russell Kingf8ce2542006-01-07 16:15:52 +000030#include <linux/clk.h>
Timo Teras77900a22006-06-26 16:16:12 -070031#include <linux/delay.h>
Dirk Behmee6687292006-12-06 17:14:00 -080032#include <linux/irq.h>
Kevin Hilman5a3a3882007-11-12 23:24:02 -080033#include <linux/clocksource.h>
34#include <linux/clockchips.h>
Russell Kingf8ce2542006-01-07 16:15:52 +000035
Tony Lindgren1dbae812005-11-10 14:26:51 +000036#include <asm/mach/time.h>
Timo Teras77900a22006-06-26 16:16:12 -070037#include <asm/arch/dmtimer.h>
Tony Lindgren1dbae812005-11-10 14:26:51 +000038
Timo Teras77900a22006-06-26 16:16:12 -070039static struct omap_dm_timer *gptimer;
Kevin Hilman5a3a3882007-11-12 23:24:02 -080040static struct clock_event_device clockevent_gpt;
Tony Lindgren1dbae812005-11-10 14:26:51 +000041
Linus Torvalds0cd61b62006-10-06 10:53:39 -070042static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
Tony Lindgren1dbae812005-11-10 14:26:51 +000043{
Kevin Hilman5a3a3882007-11-12 23:24:02 -080044 struct omap_dm_timer *gpt = (struct omap_dm_timer *)dev_id;
45 struct clock_event_device *evt = &clockevent_gpt;
Tony Lindgren1dbae812005-11-10 14:26:51 +000046
Kevin Hilman5a3a3882007-11-12 23:24:02 -080047 omap_dm_timer_write_status(gpt, OMAP_TIMER_INT_OVERFLOW);
48
49 evt->event_handler(evt);
Tony Lindgren1dbae812005-11-10 14:26:51 +000050 return IRQ_HANDLED;
51}
52
53static struct irqaction omap2_gp_timer_irq = {
54 .name = "gp timer",
Bernhard Walleb30faba2007-05-08 00:35:39 -070055 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
Tony Lindgren1dbae812005-11-10 14:26:51 +000056 .handler = omap2_gp_timer_interrupt,
57};
58
Kevin Hilman5a3a3882007-11-12 23:24:02 -080059static int omap2_gp_timer_set_next_event(unsigned long cycles,
60 struct clock_event_device *evt)
Tony Lindgren1dbae812005-11-10 14:26:51 +000061{
Kevin Hilman5a3a3882007-11-12 23:24:02 -080062 omap_dm_timer_set_load(gptimer, 0, 0xffffffff - cycles);
63 omap_dm_timer_start(gptimer);
Tony Lindgren1dbae812005-11-10 14:26:51 +000064
Kevin Hilman5a3a3882007-11-12 23:24:02 -080065 return 0;
66}
67
68static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
69 struct clock_event_device *evt)
70{
71 u32 period;
72
73 omap_dm_timer_stop(gptimer);
74
75 switch (mode) {
76 case CLOCK_EVT_MODE_PERIODIC:
77 period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
78 period -= 1;
79
80 omap_dm_timer_set_load(gptimer, 1, 0xffffffff - period);
81 omap_dm_timer_start(gptimer);
82 break;
83 case CLOCK_EVT_MODE_ONESHOT:
84 break;
85 case CLOCK_EVT_MODE_UNUSED:
86 case CLOCK_EVT_MODE_SHUTDOWN:
87 case CLOCK_EVT_MODE_RESUME:
88 break;
89 }
90}
91
92static struct clock_event_device clockevent_gpt = {
93 .name = "gp timer",
94 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
95 .shift = 32,
96 .set_next_event = omap2_gp_timer_set_next_event,
97 .set_mode = omap2_gp_timer_set_mode,
98};
99
100static void __init omap2_gp_clockevent_init(void)
101{
102 u32 tick_rate;
103
Timo Terase32f7ec2006-06-26 16:16:13 -0700104 gptimer = omap_dm_timer_request_specific(1);
Timo Teras77900a22006-06-26 16:16:12 -0700105 BUG_ON(gptimer == NULL);
Tony Lindgren1dbae812005-11-10 14:26:51 +0000106
Kevin Hilman5a3a3882007-11-12 23:24:02 -0800107#if defined(CONFIG_OMAP_32K_TIMER)
108 omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ);
109#else
Timo Teras77900a22006-06-26 16:16:12 -0700110 omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_SYS_CLK);
Kevin Hilman5a3a3882007-11-12 23:24:02 -0800111#endif
112 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer));
Tony Lindgren1dbae812005-11-10 14:26:51 +0000113
Kevin Hilman5a3a3882007-11-12 23:24:02 -0800114 omap2_gp_timer_irq.dev_id = (void *)gptimer;
Timo Teras77900a22006-06-26 16:16:12 -0700115 setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq);
Kevin Hilman5a3a3882007-11-12 23:24:02 -0800116 omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
117
118 clockevent_gpt.mult = div_sc(tick_rate, NSEC_PER_SEC,
119 clockevent_gpt.shift);
120 clockevent_gpt.max_delta_ns =
121 clockevent_delta2ns(0xffffffff, &clockevent_gpt);
122 clockevent_gpt.min_delta_ns =
123 clockevent_delta2ns(1, &clockevent_gpt);
124
125 clockevent_gpt.cpumask = cpumask_of_cpu(0);
126 clockevents_register_device(&clockevent_gpt);
127}
128
129#ifdef CONFIG_OMAP_32K_TIMER
130/*
131 * When 32k-timer is enabled, don't use GPTimer for clocksource
132 * instead, just leave default clocksource which uses the 32k
133 * sync counter. See clocksource setup in see plat-omap/common.c.
134 */
135
136static inline void __init omap2_gp_clocksource_init(void) {}
137#else
138/*
139 * clocksource
140 */
141static struct omap_dm_timer *gpt_clocksource;
142static cycle_t clocksource_read_cycles(void)
143{
144 return (cycle_t)omap_dm_timer_read_counter(gpt_clocksource);
145}
146
147static struct clocksource clocksource_gpt = {
148 .name = "gp timer",
149 .rating = 300,
150 .read = clocksource_read_cycles,
151 .mask = CLOCKSOURCE_MASK(32),
152 .shift = 24,
153 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
154};
155
156/* Setup free-running counter for clocksource */
157static void __init omap2_gp_clocksource_init(void)
158{
159 static struct omap_dm_timer *gpt;
160 u32 tick_rate, tick_period;
161 static char err1[] __initdata = KERN_ERR
162 "%s: failed to request dm-timer\n";
163 static char err2[] __initdata = KERN_ERR
164 "%s: can't register clocksource!\n";
165
166 gpt = omap_dm_timer_request();
167 if (!gpt)
168 printk(err1, clocksource_gpt.name);
169 gpt_clocksource = gpt;
170
171 omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK);
172 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt));
173 tick_period = (tick_rate / HZ) - 1;
174
175 omap_dm_timer_set_load(gpt, 1, 0);
176 omap_dm_timer_start(gpt);
177
178 clocksource_gpt.mult =
179 clocksource_khz2mult(tick_rate/1000, clocksource_gpt.shift);
180 if (clocksource_register(&clocksource_gpt))
181 printk(err2, clocksource_gpt.name);
182}
183#endif
184
185static void __init omap2_gp_timer_init(void)
186{
187 omap_dm_timer_init();
188
189 omap2_gp_clockevent_init();
190 omap2_gp_clocksource_init();
Tony Lindgren1dbae812005-11-10 14:26:51 +0000191}
192
193struct sys_timer omap_timer = {
194 .init = omap2_gp_timer_init,
195};