blob: 27130065d92a70679292ef316aaadf848772944c [file] [log] [blame]
Auke Kok9d5c8242008-01-24 02:22:38 -08001/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
Carolyn Wyborny74cfb2e2014-02-25 17:58:57 -08004 Copyright(c) 2007-2014 Intel Corporation.
Auke Kok9d5c8242008-01-24 02:22:38 -08005
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
Carolyn Wyborny74cfb2e2014-02-25 17:58:57 -080016 this program; if not, see <http://www.gnu.org/licenses/>.
Auke Kok9d5c8242008-01-24 02:22:38 -080017
18 The full GNU General Public License is included in this distribution in
19 the file called "COPYING".
20
21 Contact Information:
22 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24
25*******************************************************************************/
26
27
28/* Linux PRO/1000 Ethernet Driver main header file */
29
30#ifndef _IGB_H_
31#define _IGB_H_
32
33#include "e1000_mac.h"
34#include "e1000_82575.h"
35
Patrick Ohly38c845c2009-02-12 05:03:41 +000036#include <linux/clocksource.h>
Patrick Ohly33af6bc2009-02-12 05:03:43 +000037#include <linux/net_tstamp.h>
Richard Cochrand339b132012-03-16 10:55:32 +000038#include <linux/ptp_clock_kernel.h>
Jiri Pirkob2cb09b2011-07-21 03:27:27 +000039#include <linux/bitops.h>
40#include <linux/if_vlan.h>
Carolyn Wyborny441fc6f2012-12-07 03:00:30 +000041#include <linux/i2c.h>
42#include <linux/i2c-algo-bit.h>
Carolyn Wybornycd14ef52013-12-10 07:58:34 +000043#include <linux/pci.h>
Carolyn Wybornyf4c01e92014-03-12 03:58:22 +000044#include <linux/mdio.h>
Patrick Ohly38c845c2009-02-12 05:03:41 +000045
Auke Kok9d5c8242008-01-24 02:22:38 -080046struct igb_adapter;
47
Jeff Kirsherb980ac12013-02-23 07:29:56 +000048#define E1000_PCS_CFG_IGN_SD 1
Carolyn Wyborny3860a0b2012-11-22 02:49:22 +000049
Alexander Duyck0ba82992011-08-26 07:45:47 +000050/* Interrupt defines */
Jeff Kirsherb980ac12013-02-23 07:29:56 +000051#define IGB_START_ITR 648 /* ~6000 ints/sec */
52#define IGB_4K_ITR 980
53#define IGB_20K_ITR 196
54#define IGB_70K_ITR 56
Auke Kok9d5c8242008-01-24 02:22:38 -080055
Auke Kok9d5c8242008-01-24 02:22:38 -080056/* TX/RX descriptor defines */
Jeff Kirsherb980ac12013-02-23 07:29:56 +000057#define IGB_DEFAULT_TXD 256
58#define IGB_DEFAULT_TX_WORK 128
59#define IGB_MIN_TXD 80
60#define IGB_MAX_TXD 4096
Auke Kok9d5c8242008-01-24 02:22:38 -080061
Jeff Kirsherb980ac12013-02-23 07:29:56 +000062#define IGB_DEFAULT_RXD 256
63#define IGB_MIN_RXD 80
64#define IGB_MAX_RXD 4096
Auke Kok9d5c8242008-01-24 02:22:38 -080065
Jeff Kirsherb980ac12013-02-23 07:29:56 +000066#define IGB_DEFAULT_ITR 3 /* dynamic */
67#define IGB_MAX_ITR_USECS 10000
68#define IGB_MIN_ITR_USECS 10
69#define NON_Q_VECTORS 1
70#define MAX_Q_VECTORS 8
Carolyn Wybornycd14ef52013-12-10 07:58:34 +000071#define MAX_MSIX_ENTRIES 10
Auke Kok9d5c8242008-01-24 02:22:38 -080072
73/* Transmit and receive queues */
Jeff Kirsherb980ac12013-02-23 07:29:56 +000074#define IGB_MAX_RX_QUEUES 8
75#define IGB_MAX_RX_QUEUES_82575 4
76#define IGB_MAX_RX_QUEUES_I211 2
77#define IGB_MAX_TX_QUEUES 8
78#define IGB_MAX_VF_MC_ENTRIES 30
79#define IGB_MAX_VF_FUNCTIONS 8
80#define IGB_MAX_VFTA_ENTRIES 128
81#define IGB_82576_VF_DEV_ID 0x10CA
82#define IGB_I350_VF_DEV_ID 0x1520
Alexander Duyck4ae196d2009-02-19 20:40:07 -080083
Carolyn Wybornyd67974f2012-06-14 16:04:19 +000084/* NVM version defines */
Jeff Kirsherb980ac12013-02-23 07:29:56 +000085#define IGB_MAJOR_MASK 0xF000
86#define IGB_MINOR_MASK 0x0FF0
87#define IGB_BUILD_MASK 0x000F
88#define IGB_COMB_VER_MASK 0x00FF
89#define IGB_MAJOR_SHIFT 12
90#define IGB_MINOR_SHIFT 4
91#define IGB_COMB_VER_SHFT 8
92#define IGB_NVM_VER_INVALID 0xFFFF
93#define IGB_ETRACK_SHIFT 16
94#define NVM_ETRACK_WORD 0x0042
95#define NVM_COMB_VER_OFF 0x0083
96#define NVM_COMB_VER_PTR 0x003d
Carolyn Wybornyd67974f2012-06-14 16:04:19 +000097
Alexander Duyck4ae196d2009-02-19 20:40:07 -080098struct vf_data_storage {
99 unsigned char vf_mac_addresses[ETH_ALEN];
100 u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
101 u16 num_vf_mc_hashes;
Alexander Duyckae641bd2009-09-03 14:49:33 +0000102 u16 vlans_enabled;
Alexander Duyckf2ca0db2009-10-27 23:46:57 +0000103 u32 flags;
104 unsigned long last_nack;
Williams, Mitch A8151d292010-02-10 01:44:24 +0000105 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
106 u16 pf_qos;
Lior Levy17dc5662011-02-08 02:28:46 +0000107 u16 tx_rate;
Lior Levy70ea4782013-03-03 20:27:48 +0000108 bool spoofchk_enabled;
Alexander Duyck4ae196d2009-02-19 20:40:07 -0800109};
110
Alexander Duyckf2ca0db2009-10-27 23:46:57 +0000111#define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */
Alexander Duyck7d5753f2009-10-27 23:47:16 +0000112#define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */
113#define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */
Williams, Mitch A8151d292010-02-10 01:44:24 +0000114#define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */
Alexander Duyckf2ca0db2009-10-27 23:46:57 +0000115
Auke Kok9d5c8242008-01-24 02:22:38 -0800116/* RX descriptor control thresholds.
117 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
118 * descriptors available in its onboard memory.
119 * Setting this to 0 disables RX descriptor prefetch.
120 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
121 * available in host memory.
122 * If PTHRESH is 0, this should also be 0.
123 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
124 * descriptors until either it has this many to write back, or the
125 * ITR timer expires.
126 */
Carolyn Wybornyceb5f132013-04-18 22:21:30 +0000127#define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
Jeff Kirsherb980ac12013-02-23 07:29:56 +0000128#define IGB_RX_HTHRESH 8
Carolyn Wybornyceb5f132013-04-18 22:21:30 +0000129#define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
Jeff Kirsherb980ac12013-02-23 07:29:56 +0000130#define IGB_TX_HTHRESH 1
131#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \
Carolyn Wybornycd14ef52013-12-10 07:58:34 +0000132 (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 4)
Jeff Kirsherb980ac12013-02-23 07:29:56 +0000133#define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
Carolyn Wybornycd14ef52013-12-10 07:58:34 +0000134 (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 16)
Auke Kok9d5c8242008-01-24 02:22:38 -0800135
136/* this is the size past which hardware will drop packets when setting LPE=0 */
137#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
138
139/* Supported Rx Buffer Sizes */
Alexander Duyckde78d1f2012-09-25 00:31:12 +0000140#define IGB_RXBUFFER_256 256
141#define IGB_RXBUFFER_2048 2048
142#define IGB_RX_HDR_LEN IGB_RXBUFFER_256
143#define IGB_RX_BUFSZ IGB_RXBUFFER_2048
Auke Kok9d5c8242008-01-24 02:22:38 -0800144
Auke Kok9d5c8242008-01-24 02:22:38 -0800145/* How many Rx Buffers do we bundle into one write to the hardware ? */
Jeff Kirsherb980ac12013-02-23 07:29:56 +0000146#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
Auke Kok9d5c8242008-01-24 02:22:38 -0800147
Jeff Kirsherb980ac12013-02-23 07:29:56 +0000148#define AUTO_ALL_MODES 0
149#define IGB_EEPROM_APME 0x0400
Auke Kok9d5c8242008-01-24 02:22:38 -0800150
151#ifndef IGB_MASTER_SLAVE
152/* Switch to override PHY master/slave setting */
153#define IGB_MASTER_SLAVE e1000_ms_hw_default
154#endif
155
Jeff Kirsherb980ac12013-02-23 07:29:56 +0000156#define IGB_MNG_VLAN_NONE -1
Auke Kok9d5c8242008-01-24 02:22:38 -0800157
Alexander Duyck1d9daf42012-11-13 04:03:23 +0000158enum igb_tx_flags {
159 /* cmd_type flags */
160 IGB_TX_FLAGS_VLAN = 0x01,
161 IGB_TX_FLAGS_TSO = 0x02,
162 IGB_TX_FLAGS_TSTAMP = 0x04,
163
164 /* olinfo flags */
165 IGB_TX_FLAGS_IPV4 = 0x10,
166 IGB_TX_FLAGS_CSUM = 0x20,
167};
168
169/* VLAN info */
Jeff Kirsherb980ac12013-02-23 07:29:56 +0000170#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
Alexander Duyck2bbfebe2011-08-26 07:44:59 +0000171#define IGB_TX_FLAGS_VLAN_SHIFT 16
172
Jeff Kirsherb980ac12013-02-23 07:29:56 +0000173/* The largest size we can write to the descriptor is 65535. In order to
Alexander Duyck21ba6fe2013-02-09 04:27:48 +0000174 * maintain a power of two alignment we have to limit ourselves to 32K.
175 */
176#define IGB_MAX_TXD_PWR 15
177#define IGB_MAX_DATA_PER_TXD (1 << IGB_MAX_TXD_PWR)
178
179/* Tx Descriptors needed, worst case */
180#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGB_MAX_DATA_PER_TXD)
181#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
182
Akeem G. Abodunrinf69aa392013-04-11 06:36:35 +0000183/* EEPROM byte offsets */
184#define IGB_SFF_8472_SWAP 0x5C
185#define IGB_SFF_8472_COMP 0x5E
186
187/* Bitmasks */
188#define IGB_SFF_ADDRESSING_MODE 0x4
189#define IGB_SFF_8472_UNSUP 0x00
190
Auke Kok9d5c8242008-01-24 02:22:38 -0800191/* wrapper around a pointer to a socket buffer,
Jeff Kirsherb980ac12013-02-23 07:29:56 +0000192 * so a DMA handle can be stored along with the buffer
193 */
Alexander Duyck06034642011-08-26 07:44:22 +0000194struct igb_tx_buffer {
Alexander Duyck8542db02011-08-26 07:44:43 +0000195 union e1000_adv_tx_desc *next_to_watch;
Alexander Duyck06034642011-08-26 07:44:22 +0000196 unsigned long time_stamp;
Alexander Duyck06034642011-08-26 07:44:22 +0000197 struct sk_buff *skb;
198 unsigned int bytecount;
199 u16 gso_segs;
Alexander Duyck7af40ad92011-08-26 07:45:15 +0000200 __be16 protocol;
Alexander Duyckc9f14bf32012-09-18 01:56:27 +0000201 DEFINE_DMA_UNMAP_ADDR(dma);
202 DEFINE_DMA_UNMAP_LEN(len);
Alexander Duyckebe42d12011-08-26 07:45:09 +0000203 u32 tx_flags;
Alexander Duyck06034642011-08-26 07:44:22 +0000204};
205
206struct igb_rx_buffer {
Auke Kok9d5c8242008-01-24 02:22:38 -0800207 dma_addr_t dma;
Alexander Duyck06034642011-08-26 07:44:22 +0000208 struct page *page;
Alexander Duyck1a1c2252012-09-25 00:30:52 +0000209 unsigned int page_offset;
Auke Kok9d5c8242008-01-24 02:22:38 -0800210};
211
Jesper Dangaard Brouer8c0ab702009-05-26 13:50:31 +0000212struct igb_tx_queue_stats {
Auke Kok9d5c8242008-01-24 02:22:38 -0800213 u64 packets;
214 u64 bytes;
Alexander Duyck04a5fca2009-10-27 15:52:27 +0000215 u64 restart_queue;
Eric Dumazet12dcd862010-10-15 17:27:10 +0000216 u64 restart_queue2;
Auke Kok9d5c8242008-01-24 02:22:38 -0800217};
218
Jesper Dangaard Brouer8c0ab702009-05-26 13:50:31 +0000219struct igb_rx_queue_stats {
220 u64 packets;
221 u64 bytes;
222 u64 drops;
Alexander Duyck04a5fca2009-10-27 15:52:27 +0000223 u64 csum_err;
224 u64 alloc_failed;
Jesper Dangaard Brouer8c0ab702009-05-26 13:50:31 +0000225};
226
Alexander Duyck0ba82992011-08-26 07:45:47 +0000227struct igb_ring_container {
228 struct igb_ring *ring; /* pointer to linked list of rings */
229 unsigned int total_bytes; /* total bytes processed this int */
230 unsigned int total_packets; /* total packets processed this int */
231 u16 work_limit; /* total work allowed per interrupt */
232 u8 count; /* total number of rings in vector */
233 u8 itr; /* current ITR setting for ring */
234};
235
Alexander Duyck047e0032009-10-27 15:49:27 +0000236struct igb_ring {
Alexander Duyck238ac812011-08-26 07:43:48 +0000237 struct igb_q_vector *q_vector; /* backlink to q_vector */
238 struct net_device *netdev; /* back pointer to net_device */
239 struct device *dev; /* device pointer for dma mapping */
Alexander Duyck06034642011-08-26 07:44:22 +0000240 union { /* array of buffer info structs */
241 struct igb_tx_buffer *tx_buffer_info;
242 struct igb_rx_buffer *rx_buffer_info;
243 };
Alexander Duyck238ac812011-08-26 07:43:48 +0000244 void *desc; /* descriptor ring memory */
245 unsigned long flags; /* ring specific flags */
246 void __iomem *tail; /* pointer to ring tail register */
Alexander Duyck5536d212012-09-25 00:31:17 +0000247 dma_addr_t dma; /* phys address of the ring */
248 unsigned int size; /* length of desc. ring in bytes */
Alexander Duyck238ac812011-08-26 07:43:48 +0000249
250 u16 count; /* number of desc. in the ring */
251 u8 queue_index; /* logical index of the ring*/
252 u8 reg_idx; /* physical index of the ring */
Alexander Duyck238ac812011-08-26 07:43:48 +0000253
254 /* everything past this point are written often */
Alexander Duyck5536d212012-09-25 00:31:17 +0000255 u16 next_to_clean;
Auke Kok9d5c8242008-01-24 02:22:38 -0800256 u16 next_to_use;
Alexander Duyckcbc8e552012-09-25 00:31:02 +0000257 u16 next_to_alloc;
Auke Kok9d5c8242008-01-24 02:22:38 -0800258
Auke Kok9d5c8242008-01-24 02:22:38 -0800259 union {
260 /* TX */
261 struct {
Jesper Dangaard Brouer8c0ab702009-05-26 13:50:31 +0000262 struct igb_tx_queue_stats tx_stats;
Eric Dumazet12dcd862010-10-15 17:27:10 +0000263 struct u64_stats_sync tx_syncp;
264 struct u64_stats_sync tx_syncp2;
Auke Kok9d5c8242008-01-24 02:22:38 -0800265 };
266 /* RX */
267 struct {
Alexander Duyck1a1c2252012-09-25 00:30:52 +0000268 struct sk_buff *skb;
Jesper Dangaard Brouer8c0ab702009-05-26 13:50:31 +0000269 struct igb_rx_queue_stats rx_stats;
Eric Dumazet12dcd862010-10-15 17:27:10 +0000270 struct u64_stats_sync rx_syncp;
Auke Kok9d5c8242008-01-24 02:22:38 -0800271 };
272 };
Alexander Duyck5536d212012-09-25 00:31:17 +0000273} ____cacheline_internodealigned_in_smp;
274
275struct igb_q_vector {
276 struct igb_adapter *adapter; /* backlink */
277 int cpu; /* CPU for DCA */
278 u32 eims_value; /* EIMS mask value */
279
280 u16 itr_val;
281 u8 set_itr;
282 void __iomem *itr_register;
283
284 struct igb_ring_container rx, tx;
285
286 struct napi_struct napi;
287 struct rcu_head rcu; /* to avoid race with update stats on free */
288 char name[IFNAMSIZ + 9];
289
290 /* for dynamic allocation of rings associated with this q_vector */
291 struct igb_ring ring[0] ____cacheline_internodealigned_in_smp;
Auke Kok9d5c8242008-01-24 02:22:38 -0800292};
293
Alexander Duyck866cff02011-08-26 07:45:36 +0000294enum e1000_ring_flags_t {
Alexander Duyck866cff02011-08-26 07:45:36 +0000295 IGB_RING_FLAG_RX_SCTP_CSUM,
Alexander Duyck8be10e92011-08-26 07:47:11 +0000296 IGB_RING_FLAG_RX_LB_VLAN_BSWAP,
Alexander Duyck866cff02011-08-26 07:45:36 +0000297 IGB_RING_FLAG_TX_CTX_IDX,
298 IGB_RING_FLAG_TX_DETECT_HANG
299};
Alexander Duyck85ad76b2009-10-27 15:52:46 +0000300
Alexander Duycke032afc2011-08-26 07:44:48 +0000301#define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)
Alexander Duyck85ad76b2009-10-27 15:52:46 +0000302
Jeff Kirsherb980ac12013-02-23 07:29:56 +0000303#define IGB_RX_DESC(R, i) \
Alexander Duyck60136902011-08-26 07:44:05 +0000304 (&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
Jeff Kirsherb980ac12013-02-23 07:29:56 +0000305#define IGB_TX_DESC(R, i) \
Alexander Duyck60136902011-08-26 07:44:05 +0000306 (&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
Jeff Kirsherb980ac12013-02-23 07:29:56 +0000307#define IGB_TX_CTXTDESC(R, i) \
Alexander Duyck60136902011-08-26 07:44:05 +0000308 (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))
Auke Kok9d5c8242008-01-24 02:22:38 -0800309
Alexander Duyck3ceb90f2011-08-26 07:46:03 +0000310/* igb_test_staterr - tests bits within Rx descriptor status and error fields */
311static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc,
312 const u32 stat_err_bits)
313{
314 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
315}
316
Alexander Duyckd7ee5b32009-10-27 15:54:23 +0000317/* igb_desc_unused - calculate if we have unused descriptors */
318static inline int igb_desc_unused(struct igb_ring *ring)
319{
320 if (ring->next_to_clean > ring->next_to_use)
321 return ring->next_to_clean - ring->next_to_use - 1;
322
323 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
324}
325
Carolyn Wybornye4288932012-12-07 03:01:42 +0000326#ifdef CONFIG_IGB_HWMON
327
328#define IGB_HWMON_TYPE_LOC 0
329#define IGB_HWMON_TYPE_TEMP 1
330#define IGB_HWMON_TYPE_CAUTION 2
331#define IGB_HWMON_TYPE_MAX 3
332
333struct hwmon_attr {
334 struct device_attribute dev_attr;
335 struct e1000_hw *hw;
336 struct e1000_thermal_diode_data *sensor;
337 char name[12];
338 };
339
340struct hwmon_buff {
Guenter Roecke3670b82013-11-26 07:15:23 +0000341 struct attribute_group group;
342 const struct attribute_group *groups[2];
343 struct attribute *attrs[E1000_MAX_SENSORS * 4 + 1];
344 struct hwmon_attr hwmon_list[E1000_MAX_SENSORS * 4];
Carolyn Wybornye4288932012-12-07 03:01:42 +0000345 unsigned int n_hwmon;
346 };
347#endif
348
Laura Mihaela Vasilescuc342b392013-07-31 20:19:48 +0000349#define IGB_RETA_SIZE 128
350
Auke Kok9d5c8242008-01-24 02:22:38 -0800351/* board specific private data structure */
Auke Kok9d5c8242008-01-24 02:22:38 -0800352struct igb_adapter {
Jiri Pirkob2cb09b2011-07-21 03:27:27 +0000353 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
Alexander Duyck238ac812011-08-26 07:43:48 +0000354
355 struct net_device *netdev;
356
357 unsigned long state;
358 unsigned int flags;
359
360 unsigned int num_q_vectors;
Carolyn Wybornycd14ef52013-12-10 07:58:34 +0000361 struct msix_entry msix_entries[MAX_MSIX_ENTRIES];
Alexander Duyck2e5655e2009-10-27 23:50:38 +0000362
Auke Kok9d5c8242008-01-24 02:22:38 -0800363 /* Interrupt Throttle Rate */
Alexander Duyck4fc82ad2009-10-27 23:45:42 +0000364 u32 rx_itr_setting;
365 u32 tx_itr_setting;
Auke Kok9d5c8242008-01-24 02:22:38 -0800366 u16 tx_itr;
367 u16 rx_itr;
Auke Kok9d5c8242008-01-24 02:22:38 -0800368
Alexander Duyck238ac812011-08-26 07:43:48 +0000369 /* TX */
Alexander Duyck13fde972011-10-05 13:35:24 +0000370 u16 tx_work_limit;
Alexander Duyck238ac812011-08-26 07:43:48 +0000371 u32 tx_timeout_count;
372 int num_tx_queues;
373 struct igb_ring *tx_ring[16];
374
375 /* RX */
376 int num_rx_queues;
377 struct igb_ring *rx_ring[16];
378
379 u32 max_frame_size;
380 u32 min_frame_size;
381
382 struct timer_list watchdog_timer;
383 struct timer_list phy_info_timer;
384
385 u16 mng_vlan_id;
386 u32 bd_number;
387 u32 wol;
388 u32 en_mng_pt;
389 u16 link_speed;
390 u16 link_duplex;
391
Auke Kok9d5c8242008-01-24 02:22:38 -0800392 struct work_struct reset_task;
393 struct work_struct watchdog_task;
394 bool fc_autoneg;
395 u8 tx_timeout_factor;
396 struct timer_list blink_timer;
397 unsigned long led_status;
398
Auke Kok9d5c8242008-01-24 02:22:38 -0800399 /* OS defined structs */
Auke Kok9d5c8242008-01-24 02:22:38 -0800400 struct pci_dev *pdev;
Auke Kok9d5c8242008-01-24 02:22:38 -0800401
Eric Dumazet12dcd862010-10-15 17:27:10 +0000402 spinlock_t stats64_lock;
403 struct rtnl_link_stats64 stats64;
404
Auke Kok9d5c8242008-01-24 02:22:38 -0800405 /* structs defined in e1000_hw.h */
406 struct e1000_hw hw;
407 struct e1000_hw_stats stats;
408 struct e1000_phy_info phy_info;
409 struct e1000_phy_stats phy_stats;
410
411 u32 test_icr;
412 struct igb_ring test_tx_ring;
413 struct igb_ring test_rx_ring;
414
415 int msg_enable;
Alexander Duyck047e0032009-10-27 15:49:27 +0000416
Alexander Duyck047e0032009-10-27 15:49:27 +0000417 struct igb_q_vector *q_vector[MAX_Q_VECTORS];
Auke Kok9d5c8242008-01-24 02:22:38 -0800418 u32 eims_enable_mask;
PJ Waskiewicz844290e2008-06-27 11:00:39 -0700419 u32 eims_other;
Auke Kok9d5c8242008-01-24 02:22:38 -0800420
421 /* to not mess up cache alignment, always add to the bottom */
Alexander Duyck2e5655e2009-10-27 23:50:38 +0000422 u16 tx_ring_count;
423 u16 rx_ring_count;
Alexander Duyck1bfaf072009-02-19 20:39:23 -0800424 unsigned int vfs_allocated_count;
Alexander Duyck4ae196d2009-02-19 20:40:07 -0800425 struct vf_data_storage *vf_data;
Lior Levy17dc5662011-02-08 02:28:46 +0000426 int vf_rate_link_speed;
Alexander Duycka99955f2009-11-12 18:37:19 +0000427 u32 rss_queues;
Greg Rose13800462010-11-06 02:08:26 +0000428 u32 wvbr;
Carolyn Wyborny1128c752011-10-14 00:13:49 +0000429 u32 *shadow_vfta;
Richard Cochrand339b132012-03-16 10:55:32 +0000430
431 struct ptp_clock *ptp_clock;
Matthew Vicka79f4f82012-08-10 05:40:44 +0000432 struct ptp_clock_info ptp_caps;
433 struct delayed_work ptp_overflow_work;
Matthew Vick1f6e8172012-08-18 07:26:33 +0000434 struct work_struct ptp_tx_work;
435 struct sk_buff *ptp_tx_skb;
Jacob Keller6ab5f7b2014-01-11 07:20:06 +0000436 struct hwtstamp_config tstamp_config;
Matthew Vick428f1f72012-12-13 07:20:34 +0000437 unsigned long ptp_tx_start;
Matthew Vickfc580752012-12-13 07:20:35 +0000438 unsigned long last_rx_ptp_check;
Jakub Kicinski5499a962014-04-02 10:33:33 +0000439 unsigned long last_rx_timestamp;
Richard Cochrand339b132012-03-16 10:55:32 +0000440 spinlock_t tmreg_lock;
441 struct cyclecounter cc;
442 struct timecounter tc;
Matthew Vick428f1f72012-12-13 07:20:34 +0000443 u32 tx_hwtstamp_timeouts;
Matthew Vickfc580752012-12-13 07:20:35 +0000444 u32 rx_hwtstamp_cleared;
Matthew Vick3c89f6d2012-08-10 05:40:43 +0000445
Carolyn Wybornyd67974f2012-06-14 16:04:19 +0000446 char fw_version[32];
Carolyn Wybornye4288932012-12-07 03:01:42 +0000447#ifdef CONFIG_IGB_HWMON
Guenter Roecke3670b82013-11-26 07:15:23 +0000448 struct hwmon_buff *igb_hwmon_buff;
Carolyn Wybornye4288932012-12-07 03:01:42 +0000449 bool ets;
450#endif
Carolyn Wyborny441fc6f2012-12-07 03:00:30 +0000451 struct i2c_algo_bit_data i2c_algo;
452 struct i2c_adapter i2c_adap;
Carolyn Wyborny603e86f2013-02-20 07:40:55 +0000453 struct i2c_client *i2c_client;
Laura Mihaela Vasilescued12cc92013-07-31 20:19:54 +0000454 u32 rss_indir_tbl_init;
455 u8 rss_indir_tbl[IGB_RETA_SIZE];
Akeem G Abodunrinaa9b8cc2013-08-28 02:22:43 +0000456
457 unsigned long link_check_timeout;
Carolyn Wyborny56cec242013-10-17 05:36:26 +0000458 int copper_tries;
459 struct e1000_info ei;
Carolyn Wybornyf4c01e92014-03-12 03:58:22 +0000460 u16 eee_advert;
Auke Kok9d5c8242008-01-24 02:22:38 -0800461};
462
Akeem G. Abodunrin039454a2012-11-13 04:03:21 +0000463#define IGB_FLAG_HAS_MSI (1 << 0)
464#define IGB_FLAG_DCA_ENABLED (1 << 1)
465#define IGB_FLAG_QUAD_PORT_A (1 << 2)
466#define IGB_FLAG_QUEUE_PAIRS (1 << 3)
467#define IGB_FLAG_DMAC (1 << 4)
468#define IGB_FLAG_PTP (1 << 5)
469#define IGB_FLAG_RSS_FIELD_IPV4_UDP (1 << 6)
470#define IGB_FLAG_RSS_FIELD_IPV6_UDP (1 << 7)
Matthew Vick63d4a8f2012-11-09 05:49:54 +0000471#define IGB_FLAG_WOL_SUPPORTED (1 << 8)
Akeem G Abodunrinaa9b8cc2013-08-28 02:22:43 +0000472#define IGB_FLAG_NEED_LINK_UPDATE (1 << 9)
Carolyn Wyborny2bdfc4e2013-10-17 05:23:01 +0000473#define IGB_FLAG_MEDIA_RESET (1 << 10)
Carolyn Wyborny56cec242013-10-17 05:36:26 +0000474#define IGB_FLAG_MAS_CAPABLE (1 << 11)
475#define IGB_FLAG_MAS_ENABLE (1 << 12)
Carolyn Wybornycd14ef52013-12-10 07:58:34 +0000476#define IGB_FLAG_HAS_MSIX (1 << 13)
Carolyn Wybornyf4c01e92014-03-12 03:58:22 +0000477#define IGB_FLAG_EEE (1 << 14)
Carolyn Wyborny56cec242013-10-17 05:36:26 +0000478
479/* Media Auto Sense */
480#define IGB_MAS_ENABLE_0 0X0001
481#define IGB_MAS_ENABLE_1 0X0002
482#define IGB_MAS_ENABLE_2 0X0004
483#define IGB_MAS_ENABLE_3 0X0008
Carolyn Wyborny831ec0b2011-03-11 20:43:54 -0800484
485/* DMA Coalescing defines */
Jeff Kirsherb980ac12013-02-23 07:29:56 +0000486#define IGB_MIN_TXPBSIZE 20408
487#define IGB_TX_BUF_4096 4096
488#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */
Alexander Duyck7dfc16f2008-07-08 15:10:46 -0700489
Jeff Kirsherb980ac12013-02-23 07:29:56 +0000490#define IGB_82576_TSYNC_SHIFT 19
491#define IGB_TS_HDR_LEN 16
Auke Kok9d5c8242008-01-24 02:22:38 -0800492enum e1000_state_t {
493 __IGB_TESTING,
494 __IGB_RESETTING,
Jakub Kicinskied4420a2014-03-15 14:55:32 +0000495 __IGB_DOWN,
496 __IGB_PTP_TX_IN_PROGRESS,
Auke Kok9d5c8242008-01-24 02:22:38 -0800497};
498
499enum igb_boards {
500 board_82575,
501};
502
503extern char igb_driver_name[];
504extern char igb_driver_version[];
505
Joe Perches5ccc9212013-09-23 11:37:59 -0700506int igb_up(struct igb_adapter *);
507void igb_down(struct igb_adapter *);
508void igb_reinit_locked(struct igb_adapter *);
509void igb_reset(struct igb_adapter *);
Laura Mihaela Vasilescu907b7832013-10-01 04:33:56 -0700510int igb_reinit_queues(struct igb_adapter *);
Joe Perches5ccc9212013-09-23 11:37:59 -0700511void igb_write_rss_indir_tbl(struct igb_adapter *);
512int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
513int igb_setup_tx_resources(struct igb_ring *);
514int igb_setup_rx_resources(struct igb_ring *);
515void igb_free_tx_resources(struct igb_ring *);
516void igb_free_rx_resources(struct igb_ring *);
517void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
518void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
519void igb_setup_tctl(struct igb_adapter *);
520void igb_setup_rctl(struct igb_adapter *);
521netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *);
522void igb_unmap_and_free_tx_resource(struct igb_ring *, struct igb_tx_buffer *);
523void igb_alloc_rx_buffers(struct igb_ring *, u16);
524void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *);
525bool igb_has_link(struct igb_adapter *adapter);
526void igb_set_ethtool_ops(struct net_device *);
527void igb_power_up_link(struct igb_adapter *);
528void igb_set_fw_version(struct igb_adapter *);
529void igb_ptp_init(struct igb_adapter *adapter);
530void igb_ptp_stop(struct igb_adapter *adapter);
531void igb_ptp_reset(struct igb_adapter *adapter);
Joe Perches5ccc9212013-09-23 11:37:59 -0700532void igb_ptp_rx_hang(struct igb_adapter *adapter);
Joe Perches5ccc9212013-09-23 11:37:59 -0700533void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb);
534void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, unsigned char *va,
535 struct sk_buff *skb);
Jacob Keller6ab5f7b2014-01-11 07:20:06 +0000536int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr);
537int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr);
Carolyn Wybornye4288932012-12-07 03:01:42 +0000538#ifdef CONFIG_IGB_HWMON
Joe Perches5ccc9212013-09-23 11:37:59 -0700539void igb_sysfs_exit(struct igb_adapter *adapter);
540int igb_sysfs_init(struct igb_adapter *adapter);
Carolyn Wybornye4288932012-12-07 03:01:42 +0000541#endif
Alexander Duyckf5f4cf02008-11-21 21:30:24 -0800542static inline s32 igb_reset_phy(struct e1000_hw *hw)
543{
Alexander Duycka8d2a0c2009-02-06 23:17:26 +0000544 if (hw->phy.ops.reset)
545 return hw->phy.ops.reset(hw);
Alexander Duyckf5f4cf02008-11-21 21:30:24 -0800546
547 return 0;
548}
549
550static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
551{
Alexander Duycka8d2a0c2009-02-06 23:17:26 +0000552 if (hw->phy.ops.read_reg)
553 return hw->phy.ops.read_reg(hw, offset, data);
Alexander Duyckf5f4cf02008-11-21 21:30:24 -0800554
555 return 0;
556}
557
558static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
559{
Alexander Duycka8d2a0c2009-02-06 23:17:26 +0000560 if (hw->phy.ops.write_reg)
561 return hw->phy.ops.write_reg(hw, offset, data);
Alexander Duyckf5f4cf02008-11-21 21:30:24 -0800562
563 return 0;
564}
565
566static inline s32 igb_get_phy_info(struct e1000_hw *hw)
567{
568 if (hw->phy.ops.get_phy_info)
569 return hw->phy.ops.get_phy_info(hw);
570
571 return 0;
572}
573
Eric Dumazetbdbc0632012-01-04 20:23:36 +0000574static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring)
575{
576 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
577}
578
Auke Kok9d5c8242008-01-24 02:22:38 -0800579#endif /* _IGB_H_ */