Brian Swetland | 600f7cf | 2008-09-09 11:04:14 -0700 | [diff] [blame] | 1 | /* arch/arm/mach-msm/clock-7x01a.c |
| 2 | * |
| 3 | * Clock tables for MSM7X01A |
| 4 | * |
| 5 | * Copyright (C) 2007 Google, Inc. |
| 6 | * Copyright (c) 2007 QUALCOMM Incorporated |
| 7 | * |
| 8 | * This software is licensed under the terms of the GNU General Public |
| 9 | * License version 2, as published by the Free Software Foundation, and |
| 10 | * may be copied, distributed, and modified under those terms. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | */ |
| 18 | |
| 19 | #include <linux/kernel.h> |
| 20 | #include <linux/platform_device.h> |
| 21 | |
| 22 | #include "clock.h" |
| 23 | #include "devices.h" |
| 24 | |
| 25 | /* clock IDs used by the modem processor */ |
| 26 | |
| 27 | #define ACPU_CLK 0 /* Applications processor clock */ |
| 28 | #define ADM_CLK 1 /* Applications data mover clock */ |
| 29 | #define ADSP_CLK 2 /* ADSP clock */ |
| 30 | #define EBI1_CLK 3 /* External bus interface 1 clock */ |
| 31 | #define EBI2_CLK 4 /* External bus interface 2 clock */ |
| 32 | #define ECODEC_CLK 5 /* External CODEC clock */ |
| 33 | #define EMDH_CLK 6 /* External MDDI host clock */ |
| 34 | #define GP_CLK 7 /* General purpose clock */ |
| 35 | #define GRP_CLK 8 /* Graphics clock */ |
| 36 | #define I2C_CLK 9 /* I2C clock */ |
| 37 | #define ICODEC_RX_CLK 10 /* Internal CODEX RX clock */ |
| 38 | #define ICODEC_TX_CLK 11 /* Internal CODEX TX clock */ |
| 39 | #define IMEM_CLK 12 /* Internal graphics memory clock */ |
| 40 | #define MDC_CLK 13 /* MDDI client clock */ |
| 41 | #define MDP_CLK 14 /* Mobile display processor clock */ |
| 42 | #define PBUS_CLK 15 /* Peripheral bus clock */ |
| 43 | #define PCM_CLK 16 /* PCM clock */ |
| 44 | #define PMDH_CLK 17 /* Primary MDDI host clock */ |
| 45 | #define SDAC_CLK 18 /* Stereo DAC clock */ |
| 46 | #define SDC1_CLK 19 /* Secure Digital Card clocks */ |
| 47 | #define SDC1_PCLK 20 |
| 48 | #define SDC2_CLK 21 |
| 49 | #define SDC2_PCLK 22 |
| 50 | #define SDC3_CLK 23 |
| 51 | #define SDC3_PCLK 24 |
| 52 | #define SDC4_CLK 25 |
| 53 | #define SDC4_PCLK 26 |
| 54 | #define TSIF_CLK 27 /* Transport Stream Interface clocks */ |
| 55 | #define TSIF_REF_CLK 28 |
| 56 | #define TV_DAC_CLK 29 /* TV clocks */ |
| 57 | #define TV_ENC_CLK 30 |
| 58 | #define UART1_CLK 31 /* UART clocks */ |
| 59 | #define UART2_CLK 32 |
| 60 | #define UART3_CLK 33 |
| 61 | #define UART1DM_CLK 34 |
| 62 | #define UART2DM_CLK 35 |
| 63 | #define USB_HS_CLK 36 /* High speed USB core clock */ |
| 64 | #define USB_HS_PCLK 37 /* High speed USB pbus clock */ |
| 65 | #define USB_OTG_CLK 38 /* Full speed USB clock */ |
| 66 | #define VDC_CLK 39 /* Video controller clock */ |
| 67 | #define VFE_CLK 40 /* Camera / Video Front End clock */ |
| 68 | #define VFE_MDC_CLK 41 /* VFE MDDI client clock */ |
| 69 | |
| 70 | #define NR_CLKS 42 |
| 71 | |
| 72 | #define CLOCK(clk_name, clk_id, clk_dev, clk_flags) { \ |
| 73 | .name = clk_name, \ |
| 74 | .id = clk_id, \ |
| 75 | .flags = clk_flags, \ |
| 76 | .dev = clk_dev, \ |
| 77 | } |
| 78 | |
| 79 | #define OFF CLKFLAG_AUTO_OFF |
| 80 | #define MINMAX CLKFLAG_USE_MIN_MAX_TO_SET |
| 81 | |
| 82 | struct clk msm_clocks[] = { |
| 83 | CLOCK("adm_clk", ADM_CLK, NULL, 0), |
| 84 | CLOCK("adsp_clk", ADSP_CLK, NULL, 0), |
| 85 | CLOCK("ebi1_clk", EBI1_CLK, NULL, 0), |
| 86 | CLOCK("ebi2_clk", EBI2_CLK, NULL, 0), |
| 87 | CLOCK("ecodec_clk", ECODEC_CLK, NULL, 0), |
| 88 | CLOCK("emdh_clk", EMDH_CLK, NULL, OFF), |
| 89 | CLOCK("gp_clk", GP_CLK, NULL, 0), |
| 90 | CLOCK("grp_clk", GRP_CLK, NULL, OFF), |
| 91 | CLOCK("i2c_clk", I2C_CLK, &msm_device_i2c.dev, 0), |
| 92 | CLOCK("icodec_rx_clk", ICODEC_RX_CLK, NULL, 0), |
| 93 | CLOCK("icodec_tx_clk", ICODEC_TX_CLK, NULL, 0), |
| 94 | CLOCK("imem_clk", IMEM_CLK, NULL, OFF), |
| 95 | CLOCK("mdc_clk", MDC_CLK, NULL, 0), |
| 96 | CLOCK("mdp_clk", MDP_CLK, NULL, OFF), |
| 97 | CLOCK("pbus_clk", PBUS_CLK, NULL, 0), |
| 98 | CLOCK("pcm_clk", PCM_CLK, NULL, 0), |
| 99 | CLOCK("pmdh_clk", PMDH_CLK, NULL, OFF | MINMAX), |
| 100 | CLOCK("sdac_clk", SDAC_CLK, NULL, OFF), |
| 101 | CLOCK("sdc_clk", SDC1_CLK, &msm_device_sdc1.dev, OFF), |
| 102 | CLOCK("sdc_pclk", SDC1_PCLK, &msm_device_sdc1.dev, OFF), |
| 103 | CLOCK("sdc_clk", SDC2_CLK, &msm_device_sdc2.dev, OFF), |
| 104 | CLOCK("sdc_pclk", SDC2_PCLK, &msm_device_sdc2.dev, OFF), |
| 105 | CLOCK("sdc_clk", SDC3_CLK, &msm_device_sdc3.dev, OFF), |
| 106 | CLOCK("sdc_pclk", SDC3_PCLK, &msm_device_sdc3.dev, OFF), |
| 107 | CLOCK("sdc_clk", SDC4_CLK, &msm_device_sdc4.dev, OFF), |
| 108 | CLOCK("sdc_pclk", SDC4_PCLK, &msm_device_sdc4.dev, OFF), |
| 109 | CLOCK("tsif_clk", TSIF_CLK, NULL, 0), |
| 110 | CLOCK("tsif_ref_clk", TSIF_REF_CLK, NULL, 0), |
| 111 | CLOCK("tv_dac_clk", TV_DAC_CLK, NULL, 0), |
| 112 | CLOCK("tv_enc_clk", TV_ENC_CLK, NULL, 0), |
| 113 | CLOCK("uart_clk", UART1_CLK, &msm_device_uart1.dev, OFF), |
| 114 | CLOCK("uart_clk", UART2_CLK, &msm_device_uart2.dev, 0), |
| 115 | CLOCK("uart_clk", UART3_CLK, &msm_device_uart3.dev, OFF), |
| 116 | CLOCK("uart1dm_clk", UART1DM_CLK, NULL, OFF), |
| 117 | CLOCK("uart2dm_clk", UART2DM_CLK, NULL, 0), |
| 118 | CLOCK("usb_hs_clk", USB_HS_CLK, &msm_device_hsusb.dev, OFF), |
| 119 | CLOCK("usb_hs_pclk", USB_HS_PCLK, &msm_device_hsusb.dev, OFF), |
| 120 | CLOCK("usb_otg_clk", USB_OTG_CLK, NULL, 0), |
| 121 | CLOCK("vdc_clk", VDC_CLK, NULL, OFF | MINMAX), |
| 122 | CLOCK("vfe_clk", VFE_CLK, NULL, OFF), |
| 123 | CLOCK("vfe_mdc_clk", VFE_MDC_CLK, NULL, OFF), |
| 124 | }; |
| 125 | |
| 126 | unsigned msm_num_clocks = ARRAY_SIZE(msm_clocks); |