| /* |
| * Xtensa Special Register symbolic names |
| */ |
| |
| /* $Id: specreg.h,v 1.2 2003/03/07 19:15:18 joetaylor Exp $ */ |
| |
| /* |
| * Copyright (c) 2003 Tensilica, Inc. All Rights Reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of version 2.1 of the GNU Lesser General Public |
| * License as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it would be useful, but |
| * WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
| * |
| * Further, this software is distributed without any warranty that it is |
| * free of the rightful claim of any third person regarding infringement |
| * or the like. Any license provided herein, whether implied or |
| * otherwise, applies only to this software file. Patent licenses, if |
| * any, provided herein do not apply to combinations of this program with |
| * other software, or any other product whatsoever. |
| * |
| * You should have received a copy of the GNU Lesser General Public |
| * License along with this program; if not, write the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, |
| * USA. |
| */ |
| |
| #ifndef XTENSA_SPECREG_H |
| #define XTENSA_SPECREG_H |
| |
| /* Include these special register bitfield definitions, for historical reasons: */ |
| #include <xtensa/corebits.h> |
| |
| |
| /* Special registers: */ |
| #define LBEG 0 |
| #define LEND 1 |
| #define LCOUNT 2 |
| #define SAR 3 |
| #define WINDOWBASE 72 |
| #define WINDOWSTART 73 |
| #define PTEVADDR 83 |
| #define RASID 90 |
| #define ITLBCFG 91 |
| #define DTLBCFG 92 |
| #define IBREAKENABLE 96 |
| #define DDR 104 |
| #define IBREAKA_0 128 |
| #define IBREAKA_1 129 |
| #define DBREAKA_0 144 |
| #define DBREAKA_1 145 |
| #define DBREAKC_0 160 |
| #define DBREAKC_1 161 |
| #define EPC_1 177 |
| #define EPC_2 178 |
| #define EPC_3 179 |
| #define EPC_4 180 |
| #define DEPC 192 |
| #define EPS_2 194 |
| #define EPS_3 195 |
| #define EPS_4 196 |
| #define EXCSAVE_1 209 |
| #define EXCSAVE_2 210 |
| #define EXCSAVE_3 211 |
| #define EXCSAVE_4 212 |
| #define INTERRUPT 226 |
| #define INTENABLE 228 |
| #define PS 230 |
| #define EXCCAUSE 232 |
| #define DEBUGCAUSE 233 |
| #define CCOUNT 234 |
| #define ICOUNT 236 |
| #define ICOUNTLEVEL 237 |
| #define EXCVADDR 238 |
| #define CCOMPARE_0 240 |
| #define CCOMPARE_1 241 |
| #define CCOMPARE_2 242 |
| #define MISC_REG_0 244 |
| #define MISC_REG_1 245 |
| |
| /* Special cases (bases of special register series): */ |
| #define IBREAKA 128 |
| #define DBREAKA 144 |
| #define DBREAKC 160 |
| #define EPC 176 |
| #define EPS 192 |
| #define EXCSAVE 208 |
| #define CCOMPARE 240 |
| |
| /* Special names for read-only and write-only interrupt registers: */ |
| #define INTREAD 226 |
| #define INTSET 226 |
| #define INTCLEAR 227 |
| |
| #endif /* XTENSA_SPECREG_H */ |
| |
