| /include/ "skeleton.dtsi" |
| |
| / { |
| compatible = "nvidia,tegra114"; |
| interrupt-parent = <&gic>; |
| |
| aliases { |
| serial0 = &uarta; |
| serial1 = &uartb; |
| serial2 = &uartc; |
| serial3 = &uartd; |
| }; |
| |
| gic: interrupt-controller { |
| compatible = "arm,cortex-a15-gic"; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| reg = <0x50041000 0x1000>, |
| <0x50042000 0x1000>, |
| <0x50044000 0x2000>, |
| <0x50046000 0x2000>; |
| interrupts = <1 9 0xf04>; |
| }; |
| |
| timer@60005000 { |
| compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer"; |
| reg = <0x60005000 0x400>; |
| interrupts = <0 0 0x04 |
| 0 1 0x04 |
| 0 41 0x04 |
| 0 42 0x04 |
| 0 121 0x04 |
| 0 122 0x04>; |
| clocks = <&tegra_car 5>; |
| }; |
| |
| tegra_car: clock { |
| compatible = "nvidia,tegra114-car"; |
| reg = <0x60006000 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| apbdma: dma { |
| compatible = "nvidia,tegra114-apbdma"; |
| reg = <0x6000a000 0x1400>; |
| interrupts = <0 104 0x04 |
| 0 105 0x04 |
| 0 106 0x04 |
| 0 107 0x04 |
| 0 108 0x04 |
| 0 109 0x04 |
| 0 110 0x04 |
| 0 111 0x04 |
| 0 112 0x04 |
| 0 113 0x04 |
| 0 114 0x04 |
| 0 115 0x04 |
| 0 116 0x04 |
| 0 117 0x04 |
| 0 118 0x04 |
| 0 119 0x04 |
| 0 128 0x04 |
| 0 129 0x04 |
| 0 130 0x04 |
| 0 131 0x04 |
| 0 132 0x04 |
| 0 133 0x04 |
| 0 134 0x04 |
| 0 135 0x04 |
| 0 136 0x04 |
| 0 137 0x04 |
| 0 138 0x04 |
| 0 139 0x04 |
| 0 140 0x04 |
| 0 141 0x04 |
| 0 142 0x04 |
| 0 143 0x04>; |
| clocks = <&tegra_car 34>; |
| }; |
| |
| ahb: ahb { |
| compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; |
| reg = <0x6000c004 0x14c>; |
| }; |
| |
| gpio: gpio { |
| compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; |
| reg = <0x6000d000 0x1000>; |
| interrupts = <0 32 0x04 |
| 0 33 0x04 |
| 0 34 0x04 |
| 0 35 0x04 |
| 0 55 0x04 |
| 0 87 0x04 |
| 0 89 0x04 |
| 0 125 0x04>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| }; |
| |
| pinmux: pinmux { |
| compatible = "nvidia,tegra114-pinmux"; |
| reg = <0x70000868 0x148 /* Pad control registers */ |
| 0x70003000 0x40c>; /* Mux registers */ |
| }; |
| |
| /* |
| * There are two serial driver i.e. 8250 based simple serial |
| * driver and APB DMA based serial driver for higher baudrate |
| * and performace. To enable the 8250 based driver, the compatible |
| * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable |
| * the APB DMA based serial driver, the comptible is |
| * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart". |
| */ |
| uarta: serial@70006000 { |
| compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
| reg = <0x70006000 0x40>; |
| reg-shift = <2>; |
| interrupts = <0 36 0x04>; |
| nvidia,dma-request-selector = <&apbdma 8>; |
| status = "disabled"; |
| clocks = <&tegra_car 6>; |
| }; |
| |
| uartb: serial@70006040 { |
| compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
| reg = <0x70006040 0x40>; |
| reg-shift = <2>; |
| interrupts = <0 37 0x04>; |
| nvidia,dma-request-selector = <&apbdma 9>; |
| status = "disabled"; |
| clocks = <&tegra_car 192>; |
| }; |
| |
| uartc: serial@70006200 { |
| compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
| reg = <0x70006200 0x100>; |
| reg-shift = <2>; |
| interrupts = <0 46 0x04>; |
| nvidia,dma-request-selector = <&apbdma 10>; |
| status = "disabled"; |
| clocks = <&tegra_car 55>; |
| }; |
| |
| uartd: serial@70006300 { |
| compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
| reg = <0x70006300 0x100>; |
| reg-shift = <2>; |
| interrupts = <0 90 0x04>; |
| nvidia,dma-request-selector = <&apbdma 19>; |
| status = "disabled"; |
| clocks = <&tegra_car 65>; |
| }; |
| |
| pwm: pwm { |
| compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; |
| reg = <0x7000a000 0x100>; |
| #pwm-cells = <2>; |
| clocks = <&tegra_car 17>; |
| status = "disabled"; |
| }; |
| |
| i2c@7000c000 { |
| compatible = "nvidia,tegra114-i2c"; |
| reg = <0x7000c000 0x100>; |
| interrupts = <0 38 0x04>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 12>; |
| clock-names = "div-clk"; |
| status = "disabled"; |
| }; |
| |
| i2c@7000c400 { |
| compatible = "nvidia,tegra114-i2c"; |
| reg = <0x7000c400 0x100>; |
| interrupts = <0 84 0x04>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 54>; |
| clock-names = "div-clk"; |
| status = "disabled"; |
| }; |
| |
| i2c@7000c500 { |
| compatible = "nvidia,tegra114-i2c"; |
| reg = <0x7000c500 0x100>; |
| interrupts = <0 92 0x04>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 67>; |
| clock-names = "div-clk"; |
| status = "disabled"; |
| }; |
| |
| i2c@7000c700 { |
| compatible = "nvidia,tegra114-i2c"; |
| reg = <0x7000c700 0x100>; |
| interrupts = <0 120 0x04>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 103>; |
| clock-names = "div-clk"; |
| status = "disabled"; |
| }; |
| |
| i2c@7000d000 { |
| compatible = "nvidia,tegra114-i2c"; |
| reg = <0x7000d000 0x100>; |
| interrupts = <0 53 0x04>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 47>; |
| clock-names = "div-clk"; |
| status = "disabled"; |
| }; |
| |
| spi@7000d400 { |
| compatible = "nvidia,tegra114-spi"; |
| reg = <0x7000d400 0x200>; |
| interrupts = <0 59 0x04>; |
| nvidia,dma-request-selector = <&apbdma 15>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 41>; |
| clock-names = "spi"; |
| status = "disabled"; |
| }; |
| |
| spi@7000d600 { |
| compatible = "nvidia,tegra114-spi"; |
| reg = <0x7000d600 0x200>; |
| interrupts = <0 82 0x04>; |
| nvidia,dma-request-selector = <&apbdma 16>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 44>; |
| clock-names = "spi"; |
| status = "disabled"; |
| }; |
| |
| spi@7000d800 { |
| compatible = "nvidia,tegra114-spi"; |
| reg = <0x7000d800 0x200>; |
| interrupts = <0 83 0x04>; |
| nvidia,dma-request-selector = <&apbdma 17>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 46>; |
| clock-names = "spi"; |
| status = "disabled"; |
| }; |
| |
| spi@7000da00 { |
| compatible = "nvidia,tegra114-spi"; |
| reg = <0x7000da00 0x200>; |
| interrupts = <0 93 0x04>; |
| nvidia,dma-request-selector = <&apbdma 18>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 68>; |
| clock-names = "spi"; |
| status = "disabled"; |
| }; |
| |
| spi@7000dc00 { |
| compatible = "nvidia,tegra114-spi"; |
| reg = <0x7000dc00 0x200>; |
| interrupts = <0 94 0x04>; |
| nvidia,dma-request-selector = <&apbdma 27>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 104>; |
| clock-names = "spi"; |
| status = "disabled"; |
| }; |
| |
| spi@7000de00 { |
| compatible = "nvidia,tegra114-spi"; |
| reg = <0x7000de00 0x200>; |
| interrupts = <0 79 0x04>; |
| nvidia,dma-request-selector = <&apbdma 28>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&tegra_car 105>; |
| clock-names = "spi"; |
| status = "disabled"; |
| }; |
| |
| rtc { |
| compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; |
| reg = <0x7000e000 0x100>; |
| interrupts = <0 2 0x04>; |
| clocks = <&tegra_car 4>; |
| }; |
| |
| kbc { |
| compatible = "nvidia,tegra114-kbc"; |
| reg = <0x7000e200 0x100>; |
| interrupts = <0 85 0x04>; |
| clocks = <&tegra_car 36>; |
| status = "disabled"; |
| }; |
| |
| pmc { |
| compatible = "nvidia,tegra114-pmc"; |
| reg = <0x7000e400 0x400>; |
| clocks = <&tegra_car 261>, <&clk32k_in>; |
| clock-names = "pclk", "clk32k_in"; |
| }; |
| |
| iommu { |
| compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu"; |
| reg = <0x7000f010 0x02c |
| 0x7000f1f0 0x010 |
| 0x7000f228 0x074>; |
| nvidia,#asids = <4>; |
| dma-window = <0 0x40000000>; |
| nvidia,swgroups = <0x18659fe>; |
| nvidia,ahb = <&ahb>; |
| }; |
| |
| sdhci@78000000 { |
| compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; |
| reg = <0x78000000 0x200>; |
| interrupts = <0 14 0x04>; |
| clocks = <&tegra_car 14>; |
| status = "disable"; |
| }; |
| |
| sdhci@78000200 { |
| compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; |
| reg = <0x78000200 0x200>; |
| interrupts = <0 15 0x04>; |
| clocks = <&tegra_car 9>; |
| status = "disable"; |
| }; |
| |
| sdhci@78000400 { |
| compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; |
| reg = <0x78000400 0x200>; |
| interrupts = <0 19 0x04>; |
| clocks = <&tegra_car 69>; |
| status = "disable"; |
| }; |
| |
| sdhci@78000600 { |
| compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; |
| reg = <0x78000600 0x200>; |
| interrupts = <0 31 0x04>; |
| clocks = <&tegra_car 15>; |
| status = "disable"; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a15"; |
| reg = <0>; |
| }; |
| |
| cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a15"; |
| reg = <1>; |
| }; |
| |
| cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a15"; |
| reg = <2>; |
| }; |
| |
| cpu@3 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a15"; |
| reg = <3>; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv7-timer"; |
| interrupts = <1 13 0xf08>, |
| <1 14 0xf08>, |
| <1 11 0xf08>, |
| <1 10 0xf08>; |
| }; |
| }; |
