| NVIDIA Tegra20 timer | |
| The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free | |
| running counter. The first two channels may also trigger a watchdog reset. | |
| Required properties: | |
| - compatible : should be "nvidia,tegra20-timer". | |
| - reg : Specifies base physical address and size of the registers. | |
| - interrupts : A list of 4 interrupts; one per timer channel. | |
| Example: | |
| timer { | |
| compatible = "nvidia,tegra20-timer"; | |
| reg = <0x60005000 0x60>; | |
| interrupts = <0 0 0x04 | |
| 0 1 0x04 | |
| 0 41 0x04 | |
| 0 42 0x04>; | |
| }; |