/ { | |
testcase-data { | |
interrupts { | |
#address-cells = <1>; | |
#size-cells = <1>; | |
test_intc0: intc0 { | |
interrupt-controller; | |
#interrupt-cells = <1>; | |
}; | |
test_intc1: intc1 { | |
interrupt-controller; | |
#interrupt-cells = <3>; | |
}; | |
test_intc2: intc2 { | |
interrupt-controller; | |
#interrupt-cells = <2>; | |
}; | |
test_intmap0: intmap0 { | |
#interrupt-cells = <1>; | |
#address-cells = <0>; | |
interrupt-map = <1 &test_intc0 9>, | |
<2 &test_intc1 10 11 12>, | |
<3 &test_intc2 13 14>, | |
<4 &test_intc2 15 16>; | |
}; | |
test_intmap1: intmap1 { | |
#interrupt-cells = <2>; | |
interrupt-map = <0x5000 1 2 &test_intc0 15>; | |
}; | |
interrupts0 { | |
interrupt-parent = <&test_intc0>; | |
interrupts = <1>, <2>, <3>, <4>; | |
}; | |
interrupts1 { | |
interrupt-parent = <&test_intmap0>; | |
interrupts = <1>, <2>, <3>, <4>; | |
}; | |
interrupts-extended0 { | |
reg = <0x5000 0x100>; | |
interrupts-extended = <&test_intc0 1>, | |
<&test_intc1 2 3 4>, | |
<&test_intc2 5 6>, | |
<&test_intmap0 1>, | |
<&test_intmap0 2>, | |
<&test_intmap0 3>, | |
<&test_intmap1 1 2>; | |
}; | |
}; | |
}; | |
}; |