| /* |
| * Carsten Langgaard, carstenl@mips.com |
| * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. |
| * |
| * ######################################################################## |
| * |
| * This program is free software; you can distribute it and/or modify it |
| * under the terms of the GNU General Public License (Version 2) as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope it will be useful, but WITHOUT |
| * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| * for more details. |
| * |
| * You should have received a copy of the GNU General Public License along |
| * with this program; if not, write to the Free Software Foundation, Inc., |
| * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. |
| * |
| * ######################################################################## |
| * |
| * Defines for the Malta interrupt controller. |
| * |
| */ |
| #ifndef _MIPS_MALTAINT_H |
| #define _MIPS_MALTAINT_H |
| |
| #include <irq.h> |
| |
| /* |
| * Interrupts 0..15 are used for Malta ISA compatible interrupts |
| */ |
| #define MALTA_INT_BASE 0 |
| |
| /* |
| * Interrupts 16..23 are used for Malta CPU interrupts (nonEIC mode) |
| */ |
| #define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE |
| |
| /* CPU interrupt offsets */ |
| #define MIPSCPU_INT_SW0 0 |
| #define MIPSCPU_INT_SW1 1 |
| #define MIPSCPU_INT_MB0 2 |
| #define MIPSCPU_INT_I8259A MIPSCPU_INT_MB0 |
| #define MIPSCPU_INT_MB1 3 |
| #define MIPSCPU_INT_SMI MIPSCPU_INT_MB1 |
| #define MIPSCPU_INT_MB2 4 |
| #define MIPSCPU_INT_MB3 5 |
| #define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3 |
| #define MIPSCPU_INT_MB4 6 |
| #define MIPSCPU_INT_CORELO MIPSCPU_INT_MB4 |
| #define MIPSCPU_INT_CPUCTR 7 |
| |
| /* |
| * Interrupts 64..127 are used for Soc-it Classic interrupts |
| */ |
| #define MSC01C_INT_BASE 64 |
| |
| /* SOC-it Classic interrupt offsets */ |
| #define MSC01C_INT_TMR 0 |
| #define MSC01C_INT_PCI 1 |
| |
| /* |
| * Interrupts 64..127 are used for Soc-it EIC interrupts |
| */ |
| #define MSC01E_INT_BASE 64 |
| |
| /* SOC-it EIC interrupt offsets */ |
| #define MSC01E_INT_SW0 1 |
| #define MSC01E_INT_SW1 2 |
| #define MSC01E_INT_MB0 3 |
| #define MSC01E_INT_I8259A MSC01E_INT_MB0 |
| #define MSC01E_INT_MB1 4 |
| #define MSC01E_INT_SMI MSC01E_INT_MB1 |
| #define MSC01E_INT_MB2 5 |
| #define MSC01E_INT_MB3 6 |
| #define MSC01E_INT_COREHI MSC01E_INT_MB3 |
| #define MSC01E_INT_MB4 7 |
| #define MSC01E_INT_CORELO MSC01E_INT_MB4 |
| #define MSC01E_INT_TMR 8 |
| #define MSC01E_INT_PCI 9 |
| #define MSC01E_INT_PERFCTR 10 |
| #define MSC01E_INT_CPUCTR 11 |
| |
| #ifndef __ASSEMBLY__ |
| extern void maltaint_init(void); |
| #endif |
| |
| #endif /* !(_MIPS_MALTAINT_H) */ |
