tree a1e7a0083a3866264331abfc1da8526a35523af0
parent 6313e3c21743cc88bb5bd8aa72948ee1e83937b6
author Catalin Marinas <catalin.marinas@arm.com> 1291737124 +0100
committer Russell King <rmk+kernel@arm.linux.org.uk> 1292196358 +0000

ARM: 6527/1: Use CTR instead of CCSIDR for the D-cache line size on ARMv7

The current implementation of the dcache_line_size macro reads the L1
cache size from the CCSIDR register. This, however, is not guaranteed to
be the smallest cache line in the cache hierarchy. The patch changes to
the macro to use the more architecturally correct CTR register.

Reported-by: Kevin Sapp <ksapp@quicinc.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>