tree 2521a37a27117a354e681d044cf357656144ac37
parent e45187620f9fc103edf68fa5ea78e73033e1668c
author Christian König <christian.koenig@amd.com> 1398278766 +0200
committer Christian König <christian.koenig@amd.com> 1398940062 +0200

drm/radeon: use pflip irq on R600+ v2

Testing the update pending bit directly after issuing an
update is nonsense cause depending on the pixel clock the
CRTC needs a bit of time to execute the flip even when we
are in the VBLANK period.

This is just a non invasive patch to solve the problem at
hand, a more complete and cleaner solution should follow
in the next merge window.

Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=76564

v2: fix source IDs for CRTC2-6

Signed-off-by: Christian König <christian.koenig@amd.com>
Cc: stable@vger.kernel.org