tree 473073168643374dfec8caca3199286c85705793
parent 3a6ac5004c7c8b140319439f8b1f3f6d4cbfe67a
author John Crispin <blogic@openwrt.org> 1345105542 +0000
committer John Crispin <blogic@openwrt.org> 1345673298 +0200

MIPS: lantiq: enable pci clk conditional for xrx200 SoC

The xrx200 SoC family has the same PCI clock register layout as the AR9.
Enable the same quirk as for AR9

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4235/