[ALSA] sound/pci: fix-up sleeping paths
ENS1370/1+ driver,ES1968 driver,Intel8x0 driver,VIA82xx driver
VIA82xx-modem driver,AC97 Codec,ALI5451 driver,CS46xx driver
MIXART driver,RME HDSP driver,Trident driver,YMFPCI driver
Description: Fix-up sleeping in sound/pci. These changes fall under the
following two categories:
1) Replace schedule_timeout() with msleep() to guarantee the
task delays as expected. This also involved replacing/removing
custom sleep functions.
2) Do not assume jiffies will only increment by one if you
request a 1 jiffy sleep, i.e. use time_after/time_before in
while loops.
Signed-off-by: Nishanth Aravamudan <nacc@us.ibm.com>
Signed-off-by: Jaroslav Kysela <perex@suse.cz>
diff --git a/sound/pci/ac97/ac97_codec.c b/sound/pci/ac97/ac97_codec.c
index 0677d41..94cd989 100644
--- a/sound/pci/ac97/ac97_codec.c
+++ b/sound/pci/ac97/ac97_codec.c
@@ -2227,6 +2227,7 @@
void snd_ac97_resume(ac97_t *ac97)
{
int i;
+ unsigned long end_time;
if (ac97->bus->ops->reset) {
ac97->bus->ops->reset(ac97);
@@ -2244,26 +2245,26 @@
snd_ac97_write(ac97, AC97_POWERDOWN, ac97->regs[AC97_POWERDOWN]);
if (ac97_is_audio(ac97)) {
ac97->bus->ops->write(ac97, AC97_MASTER, 0x8101);
- for (i = HZ/10; i >= 0; i--) {
+ end_time = jiffies + msecs_to_jiffies(100);
+ do {
if (snd_ac97_read(ac97, AC97_MASTER) == 0x8101)
break;
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(1);
- }
+ } while (time_after_eq(end_time, jiffies));
/* FIXME: extra delay */
ac97->bus->ops->write(ac97, AC97_MASTER, 0x8000);
- if (snd_ac97_read(ac97, AC97_MASTER) != 0x8000) {
- set_current_state(TASK_UNINTERRUPTIBLE);
- schedule_timeout(HZ/4);
- }
+ if (snd_ac97_read(ac97, AC97_MASTER) != 0x8000)
+ msleep(250);
} else {
- for (i = HZ/10; i >= 0; i--) {
+ end_time = jiffies + msecs_to_jiffies(100);
+ do {
unsigned short val = snd_ac97_read(ac97, AC97_EXTENDED_MID);
if (val != 0xffff && (val & 1) != 0)
break;
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(1);
- }
+ } while (time_after_eq(end_time, jiffies));
}
__reset_ready:
diff --git a/sound/pci/ali5451/ali5451.c b/sound/pci/ali5451/ali5451.c
index eb5c36d..f08ae71f 100644
--- a/sound/pci/ali5451/ali5451.c
+++ b/sound/pci/ali5451/ali5451.c
@@ -399,7 +399,7 @@
unsigned long end_time;
unsigned int res;
- end_time = jiffies + 10 * (HZ >> 2);
+ end_time = jiffies + 10 * msecs_to_jiffies(250);
do {
res = snd_ali_5451_peek(codec,port);
if (! (res & 0x8000))
@@ -422,7 +422,7 @@
dwChk1 = snd_ali_5451_peek(codec, ALI_STIMER);
dwChk2 = snd_ali_5451_peek(codec, ALI_STIMER);
- end_time = jiffies + 10 * (HZ >> 2);
+ end_time = jiffies + 10 * msecs_to_jiffies(250);
do {
dwChk2 = snd_ali_5451_peek(codec, ALI_STIMER);
if (dwChk2 != dwChk1)
diff --git a/sound/pci/cs46xx/cs46xx_lib.c b/sound/pci/cs46xx/cs46xx_lib.c
index fd4c50c..ff28af1 100644
--- a/sound/pci/cs46xx/cs46xx_lib.c
+++ b/sound/pci/cs46xx/cs46xx_lib.c
@@ -2400,8 +2400,7 @@
if ((err = snd_ac97_read(ac97, AC97_REC_GAIN)) == 0x8a05)
return;
- set_current_state(TASK_UNINTERRUPTIBLE);
- schedule_timeout(HZ/100);
+ msleep(10);
} while (time_after_eq(end_time, jiffies));
snd_printk("CS46xx secondary codec dont respond!\n");
@@ -2435,8 +2434,7 @@
err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]);
return err;
}
- set_current_state(TASK_INTERRUPTIBLE);
- schedule_timeout(HZ/100);
+ msleep(10);
}
snd_printdd("snd_cs46xx: codec %d detection timeout\n", codec);
return -ENXIO;
@@ -3018,8 +3016,7 @@
/*
* Wait until the PLL has stabilized.
*/
- set_current_state(TASK_UNINTERRUPTIBLE);
- schedule_timeout(HZ/10); /* 100ms */
+ msleep(100);
/*
* Turn on clocking of the core so that we can setup the serial ports.
@@ -3072,8 +3069,7 @@
*/
if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY)
goto ok1;
- set_current_state(TASK_UNINTERRUPTIBLE);
- schedule_timeout((HZ+99)/100);
+ msleep(10);
}
@@ -3122,8 +3118,7 @@
*/
if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
goto ok2;
- set_current_state(TASK_UNINTERRUPTIBLE);
- schedule_timeout((HZ+99)/100);
+ msleep(10);
}
#ifndef CONFIG_SND_CS46XX_NEW_DSP
diff --git a/sound/pci/ens1370.c b/sound/pci/ens1370.c
index d428733..78a81f3 100644
--- a/sound/pci/ens1370.c
+++ b/sound/pci/ens1370.c
@@ -2018,21 +2018,11 @@
if (pci->vendor == es1371_ac97_reset_hack[idx].vid &&
pci->device == es1371_ac97_reset_hack[idx].did &&
ensoniq->rev == es1371_ac97_reset_hack[idx].rev) {
- unsigned long tmo;
- signed long tmo2;
-
ensoniq->cssr |= ES_1371_ST_AC97_RST;
outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
/* need to delay around 20ms(bleech) to give
some CODECs enough time to wakeup */
- tmo = jiffies + (HZ / 50) + 1;
- while (1) {
- tmo2 = tmo - jiffies;
- if (tmo2 <= 0)
- break;
- set_current_state(TASK_UNINTERRUPTIBLE);
- schedule_timeout(tmo2);
- }
+ msleep(20);
break;
}
/* AC'97 warm reset to start the bitclk */
diff --git a/sound/pci/es1968.c b/sound/pci/es1968.c
index 327a341..9d7a287 100644
--- a/sound/pci/es1968.c
+++ b/sound/pci/es1968.c
@@ -664,11 +664,6 @@
return result;
}
-#define big_mdelay(msec) do {\
- set_current_state(TASK_UNINTERRUPTIBLE);\
- schedule_timeout(((msec) * HZ + 999) / 1000);\
-} while (0)
-
/* Wait for the codec bus to be free */
static int snd_es1968_ac97_wait(es1968_t *chip)
{
@@ -1809,8 +1804,7 @@
snd_es1968_trigger_apu(chip, apu, ESM_APU_16BITLINEAR);
do_gettimeofday(&start_time);
spin_unlock_irq(&chip->reg_lock);
- set_current_state(TASK_UNINTERRUPTIBLE);
- schedule_timeout(HZ / 20); /* 50 msec */
+ msleep(50);
spin_lock_irq(&chip->reg_lock);
offset = __apu_get_register(chip, apu, 5);
do_gettimeofday(&stop_time);
@@ -2093,7 +2087,7 @@
outw(0x0000, ioaddr + 0x60); /* write 0 to gpio 0 */
udelay(20);
outw(0x0001, ioaddr + 0x60); /* write 1 to gpio 1 */
- big_mdelay(20);
+ msleep(20);
outw(save_68 | 0x1, ioaddr + 0x68); /* now restore .. */
outw((inw(ioaddr + 0x38) & 0xfffc) | 0x1, ioaddr + 0x38);
@@ -2109,7 +2103,7 @@
outw(0x0001, ioaddr + 0x60); /* write 1 to gpio */
udelay(20);
outw(0x0009, ioaddr + 0x60); /* write 9 to gpio */
- big_mdelay(500);
+ msleep(500);
//outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38);
outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a);
outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c);
@@ -2135,7 +2129,7 @@
if (w > 10000) {
outb(inb(ioaddr + 0x37) | 0x08, ioaddr + 0x37); /* do a software reset */
- big_mdelay(500); /* oh my.. */
+ msleep(500); /* oh my.. */
outb(inb(ioaddr + 0x37) & ~0x08,
ioaddr + 0x37);
udelay(1);
diff --git a/sound/pci/intel8x0.c b/sound/pci/intel8x0.c
index c3c3b68..7c806bd 100644
--- a/sound/pci/intel8x0.c
+++ b/sound/pci/intel8x0.c
@@ -2464,8 +2464,7 @@
}
do_gettimeofday(&start_time);
spin_unlock_irq(&chip->reg_lock);
- set_current_state(TASK_UNINTERRUPTIBLE);
- schedule_timeout(HZ / 20);
+ msleep(50);
spin_lock_irq(&chip->reg_lock);
/* check the position */
pos = ichdev->fragsize1;
diff --git a/sound/pci/mixart/mixart.c b/sound/pci/mixart/mixart.c
index 082c0d0..6c868d9 100644
--- a/sound/pci/mixart/mixart.c
+++ b/sound/pci/mixart/mixart.c
@@ -445,9 +445,9 @@
static int mixart_sync_nonblock_events(mixart_mgr_t *mgr)
{
- int timeout = HZ;
+ unsigned long timeout = jiffies + HZ;
while (atomic_read(&mgr->msg_processed) > 0) {
- if (! timeout--) {
+ if (time_after(jiffies, timeout)) {
snd_printk(KERN_ERR "mixart: cannot process nonblock events!\n");
return -EBUSY;
}
diff --git a/sound/pci/rme9652/hdsp.c b/sound/pci/rme9652/hdsp.c
index 0db558a..796621d 100644
--- a/sound/pci/rme9652/hdsp.c
+++ b/sound/pci/rme9652/hdsp.c
@@ -679,8 +679,7 @@
}
if ((1000 / HZ) < 3000) {
- set_current_state(TASK_UNINTERRUPTIBLE);
- schedule_timeout((3000 * HZ + 999) / 1000);
+ ssleep(3);
} else {
mdelay(3000);
}
@@ -5080,8 +5079,7 @@
if (!is_9652 && !is_9632) {
/* we wait 2 seconds to let freshly inserted cardbus cards do their hardware init */
if ((1000 / HZ) < 2000) {
- set_current_state(TASK_UNINTERRUPTIBLE);
- schedule_timeout((2000 * HZ + 999) / 1000);
+ ssleep(2);
} else {
mdelay(2000);
}
diff --git a/sound/pci/trident/trident_main.c b/sound/pci/trident/trident_main.c
index b01c91b..29d89bfb 100644
--- a/sound/pci/trident/trident_main.c
+++ b/sound/pci/trident/trident_main.c
@@ -3153,8 +3153,7 @@
switch (mode) {
case GAMEPORT_MODE_COOKED:
outb(GAMEPORT_MODE_ADC, TRID_REG(chip, GAMEPORT_GCR));
- set_current_state(TASK_UNINTERRUPTIBLE);
- schedule_timeout(1 + 20 * HZ / 1000); /* 20msec */
+ msleep(20);
return 0;
case GAMEPORT_MODE_RAW:
outb(0, TRID_REG(chip, GAMEPORT_GCR));
diff --git a/sound/pci/via82xx.c b/sound/pci/via82xx.c
index 064972b..890582c 100644
--- a/sound/pci/via82xx.c
+++ b/sound/pci/via82xx.c
@@ -547,8 +547,7 @@
int err;
err = snd_via82xx_codec_ready(chip, ac97->num);
/* here we need to wait fairly for long time.. */
- set_current_state(TASK_UNINTERRUPTIBLE);
- schedule_timeout(HZ/2);
+ msleep(500);
}
static void snd_via82xx_codec_write(ac97_t *ac97,
@@ -1847,7 +1846,7 @@
static int snd_via82xx_chip_init(via82xx_t *chip)
{
unsigned int val;
- int max_count;
+ unsigned long end_time;
unsigned char pval;
#if 0 /* broken on K7M? */
@@ -1889,14 +1888,14 @@
}
/* wait until codec ready */
- max_count = ((3 * HZ) / 4) + 1;
+ end_time = jiffies + msecs_to_jiffies(750);
do {
pci_read_config_byte(chip->pci, VIA_ACLINK_STAT, &pval);
if (pval & VIA_ACLINK_C00_READY) /* primary codec ready */
break;
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(1);
- } while (--max_count > 0);
+ } while (time_before(jiffies, end_time));
if ((val = snd_via82xx_codec_xread(chip)) & VIA_REG_AC97_BUSY)
snd_printk("AC'97 codec is not ready [0x%x]\n", val);
@@ -1905,7 +1904,7 @@
snd_via82xx_codec_xwrite(chip, VIA_REG_AC97_READ |
VIA_REG_AC97_SECONDARY_VALID |
(VIA_REG_AC97_CODEC_ID_SECONDARY << VIA_REG_AC97_CODEC_ID_SHIFT));
- max_count = ((3 * HZ) / 4) + 1;
+ end_time = jiffies + msecs_to_jiffies(750);
snd_via82xx_codec_xwrite(chip, VIA_REG_AC97_READ |
VIA_REG_AC97_SECONDARY_VALID |
(VIA_REG_AC97_CODEC_ID_SECONDARY << VIA_REG_AC97_CODEC_ID_SHIFT));
@@ -1916,7 +1915,7 @@
}
set_current_state(TASK_INTERRUPTIBLE);
schedule_timeout(1);
- } while (--max_count > 0);
+ } while (time_before(jiffies, end_time));
/* This is ok, the most of motherboards have only one codec */
__ac97_ok2:
diff --git a/sound/pci/via82xx_modem.c b/sound/pci/via82xx_modem.c
index 5896d28..4a9779c 100644
--- a/sound/pci/via82xx_modem.c
+++ b/sound/pci/via82xx_modem.c
@@ -408,8 +408,7 @@
int err;
err = snd_via82xx_codec_ready(chip, ac97->num);
/* here we need to wait fairly for long time.. */
- set_current_state(TASK_UNINTERRUPTIBLE);
- schedule_timeout(HZ/2);
+ msleep(500);
}
static void snd_via82xx_codec_write(ac97_t *ac97,
@@ -923,7 +922,7 @@
static int snd_via82xx_chip_init(via82xx_t *chip)
{
unsigned int val;
- int max_count;
+ unsigned long end_time;
unsigned char pval;
pci_read_config_byte(chip->pci, VIA_MC97_CTRL, &pval);
@@ -962,14 +961,14 @@
}
/* wait until codec ready */
- max_count = ((3 * HZ) / 4) + 1;
+ end_time = jiffies + msecs_to_jiffies(750);
do {
pci_read_config_byte(chip->pci, VIA_ACLINK_STAT, &pval);
if (pval & VIA_ACLINK_C00_READY) /* primary codec ready */
break;
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(1);
- } while (--max_count > 0);
+ } while (time_before(jiffies, end_time));
if ((val = snd_via82xx_codec_xread(chip)) & VIA_REG_AC97_BUSY)
snd_printk("AC'97 codec is not ready [0x%x]\n", val);
@@ -977,7 +976,7 @@
snd_via82xx_codec_xwrite(chip, VIA_REG_AC97_READ |
VIA_REG_AC97_SECONDARY_VALID |
(VIA_REG_AC97_CODEC_ID_SECONDARY << VIA_REG_AC97_CODEC_ID_SHIFT));
- max_count = ((3 * HZ) / 4) + 1;
+ end_time = jiffies + msecs_to_jiffies(750);
snd_via82xx_codec_xwrite(chip, VIA_REG_AC97_READ |
VIA_REG_AC97_SECONDARY_VALID |
(VIA_REG_AC97_CODEC_ID_SECONDARY << VIA_REG_AC97_CODEC_ID_SHIFT));
@@ -988,7 +987,7 @@
}
set_current_state(TASK_INTERRUPTIBLE);
schedule_timeout(1);
- } while (--max_count > 0);
+ } while (time_before(jiffies, end_time));
/* This is ok, the most of motherboards have only one codec */
__ac97_ok2:
diff --git a/sound/pci/ymfpci/ymfpci_main.c b/sound/pci/ymfpci/ymfpci_main.c
index 2ae7961..d54f88a 100644
--- a/sound/pci/ymfpci/ymfpci_main.c
+++ b/sound/pci/ymfpci/ymfpci_main.c
@@ -84,16 +84,16 @@
static int snd_ymfpci_codec_ready(ymfpci_t *chip, int secondary)
{
- signed long end_time;
+ unsigned long end_time;
u32 reg = secondary ? YDSXGR_SECSTATUSADR : YDSXGR_PRISTATUSADR;
- end_time = (jiffies + ((3 * HZ) / 4)) + 1;
+ end_time = jiffies + msecs_to_jiffies(750);
do {
if ((snd_ymfpci_readw(chip, reg) & 0x8000) == 0)
return 0;
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(1);
- } while (end_time - (signed long)jiffies >= 0);
+ } while (time_before(jiffies, end_time));
snd_printk("codec_ready: codec %i is not ready [0x%x]\n", secondary, snd_ymfpci_readw(chip, reg));
return -EBUSY;
}
