tree 22c2eb369022138b5da775c791e5126c7068d8b0
parent be456b77ffbd3983b5da8eff49a70a701333f68b
author Sergei Shtylyov <sshtylyov@ru.mvista.com> 1186765126 +0400
committer Jeff Garzik <jeff@garzik.org> 1187165947 -0400

pata_hpt37x: actually clock HPT374 with 50 MHz DPLL (take 2)

The DPLL tuning code always set up it for 66 MHz due to wrong UltraDMA mask
including mode 5 used to check for the necessity of 66 MHz clocking -- this
caused 66 MHz clock to be used for HPT374 chip that does not tolerate it.
While fixing this, also remove PLL mode from the TODO list -- I don't think
it's still a relevant item.

Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>