/*
 * SBC8548 Device Tree Source
 *
 * Copyright 2007 Wind River Systems Inc.
 *
 * Paul Gortmaker (see MAINTAINERS for contact information)
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */


/dts-v1/;

/ {
	model = "SBC8548";
	compatible = "SBC8548";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
		/* pci1 doesn't have a corresponding physical connector */
		pci2 = &pci2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8548@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <0x20>;	// 32 bytes
			i-cache-line-size = <0x20>;	// 32 bytes
			d-cache-size = <0x8000>;	// L1, 32K
			i-cache-size = <0x8000>;	// L1, 32K
			timebase-frequency = <0>;	// From uboot
			bus-frequency = <0>;
			clock-frequency = <0>;
			next-level-cache = <&L2>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x10000000>;
	};

	localbus@e0000000 {
		#address-cells = <2>;
		#size-cells = <1>;
		compatible = "simple-bus";
		reg = <0xe0000000 0x5000>;
		interrupt-parent = <&mpic>;

		ranges = <0x0 0x0 0xff800000 0x00800000		/*8MB Flash*/
			  0x3 0x0 0xf0000000 0x04000000		/*64MB SDRAM*/
			  0x4 0x0 0xf4000000 0x04000000 	/*64MB SDRAM*/
			  0x5 0x0 0xf8000000 0x00b10000		/* EPLD */
			  0x6 0x0 0xfb800000 0x04000000>;	/*64MB Flash*/


		flash@0,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "cfi-flash";
			reg = <0x0 0x0 0x800000>;
			bank-width = <1>;
			device-width = <1>;
			partition@0x0 {
				label = "space";
				reg = <0x00000000 0x00100000>;
			};
			partition@0x100000 {
				label = "bootloader";
				reg = <0x00100000 0x00700000>;
				read-only;
			};
		};

		epld@5,0 {
			compatible = "wrs,epld-localbus";
			#address-cells = <2>;
			#size-cells = <1>;
			reg = <0x5 0x0 0x00b10000>;
			ranges = <
				0x0 0x0 0x5 0x000000 0x1fff	/* LED */
				0x1 0x0 0x5 0x100000 0x1fff	/* Switches */
				0x3 0x0 0x5 0x300000 0x1fff	/* HW Rev. */
				0xb 0x0	0x5 0xb00000 0x1fff	/* EEPROM */
			>;

			led@0,0 {
				compatible = "led";
				reg = <0x0 0x0 0x1fff>;
			};

			switches@1,0 {
				compatible = "switches";
				reg = <0x1 0x0 0x1fff>;
			};

			hw-rev@3,0 {
				compatible = "hw-rev";
				reg = <0x3 0x0 0x1fff>;
			};

			eeprom@b,0 {
				compatible = "eeprom";
				reg = <0xb 0 0x1fff>;
			};

		};

		alt-flash@6,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x6 0x0 0x04000000>;
			compatible = "cfi-flash";
			bank-width = <4>;
			device-width = <1>;
			partition@0x0 {
				label = "bootloader";
				reg = <0x00000000 0x00100000>;
				read-only;
			};
			partition@0x00100000 {
				label = "file-system";
				reg = <0x00100000 0x01f00000>;
			};
			partition@0x02000000 {
				label = "boot-config";
				reg = <0x02000000 0x00100000>;
			};
			partition@0x02100000 {
				label = "space";
				reg = <0x02100000 0x01f00000>;
			};
                };
        };

	soc8548@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		ranges = <0x00000000 0xe0000000 0x00100000>;
		reg = <0xe0000000 0x00001000>;	// CCSRBAR
		bus-frequency = <0>;
		compatible = "simple-bus";

		memory-controller@2000 {
			compatible = "fsl,8548-memory-controller";
			reg = <0x2000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <0x12 0x2>;
		};

		L2: l2-cache-controller@20000 {
			compatible = "fsl,8548-l2-cache-controller";
			reg = <0x20000 0x1000>;
			cache-line-size = <0x20>;	// 32 bytes
			cache-size = <0x80000>;	// L2, 512K
			interrupt-parent = <&mpic>;
			interrupts = <0x10 0x2>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <0x2b 0x2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <0x2b 0x2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
			reg = <0x21300 0x4>;
			ranges = <0x0 0x21100 0x200>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8548-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8548-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8548-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8548-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x180 0x80>;
				cell-index = <3>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};

		enet0: ethernet@24000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <0>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			ranges = <0x0 0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi0>;
			phy-handle = <&phy0>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-mdio";
				reg = <0x520 0x20>;

				phy0: ethernet-phy@19 {
					interrupt-parent = <&mpic>;
					interrupts = <0x6 0x1>;
					reg = <0x19>;
					device_type = "ethernet-phy";
				};
				phy1: ethernet-phy@1a {
					interrupt-parent = <&mpic>;
					interrupts = <0x7 0x1>;
					reg = <0x1a>;
					device_type = "ethernet-phy";
				};
				tbi0: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		enet1: ethernet@25000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <1>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			ranges = <0x0 0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi1>;
			phy-handle = <&phy1>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

				tbi1: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;	// reg base, size
			clock-frequency = <0>;	// should we fill in in uboot?
			interrupts = <0x2a 0x2>;
			interrupt-parent = <&mpic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;	// reg base, size
			clock-frequency = <0>;	// should we fill in in uboot?
			interrupts = <0x2a 0x2>;
			interrupt-parent = <&mpic>;
		};

		global-utilities@e0000 {	//global utilities reg
			compatible = "fsl,mpc8548-guts";
			reg = <0xe0000 0x1000>;
			fsl,has-rstcr;
		};

		crypto@30000 {
			compatible = "fsl,sec2.1", "fsl,sec2.0";
			reg = <0x30000 0x10000>;
			interrupts = <45 2>;
			interrupt-parent = <&mpic>;
			fsl,num-channels = <4>;
			fsl,channel-fifo-len = <24>;
			fsl,exec-units-mask = <0xfe>;
			fsl,descriptor-types-mask = <0x12b0ebf>;
		};

		mpic: pic@40000 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
		};
	};

	pci0: pci@e0008000 {
		cell-index = <0>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <
			/* IDSEL 0x01 (PCI-X slot) @66MHz */
			0x0800 0x0 0x0 0x1 &mpic 0x2 0x1
			0x0800 0x0 0x0 0x2 &mpic 0x3 0x1
			0x0800 0x0 0x0 0x3 &mpic 0x4 0x1
			0x0800 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x11 (PCI, 3.3V 32bit) @33MHz */
			0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
			0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
			0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
			0x8800 0x0 0x0 0x4 &mpic 0x1 0x1>;

		interrupt-parent = <&mpic>;
		interrupts = <0x18 0x2>;
		bus-range = <0 0>;
		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
			  0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00800000>;
		clock-frequency = <66666666>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008000 0x1000>;
		compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
		device_type = "pci";
	};

	pci2: pcie@e000a000 {
		cell-index = <2>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

			/* IDSEL 0x0 (PEX) */
			0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
			0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
			0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
			0x0000 0x0 0x0 0x4 &mpic 0x3 0x1>;

		interrupt-parent = <&mpic>;
		interrupts = <0x1a 0x2>;
		bus-range = <0x0 0xff>;
		ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
			  0x01000000 0x0 0x00000000 0xe3000000 0x0 0x08000000>;
		clock-frequency = <33333333>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe000a000 0x1000>;
		compatible = "fsl,mpc8548-pcie";
		device_type = "pci";
		pcie@0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x02000000 0x0 0xa0000000
				  0x02000000 0x0 0xa0000000
				  0x0 0x20000000

				  0x01000000 0x0 0x00000000
				  0x01000000 0x0 0x00000000
				  0x0 0x08000000>;
		};
	};
};