tree fb5e53355a8b9973d6ae2a1b9ab0d6b86f2efeb9
parent fc7a9feb9c9df50ed6d115514b48c49e8511a4de
author Benjamin Herrenschmidt <benh@kernel.crashing.org> 1231700625 +0000
committer Benjamin Herrenschmidt <benh@kernel.crashing.org> 1231818483 +1100

powerpc/powermac: Fix occasional SMP boot failure

The PowerMac kernel occasionally fails to bring up the secondary CPUs on
SMP, the trigger factor seem to be fairly random and related to location
of code and data.

This appears to be due to the initial loading of the TOC value by the
secondary processor which now happens before we clear HID4:RM_CI (Real
Mode Cache Invalidate). This bit should really be cleared before we do
any load or store other than fetching code.

This fix works based on the assumption that all SMP 64-bit PowerMacs use
variants of the 970, which fortunately is true, by explicitely clearing
that bit, adding an slbia for good measure as RM_CI mode is known to
create bogus ERAT entries.

I also removed some spurrious debug output that was left enabled by
mistake while at it.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>