[MIPS] Define MIPS_CPU_IRQ_BASE in generic header
The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all
platforms and are same value on most platforms (0 or 16, depends on
CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make
them customizable. This will save a few cycle on each CPU interrupt.
A good side effect is removing some dependencies to MALTA in generic
SMTC code.
Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq
mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing
them might cause some header dependency problem and there seems no
good reason to customize it. So currently only VR41XX is using custom
MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259.
Testing this patch on those platforms is greatly appreciated. Thank
you.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff --git a/include/asm-mips/emma2rh/emma2rh.h b/include/asm-mips/emma2rh/emma2rh.h
index 4fb8df7..6a1af0a 100644
--- a/include/asm-mips/emma2rh/emma2rh.h
+++ b/include/asm-mips/emma2rh/emma2rh.h
@@ -24,6 +24,8 @@
#ifndef __ASM_EMMA2RH_EMMA2RH_H
#define __ASM_EMMA2RH_EMMA2RH_H
+#include <irq.h>
+
/*
* EMMA2RH registers
*/
@@ -104,7 +106,8 @@
#define NUM_EMMA2RH_IRQ 96
#define CPU_EMMA2RH_CASCADE 2
-#define EMMA2RH_IRQ_BASE 0
+#define CPU_IRQ_BASE MIPS_CPU_IRQ_BASE
+#define EMMA2RH_IRQ_BASE (CPU_IRQ_BASE + NUM_CPU_IRQ)
/*
* emma2rh irq defs
