Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6: (54 commits)
MAINTIANERS: just use Mike gmail e-mail for contact and pawn the serial driver off onto Sonic
[Blackfin] arch: remove old I2C BF54x porting.
[Blackfin] arch: Add the semtimedop syscall. Upstream uClibc doesn't compile without it.
[Blackfin] arch: fix bug kernel boot message: memory information is not reasonable
[Blackfin] arch: use common flash driver to setup partitions rather than the bf5xx-flash driver
[Blackfin] arch: Fix bug - kernel build with Debug option enabled fails to boot up
[Blackfin] arch: Fix bug Only RTC interrupt can wake up deeper sleep core.
[Blackfin] arch: Add proper SW System Reset delay sequence
[Blackfin] arch: Update copyright date
[Blackfin] arch: GPIO API cleanup and anomaly update
[Blackfin] arch: Fix BUG gpio_direction_output API is not compatitable with GENERIC_GPIO API interface
[Blackfin] arch: Initial checkin of the memory protection support.
[Blackfin] arch: set_bfin_dma_config shouldnt set SYNC or RESTART by default - add argument or option
[Blackfin] arch: Add some comments - fix semicolons
[Blackfin] arch: move all code related to CPLB handling into a new subdirectory under kernel/
[Blackfin] arch: print out list of modules if kernel is crashing and tell people if the kernel is tainted
[Blackfin] arch: enable generic GPIO based I2C driver in STAMP-BF533, EZKIT-BF533 and EZKIT-BF561 boards
[Blackfin] arch: Don't oops_in_progress if single step is comming from the kernel
[Blackfin] arch: Fix BUG - kernel sometimes would stuck with KEYBOARD_GPIO on
[Blackfin] arch: update to latest anomaly sheets
...
diff --git a/MAINTAINERS b/MAINTAINERS
index 59db481..2937122 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -758,22 +758,20 @@
BLACKFIN RTC DRIVER
P: Mike Frysinger
-M: michael.frysinger@analog.com
M: vapier.adi@gmail.com
L: uclinux-dist-devel@blackfin.uclinux.org (subscribers-only)
W: http://blackfin.uclinux.org
S: Supported
BLACKFIN SERIAL DRIVER
-P: Aubrey Li
-M: aubrey.li@analog.com
+P: Sonic Zhang
+M: sonic.zhang@analog.com
L: uclinux-dist-devel@blackfin.uclinux.org (subscribers-only)
W: http://blackfin.uclinux.org
S: Supported
BLACKFIN WATCHDOG DRIVER
P: Mike Frysinger
-M: michael.frysinger@analog.com
M: vapier.adi@gmail.com
L: uclinux-dist-devel@blackfin.uclinux.org (subscribers-only)
W: http://blackfin.uclinux.org
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index 25232ba..fc7ca86 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -85,11 +85,26 @@
help
BF522 Processor Support.
+config BF523
+ bool "BF523"
+ help
+ BF523 Processor Support.
+
+config BF524
+ bool "BF524"
+ help
+ BF524 Processor Support.
+
config BF525
bool "BF525"
help
BF525 Processor Support.
+config BF526
+ bool "BF526"
+ help
+ BF526 Processor Support.
+
config BF527
bool "BF527"
help
@@ -198,7 +213,7 @@
config BF52x
bool
- depends on (BF522 || BF525 || BF527)
+ depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
default y
config BF53x
@@ -253,11 +268,6 @@
depends on (BFIN527_EZKIT)
default y
-config BFIN_SHARED_FLASH_ENET
- bool
- depends on (BFIN533_STAMP)
- default y
-
source "arch/blackfin/mach-bf527/Kconfig"
source "arch/blackfin/mach-bf533/Kconfig"
source "arch/blackfin/mach-bf561/Kconfig"
@@ -317,7 +327,7 @@
range 1 64
default "22" if BFIN533_EZKIT
default "45" if BFIN533_STAMP
- default "20" if (BFIN537_STAMP || BFIN527_EZKIT)
+ default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT)
default "22" if BFIN533_BLUETECHNIX_CM
default "20" if BFIN537_BLUETECHNIX_CM
default "20" if BFIN561_BLUETECHNIX_CM
@@ -354,7 +364,7 @@
range 1 15
default 5 if BFIN533_EZKIT
default 5 if BFIN533_STAMP
- default 4 if (BFIN537_STAMP || BFIN527_EZKIT)
+ default 4 if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT)
default 5 if BFIN533_BLUETECHNIX_CM
default 4 if BFIN537_BLUETECHNIX_CM
default 4 if BFIN561_BLUETECHNIX_CM
@@ -371,7 +381,10 @@
config MAX_VCO_HZ
int
default 600000000 if BF522
+ default 400000000 if BF523
+ default 400000000 if BF524
default 600000000 if BF525
+ default 400000000 if BF526
default 600000000 if BF527
default 400000000 if BF531
default 400000000 if BF532
@@ -383,6 +396,8 @@
default 533333333 if BF539
default 600000000 if BF542
default 533333333 if BF544
+ default 600000000 if BF547
+ default 600000000 if BF548
default 533333333 if BF549
default 600000000 if BF561
@@ -409,6 +424,7 @@
default 32 if BFIN533_EZKIT
default 64 if BFIN527_EZKIT
default 64 if BFIN537_STAMP
+ default 64 if BFIN548_EZKIT
default 64 if BFIN561_EZKIT
default 128 if BFIN533_STAMP
default 64 if PNAV10
@@ -416,6 +432,7 @@
config MEM_ADD_WIDTH
int "SDRAM Memory Address Width"
+ depends on (!BF54x)
default 9 if BFIN533_EZKIT
default 9 if BFIN561_EZKIT
default 9 if H8606_HVSISTEMAS
@@ -424,6 +441,19 @@
default 11 if BFIN533_STAMP
default 10 if PNAV10
+
+choice
+ prompt "DDR SDRAM Chip Type"
+ depends on BFIN548_EZKIT
+ default MEM_MT46V32M16_5B
+
+config MEM_MT46V32M16_6T
+ bool "MT46V32M16_6T"
+
+config MEM_MT46V32M16_5B
+ bool "MT46V32M16_5B"
+endchoice
+
config ENET_FLASH_PIN
int "PF port/pin used for flash and ethernet sharing"
depends on (BFIN533_STAMP)
@@ -448,40 +478,6 @@
memory region is used to capture NULL pointer references as well
as some core kernel functions.
-comment "LED Status Indicators"
- depends on (BFIN533_STAMP || BFIN533_BLUETECHNIX_CM)
-
-config BFIN_ALIVE_LED
- bool "Enable Board Alive"
- depends on (BFIN533_STAMP || BFIN533_BLUETECHNIX_CM)
- default n
- help
- Blink the LEDs you select when the kernel is running. Helps detect
- a hung kernel.
-
-config BFIN_ALIVE_LED_NUM
- int "LED"
- depends on BFIN_ALIVE_LED
- range 1 3 if BFIN533_STAMP
- default "3" if BFIN533_STAMP
- help
- Select the LED (marked on the board) for you to blink.
-
-config BFIN_IDLE_LED
- bool "Enable System Load/Idle LED"
- depends on (BFIN533_STAMP || BFIN533_BLUETECHNIX_CM)
- default n
- help
- Blinks the LED you select when to determine kernel load.
-
-config BFIN_IDLE_LED_NUM
- int "LED"
- depends on BFIN_IDLE_LED
- range 1 3 if BFIN533_STAMP
- default "2" if BFIN533_STAMP
- help
- Select the LED (marked on the board) for you to blink.
-
choice
prompt "Blackfin Exception Scratch Register"
default BFIN_SCRATCH_REG_RETN
@@ -528,41 +524,6 @@
endchoice
-#
-# Sorry - but you need to put the hex address here -
-#
-
-# Flag Data register
-config BFIN_ALIVE_LED_PORT
- hex
- default 0xFFC00700 if (BFIN533_STAMP)
-
-# Peripheral Flag Direction Register
-config BFIN_ALIVE_LED_DPORT
- hex
- default 0xFFC00730 if (BFIN533_STAMP)
-
-config BFIN_ALIVE_LED_PIN
- hex
- default 0x04 if (BFIN533_STAMP && BFIN_ALIVE_LED_NUM = 1)
- default 0x08 if (BFIN533_STAMP && BFIN_ALIVE_LED_NUM = 2)
- default 0x10 if (BFIN533_STAMP && BFIN_ALIVE_LED_NUM = 3)
-
-config BFIN_IDLE_LED_PORT
- hex
- default 0xFFC00700 if (BFIN533_STAMP)
-
-# Peripheral Flag Direction Register
-config BFIN_IDLE_LED_DPORT
- hex
- default 0xFFC00730 if (BFIN533_STAMP)
-
-config BFIN_IDLE_LED_PIN
- hex
- default 0x04 if (BFIN533_STAMP && BFIN_IDLE_LED_NUM = 1)
- default 0x08 if (BFIN533_STAMP && BFIN_IDLE_LED_NUM = 2)
- default 0x10 if (BFIN533_STAMP && BFIN_IDLE_LED_NUM = 3)
-
endmenu
@@ -799,6 +760,15 @@
Set the max memory pieces for the L1 SRAM allocation algorithm.
Min value is 16. Max value is 1024.
+
+config MPU
+ bool "Enable the memory protection unit (EXPERIMENTAL)"
+ default n
+ help
+ Use the processor's MPU to protect applications from accessing
+ memory they do not own. This comes at a performance penalty
+ and is recommended only for debugging.
+
comment "Asynchonous Memory Configuration"
menu "EBIU_AMGCTL Global Control"
@@ -808,7 +778,6 @@
config C_CDPRIO
bool "DMA has priority over core for ext. accesses"
- depends on !BF54x
default n
config C_B0PEN
@@ -949,8 +918,10 @@
config PM_WAKEUP_SIC_IWR
hex "Wakeup Events (SIC_IWR)"
depends on PM_WAKEUP_GPIO_BY_SIC_IWR
- default 0x80000000 if (BF537 || BF536 || BF534)
- default 0x100000 if (BF533 || BF532 || BF531)
+ default 0x8 if (BF537 || BF536 || BF534)
+ default 0x80 if (BF533 || BF532 || BF531)
+ default 0x80 if (BF54x)
+ default 0x80 if (BF52x)
config PM_WAKEUP_GPIO_NUMBER
int "Wakeup GPIO number"
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile
index c47e000..0edc402 100644
--- a/arch/blackfin/Makefile
+++ b/arch/blackfin/Makefile
@@ -21,7 +21,10 @@
# setup the machine name and the machine dependent settings
machine-$(CONFIG_BF522) := bf527
+machine-$(CONFIG_BF523) := bf527
+machine-$(CONFIG_BF524) := bf527
machine-$(CONFIG_BF525) := bf527
+machine-$(CONFIG_BF526) := bf527
machine-$(CONFIG_BF527) := bf527
machine-$(CONFIG_BF531) := bf533
machine-$(CONFIG_BF532) := bf533
@@ -39,7 +42,10 @@
export MACHINE
cpu-$(CONFIG_BF522) := bf522
+cpu-$(CONFIG_BF523) := bf523
+cpu-$(CONFIG_BF524) := bf524
cpu-$(CONFIG_BF525) := bf525
+cpu-$(CONFIG_BF526) := bf526
cpu-$(CONFIG_BF527) := bf527
cpu-$(CONFIG_BF531) := bf531
cpu-$(CONFIG_BF532) := bf532
@@ -76,6 +82,12 @@
core-y += arch/$(ARCH)/mach-$(MACHINE)/boards/
endif
+ifeq ($(CONFIG_MPU),y)
+core-y += arch/$(ARCH)/kernel/cplb-mpu/
+else
+core-y += arch/$(ARCH)/kernel/cplb-nompu/
+endif
+
libs-y += arch/$(ARCH)/lib/
drivers-$(CONFIG_OPROFILE) += arch/$(ARCH)/oprofile/
diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig
index fa6eb4e..d59ee15 100644
--- a/arch/blackfin/configs/BF527-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF527-EZKIT_defconfig
@@ -1,6 +1,7 @@
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.22.12
+# Linux kernel version: 2.6.22.14
+# Thu Nov 29 17:32:47 2007
#
# CONFIG_MMU is not set
# CONFIG_FPU is not set
@@ -153,8 +154,8 @@
CONFIG_BF527_SPORT0_PORTG=y
CONFIG_BF527_SPORT0_TSCLK_PG10=y
# CONFIG_BF527_SPORT0_TSCLK_PG14 is not set
-# CONFIG_BF527_UART1_PORTF is not set
-CONFIG_BF527_UART1_PORTG=y
+CONFIG_BF527_UART1_PORTF=y
+# CONFIG_BF527_UART1_PORTG is not set
# CONFIG_BF527_NAND_D_PORTF is not set
CONFIG_BF527_NAND_D_PORTH=y
@@ -232,7 +233,7 @@
# CONFIG_BFIN_KERNEL_CLOCK is not set
CONFIG_MAX_VCO_HZ=600000000
CONFIG_MIN_VCO_HZ=50000000
-CONFIG_MAX_SCLK_HZ=133000000
+CONFIG_MAX_SCLK_HZ=133333333
CONFIG_MIN_SCLK_HZ=27000000
#
@@ -626,8 +627,8 @@
# CONFIG_SMSC911X is not set
# CONFIG_DM9000 is not set
CONFIG_NETDEV_1000=y
-CONFIG_NETDEV_10000=y
# CONFIG_AX88180 is not set
+CONFIG_NETDEV_10000=y
#
# Wireless LAN
@@ -1183,7 +1184,7 @@
#
# CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_MAGIC_SYSRQ=y
+# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
CONFIG_DEBUG_FS=y
# CONFIG_HEADERS_CHECK is not set
@@ -1208,7 +1209,7 @@
# CONFIG_KEYS is not set
CONFIG_SECURITY=y
# CONFIG_SECURITY_NETWORK is not set
-CONFIG_SECURITY_CAPABILITIES=y
+CONFIG_SECURITY_CAPABILITIES=m
#
# Cryptographic options
@@ -1219,7 +1220,7 @@
# Library routines
#
CONFIG_BITREVERSE=y
-# CONFIG_CRC_CCITT is not set
+CONFIG_CRC_CCITT=m
# CONFIG_CRC16 is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
diff --git a/arch/blackfin/configs/BF533-EZKIT_defconfig b/arch/blackfin/configs/BF533-EZKIT_defconfig
index 4fdb493..811711f 100644
--- a/arch/blackfin/configs/BF533-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF533-EZKIT_defconfig
@@ -1,6 +1,6 @@
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.22.12
+# Linux kernel version: 2.6.22.16
#
# CONFIG_MMU is not set
# CONFIG_FPU is not set
@@ -115,7 +115,10 @@
# Processor and Board Settings
#
# CONFIG_BF522 is not set
+# CONFIG_BF523 is not set
+# CONFIG_BF524 is not set
# CONFIG_BF525 is not set
+# CONFIG_BF526 is not set
# CONFIG_BF527 is not set
# CONFIG_BF531 is not set
# CONFIG_BF532 is not set
@@ -194,7 +197,7 @@
# CONFIG_BFIN_KERNEL_CLOCK is not set
CONFIG_MAX_VCO_HZ=750000000
CONFIG_MIN_VCO_HZ=50000000
-CONFIG_MAX_SCLK_HZ=133000000
+CONFIG_MAX_SCLK_HZ=133333333
CONFIG_MIN_SCLK_HZ=27000000
#
@@ -267,6 +270,7 @@
# CONFIG_BFIN_WB is not set
CONFIG_BFIN_WT=y
CONFIG_L1_MAX_PIECE=16
+# CONFIG_MPU is not set
#
# Asynchonous Memory Configuration
@@ -321,7 +325,7 @@
CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR=y
# CONFIG_PM_WAKEUP_BY_GPIO is not set
# CONFIG_PM_WAKEUP_GPIO_API is not set
-CONFIG_PM_WAKEUP_SIC_IWR=0x100000
+CONFIG_PM_WAKEUP_SIC_IWR=0x80
#
# CPU Frequency scaling
@@ -510,7 +514,6 @@
# CONFIG_MTD_CFI_INTELEXT is not set
# CONFIG_MTD_CFI_AMDSTD is not set
# CONFIG_MTD_CFI_STAA is not set
-CONFIG_MTD_MW320D=m
CONFIG_MTD_RAM=y
CONFIG_MTD_ROM=m
# CONFIG_MTD_ABSENT is not set
@@ -520,9 +523,6 @@
#
CONFIG_MTD_COMPLEX_MAPPINGS=y
# CONFIG_MTD_PHYSMAP is not set
-CONFIG_MTD_BF5xx=m
-CONFIG_BFIN_FLASH_SIZE=0x400000
-CONFIG_EBIU_FLASH_BASE=0x20000000
# CONFIG_MTD_UCLINUX is not set
# CONFIG_MTD_PLATRAM is not set
@@ -610,8 +610,8 @@
# CONFIG_SMSC911X is not set
# CONFIG_DM9000 is not set
CONFIG_NETDEV_1000=y
-CONFIG_NETDEV_10000=y
# CONFIG_AX88180 is not set
+CONFIG_NETDEV_10000=y
#
# Wireless LAN
@@ -680,7 +680,6 @@
CONFIG_BFIN_SPORT=y
# CONFIG_BFIN_TIMER_LATENCY is not set
# CONFIG_AD5304 is not set
-# CONFIG_BF5xx_FBDMA is not set
# CONFIG_VT is not set
# CONFIG_SERIAL_NONSTANDARD is not set
diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig
index b04e8e5..9b7123c 100644
--- a/arch/blackfin/configs/BF533-STAMP_defconfig
+++ b/arch/blackfin/configs/BF533-STAMP_defconfig
@@ -1,6 +1,6 @@
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.22.12
+# Linux kernel version: 2.6.22.16
#
# CONFIG_MMU is not set
# CONFIG_FPU is not set
@@ -115,7 +115,10 @@
# Processor and Board Settings
#
# CONFIG_BF522 is not set
+# CONFIG_BF523 is not set
+# CONFIG_BF524 is not set
# CONFIG_BF525 is not set
+# CONFIG_BF526 is not set
# CONFIG_BF527 is not set
# CONFIG_BF531 is not set
# CONFIG_BF532 is not set
@@ -140,7 +143,6 @@
CONFIG_BF53x=y
CONFIG_BFIN_SINGLE_CORE=y
CONFIG_MEM_MT48LC64M4A2FB_7E=y
-CONFIG_BFIN_SHARED_FLASH_ENET=y
# CONFIG_BFIN533_EZKIT is not set
CONFIG_BFIN533_STAMP=y
# CONFIG_BFIN533_BLUETECHNIX_CM is not set
@@ -195,7 +197,7 @@
# CONFIG_BFIN_KERNEL_CLOCK is not set
CONFIG_MAX_VCO_HZ=750000000
CONFIG_MIN_VCO_HZ=50000000
-CONFIG_MAX_SCLK_HZ=133000000
+CONFIG_MAX_SCLK_HZ=133333333
CONFIG_MIN_SCLK_HZ=27000000
#
@@ -215,18 +217,10 @@
CONFIG_ENET_FLASH_PIN=0
CONFIG_BOOT_LOAD=0x1000
-#
-# LED Status Indicators
-#
-# CONFIG_BFIN_ALIVE_LED is not set
-# CONFIG_BFIN_IDLE_LED is not set
+
CONFIG_BFIN_SCRATCH_REG_RETN=y
# CONFIG_BFIN_SCRATCH_REG_RETE is not set
# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set
-CONFIG_BFIN_ALIVE_LED_PORT=0xFFC00700
-CONFIG_BFIN_ALIVE_LED_DPORT=0xFFC00730
-CONFIG_BFIN_IDLE_LED_PORT=0xFFC00700
-CONFIG_BFIN_IDLE_LED_DPORT=0xFFC00730
#
# Blackfin Kernel Optimizations
@@ -279,6 +273,7 @@
# CONFIG_BFIN_WB is not set
CONFIG_BFIN_WT=y
CONFIG_L1_MAX_PIECE=16
+# CONFIG_MPU is not set
#
# Asynchonous Memory Configuration
@@ -333,7 +328,7 @@
CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR=y
# CONFIG_PM_WAKEUP_BY_GPIO is not set
# CONFIG_PM_WAKEUP_GPIO_API is not set
-CONFIG_PM_WAKEUP_SIC_IWR=0x100000
+CONFIG_PM_WAKEUP_SIC_IWR=0x80
#
# CPU Frequency scaling
@@ -522,7 +517,6 @@
# CONFIG_MTD_CFI_INTELEXT is not set
# CONFIG_MTD_CFI_AMDSTD is not set
# CONFIG_MTD_CFI_STAA is not set
-CONFIG_MTD_MW320D=m
CONFIG_MTD_RAM=y
CONFIG_MTD_ROM=m
# CONFIG_MTD_ABSENT is not set
@@ -532,17 +526,6 @@
#
CONFIG_MTD_COMPLEX_MAPPINGS=y
# CONFIG_MTD_PHYSMAP is not set
-CONFIG_MTD_BF5xx=m
-CONFIG_BFIN_FLASH_SIZE=0x400000
-CONFIG_EBIU_FLASH_BASE=0x20000000
-
-#
-# FLASH_EBIU_AMBCTL Control
-#
-CONFIG_BFIN_FLASH_BANK_0=0x7BB0
-CONFIG_BFIN_FLASH_BANK_1=0x7BB0
-CONFIG_BFIN_FLASH_BANK_2=0x7BB0
-CONFIG_BFIN_FLASH_BANK_3=0x7BB0
# CONFIG_MTD_UCLINUX is not set
# CONFIG_MTD_PLATRAM is not set
@@ -630,8 +613,8 @@
# CONFIG_SMSC911X is not set
# CONFIG_DM9000 is not set
CONFIG_NETDEV_1000=y
-CONFIG_NETDEV_10000=y
# CONFIG_AX88180 is not set
+CONFIG_NETDEV_10000=y
#
# Wireless LAN
@@ -687,7 +670,6 @@
# CONFIG_INPUT_POWERMATE is not set
# CONFIG_INPUT_YEALINK is not set
# CONFIG_INPUT_UINPUT is not set
-# CONFIG_BF53X_PFBUTTONS is not set
CONFIG_TWI_KEYPAD=m
CONFIG_BFIN_TWIKEYPAD_IRQ_PFX=39
@@ -711,8 +693,6 @@
CONFIG_TWI_LCD=m
CONFIG_TWI_LCD_SLAVE_ADDR=34
# CONFIG_AD5304 is not set
-# CONFIG_BF5xx_TEA5764 is not set
-# CONFIG_BF5xx_FBDMA is not set
# CONFIG_VT is not set
# CONFIG_SERIAL_NONSTANDARD is not set
@@ -778,7 +758,6 @@
#
# I2C Hardware Bus support
#
-# CONFIG_I2C_BLACKFIN_GPIO is not set
# CONFIG_I2C_GPIO is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PARPORT_LIGHT is not set
diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig
index f812b66..b37ccc6 100644
--- a/arch/blackfin/configs/BF537-STAMP_defconfig
+++ b/arch/blackfin/configs/BF537-STAMP_defconfig
@@ -1,6 +1,6 @@
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.22.12
+# Linux kernel version: 2.6.22.16
#
# CONFIG_MMU is not set
# CONFIG_FPU is not set
@@ -115,7 +115,10 @@
# Processor and Board Settings
#
# CONFIG_BF522 is not set
+# CONFIG_BF523 is not set
+# CONFIG_BF524 is not set
# CONFIG_BF525 is not set
+# CONFIG_BF526 is not set
# CONFIG_BF527 is not set
# CONFIG_BF531 is not set
# CONFIG_BF532 is not set
@@ -170,6 +173,7 @@
CONFIG_BFIN537_STAMP=y
# CONFIG_BFIN537_BLUETECHNIX_CM is not set
# CONFIG_PNAV10 is not set
+# CONFIG_CAMSIG_MINOTAUR is not set
# CONFIG_GENERIC_BF537_BOARD is not set
#
@@ -201,7 +205,7 @@
# CONFIG_BFIN_KERNEL_CLOCK is not set
CONFIG_MAX_VCO_HZ=600000000
CONFIG_MIN_VCO_HZ=50000000
-CONFIG_MAX_SCLK_HZ=133000000
+CONFIG_MAX_SCLK_HZ=133333333
CONFIG_MIN_SCLK_HZ=27000000
#
@@ -274,6 +278,7 @@
# CONFIG_BFIN_WB is not set
CONFIG_BFIN_WT=y
CONFIG_L1_MAX_PIECE=16
+# CONFIG_MPU is not set
#
# Asynchonous Memory Configuration
@@ -328,7 +333,7 @@
CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR=y
# CONFIG_PM_WAKEUP_BY_GPIO is not set
# CONFIG_PM_WAKEUP_GPIO_API is not set
-CONFIG_PM_WAKEUP_SIC_IWR=0x80000000
+CONFIG_PM_WAKEUP_SIC_IWR=0x8
#
# CPU Frequency scaling
@@ -483,7 +488,7 @@
# CONFIG_MTD_CONCAT is not set
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
#
# User Modules And Translation Layers
@@ -500,8 +505,8 @@
#
# RAM/ROM/Flash chip drivers
#
-# CONFIG_MTD_CFI is not set
-CONFIG_MTD_JEDECPROBE=m
+CONFIG_MTD_CFI=m
+# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_GEN_PROBE=m
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
@@ -515,9 +520,9 @@
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_CFI_INTELEXT is not set
-# CONFIG_MTD_CFI_AMDSTD is not set
+CONFIG_MTD_CFI_AMDSTD=m
# CONFIG_MTD_CFI_STAA is not set
-CONFIG_MTD_MW320D=m
+CONFIG_MTD_CFI_UTIL=m
CONFIG_MTD_RAM=y
CONFIG_MTD_ROM=m
# CONFIG_MTD_ABSENT is not set
@@ -525,11 +530,11 @@
#
# Mapping drivers for chip access
#
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-# CONFIG_MTD_PHYSMAP is not set
-CONFIG_MTD_BF5xx=m
-CONFIG_BFIN_FLASH_SIZE=0x400000
-CONFIG_EBIU_FLASH_BASE=0x20000000
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=m
+CONFIG_MTD_PHYSMAP_START=0x20000000
+CONFIG_MTD_PHYSMAP_LEN=0x0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
# CONFIG_MTD_UCLINUX is not set
# CONFIG_MTD_PLATRAM is not set
@@ -647,8 +652,8 @@
# CONFIG_SMSC911X is not set
# CONFIG_DM9000 is not set
CONFIG_NETDEV_1000=y
-CONFIG_NETDEV_10000=y
# CONFIG_AX88180 is not set
+CONFIG_NETDEV_10000=y
#
# Wireless LAN
@@ -704,7 +709,6 @@
# CONFIG_INPUT_POWERMATE is not set
# CONFIG_INPUT_YEALINK is not set
# CONFIG_INPUT_UINPUT is not set
-# CONFIG_BF53X_PFBUTTONS is not set
CONFIG_TWI_KEYPAD=m
CONFIG_BFIN_TWIKEYPAD_IRQ_PFX=72
@@ -728,8 +732,6 @@
CONFIG_TWI_LCD=m
CONFIG_TWI_LCD_SLAVE_ADDR=34
# CONFIG_AD5304 is not set
-# CONFIG_BF5xx_TEA5764 is not set
-# CONFIG_BF5xx_FBDMA is not set
# CONFIG_VT is not set
# CONFIG_SERIAL_NONSTANDARD is not set
@@ -802,7 +804,6 @@
#
# I2C Hardware Bus support
#
-# CONFIG_I2C_BLACKFIN_GPIO is not set
CONFIG_I2C_BLACKFIN_TWI=m
CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50
# CONFIG_I2C_GPIO is not set
@@ -957,6 +958,7 @@
# CONFIG_FB_BFIN_LANDSCAPE is not set
# CONFIG_FB_BFIN_BGR is not set
# CONFIG_FB_BFIN_T350MCQB is not set
+# CONFIG_FB_HITACHI_TX09 is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_LOGO is not set
@@ -1008,12 +1010,22 @@
#
# System on Chip audio support
#
-# CONFIG_SND_SOC is not set
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_SOC=m
+CONFIG_SND_BF5XX_SOC=m
+CONFIG_SND_BF5XX_SOC_AC97=m
+# CONFIG_SND_BF5XX_SOC_WM8750 is not set
+# CONFIG_SND_BF5XX_SOC_WM8731 is not set
+CONFIG_SND_BF5XX_SOC_BF5xx=m
+CONFIG_SND_BF5XX_SPORT_NUM=0
+# CONFIG_SND_BF5XX_HAVE_COLD_RESET is not set
+CONFIG_SND_SOC_AD1980=m
#
# Open Sound System
#
# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=m
#
# HID Devices
diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig
index 48367cc9..fd70216 100644
--- a/arch/blackfin/configs/BF548-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF548-EZKIT_defconfig
@@ -1,6 +1,6 @@
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.22.12
+# Linux kernel version: 2.6.22.16
#
# CONFIG_MMU is not set
# CONFIG_FPU is not set
@@ -115,7 +115,10 @@
# Processor and Board Settings
#
# CONFIG_BF522 is not set
+# CONFIG_BF523 is not set
+# CONFIG_BF524 is not set
# CONFIG_BF525 is not set
+# CONFIG_BF526 is not set
# CONFIG_BF527 is not set
# CONFIG_BF531 is not set
# CONFIG_BF532 is not set
@@ -126,8 +129,8 @@
# CONFIG_BF542 is not set
# CONFIG_BF544 is not set
# CONFIG_BF547 is not set
-# CONFIG_BF548 is not set
-CONFIG_BF549=y
+CONFIG_BF548=y
+# CONFIG_BF549 is not set
# CONFIG_BF561 is not set
CONFIG_BF_REV_0_0=y
# CONFIG_BF_REV_0_1 is not set
@@ -265,9 +268,9 @@
#
CONFIG_CLKIN_HZ=25000000
# CONFIG_BFIN_KERNEL_CLOCK is not set
-CONFIG_MAX_VCO_HZ=533000000
+CONFIG_MAX_VCO_HZ=600000000
CONFIG_MIN_VCO_HZ=50000000
-CONFIG_MAX_SCLK_HZ=133000000
+CONFIG_MAX_SCLK_HZ=133333333
CONFIG_MIN_SCLK_HZ=27000000
#
@@ -283,7 +286,8 @@
# Memory Setup
#
CONFIG_MEM_SIZE=64
-CONFIG_MEM_ADD_WIDTH=10
+# CONFIG_MEM_MT46V32M16_6T is not set
+CONFIG_MEM_MT46V32M16_5B=y
CONFIG_BOOT_LOAD=0x1000
CONFIG_BFIN_SCRATCH_REG_RETN=y
# CONFIG_BFIN_SCRATCH_REG_RETE is not set
@@ -340,6 +344,7 @@
# CONFIG_BFIN_WB is not set
CONFIG_BFIN_WT=y
CONFIG_L1_MAX_PIECE=16
+# CONFIG_MPU is not set
#
# Asynchonous Memory Configuration
@@ -349,6 +354,7 @@
# EBIU_AMGCTL Global Control
#
CONFIG_C_AMCKEN=y
+# CONFIG_C_CDPRIO is not set
# CONFIG_C_AMBEN is not set
# CONFIG_C_AMBEN_B0 is not set
# CONFIG_C_AMBEN_B0_B1 is not set
@@ -362,9 +368,9 @@
CONFIG_BANK_1=0x5554
CONFIG_BANK_2=0x7BB0
CONFIG_BANK_3=0x99B3
-CONFIG_EBUI_MBSCTLVAL=0x0
-CONFIG_EBUI_MODEVAL=0x1
-CONFIG_EBUI_FCTLVAL=0x6
+CONFIG_EBIU_MBSCTLVAL=0x0
+CONFIG_EBIU_MODEVAL=0x1
+CONFIG_EBIU_FCTLVAL=0x6
#
# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
@@ -537,7 +543,6 @@
CONFIG_MTD_CFI_INTELEXT=y
# CONFIG_MTD_CFI_AMDSTD is not set
# CONFIG_MTD_CFI_STAA is not set
-# CONFIG_MTD_MW320D is not set
CONFIG_MTD_CFI_UTIL=y
CONFIG_MTD_RAM=y
# CONFIG_MTD_ROM is not set
@@ -549,9 +554,8 @@
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_START=0x20000000
-CONFIG_MTD_PHYSMAP_LEN=0x400000
+CONFIG_MTD_PHYSMAP_LEN=0
CONFIG_MTD_PHYSMAP_BANKWIDTH=2
-# CONFIG_MTD_BF5xx is not set
# CONFIG_MTD_UCLINUX is not set
# CONFIG_MTD_PLATRAM is not set
@@ -690,8 +694,8 @@
CONFIG_SMSC911X=y
# CONFIG_DM9000 is not set
CONFIG_NETDEV_1000=y
-CONFIG_NETDEV_10000=y
# CONFIG_AX88180 is not set
+CONFIG_NETDEV_10000=y
#
# Wireless LAN
@@ -719,7 +723,7 @@
#
# Input device support
#
-CONFIG_INPUT=m
+CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
@@ -745,7 +749,8 @@
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_GPIO is not set
-CONFIG_KEYBOARD_BFIN=m
+CONFIG_KEYBOARD_BFIN=y
+# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
@@ -768,7 +773,6 @@
# CONFIG_INPUT_POWERMATE is not set
# CONFIG_INPUT_YEALINK is not set
# CONFIG_INPUT_UINPUT is not set
-# CONFIG_BF53X_PFBUTTONS is not set
# CONFIG_TWI_KEYPAD is not set
#
@@ -786,13 +790,16 @@
# CONFIG_BF5xx_PPIFCD is not set
# CONFIG_BFIN_SIMPLE_TIMER is not set
# CONFIG_BF5xx_PPI is not set
+CONFIG_BFIN_OTP=y
+# CONFIG_BFIN_OTP_WRITE_ENABLE is not set
# CONFIG_BFIN_SPORT is not set
# CONFIG_BFIN_TIMER_LATENCY is not set
# CONFIG_TWI_LCD is not set
# CONFIG_AD5304 is not set
-# CONFIG_BF5xx_TEA5764 is not set
-# CONFIG_BF5xx_FBDMA is not set
-# CONFIG_VT is not set
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
# CONFIG_SERIAL_NONSTANDARD is not set
#
@@ -858,7 +865,6 @@
#
# I2C Hardware Bus support
#
-# CONFIG_I2C_BLACKFIN_GPIO is not set
CONFIG_I2C_BLACKFIN_TWI=y
CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50
# CONFIG_I2C_GPIO is not set
@@ -976,12 +982,12 @@
#
# CONFIG_DISPLAY_SUPPORT is not set
# CONFIG_VGASTATE is not set
-CONFIG_FB=m
+CONFIG_FB=y
CONFIG_FIRMWARE_EDID=y
# CONFIG_FB_DDC is not set
-CONFIG_FB_CFB_FILLRECT=m
-CONFIG_FB_CFB_COPYAREA=m
-CONFIG_FB_CFB_IMAGEBLIT=m
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
# CONFIG_FB_SYS_FILLRECT is not set
# CONFIG_FB_SYS_COPYAREA is not set
# CONFIG_FB_SYS_IMAGEBLIT is not set
@@ -998,11 +1004,34 @@
#
# CONFIG_FB_BFIN_7171 is not set
# CONFIG_FB_BFIN_7393 is not set
-CONFIG_FB_BF54X_LQ043=m
+CONFIG_FB_BF54X_LQ043=y
# CONFIG_FB_BFIN_T350MCQB is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_VIRTUAL is not set
-# CONFIG_LOGO is not set
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FONTS=y
+# CONFIG_FONT_8x8 is not set
+# CONFIG_FONT_8x16 is not set
+CONFIG_FONT_6x11=y
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+# CONFIG_LOGO_LINUX_CLUT224 is not set
+# CONFIG_LOGO_BLACKFIN_VGA16 is not set
+CONFIG_LOGO_BLACKFIN_CLUT224=y
#
# Sound
@@ -1051,7 +1080,8 @@
# CONFIG_SND_BF5XX_SOC_WM8750 is not set
# CONFIG_SND_BF5XX_SOC_WM8731 is not set
CONFIG_SND_BF5XX_SPORT_NUM=0
-# CONFIG_SND_BF5XX_HAVE_COLD_RESET is not set
+CONFIG_SND_BF5XX_HAVE_COLD_RESET=y
+CONFIG_SND_BF5XX_RESET_GPIO_NUM=19
CONFIG_SND_SOC_AD1980=y
#
@@ -1403,7 +1433,7 @@
#
# CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_MAGIC_SYSRQ=y
+# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
CONFIG_DEBUG_FS=y
# CONFIG_HEADERS_CHECK is not set
@@ -1428,7 +1458,7 @@
# CONFIG_KEYS is not set
CONFIG_SECURITY=y
# CONFIG_SECURITY_NETWORK is not set
-CONFIG_SECURITY_CAPABILITIES=y
+CONFIG_SECURITY_CAPABILITIES=m
#
# Cryptographic options
@@ -1439,7 +1469,7 @@
# Library routines
#
CONFIG_BITREVERSE=y
-# CONFIG_CRC_CCITT is not set
+CONFIG_CRC_CCITT=m
# CONFIG_CRC16 is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig
index e9f100b..8546994 100644
--- a/arch/blackfin/configs/BF561-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF561-EZKIT_defconfig
@@ -1,6 +1,6 @@
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.22.12
+# Linux kernel version: 2.6.22.16
#
# CONFIG_MMU is not set
# CONFIG_FPU is not set
@@ -115,7 +115,10 @@
# Processor and Board Settings
#
# CONFIG_BF522 is not set
+# CONFIG_BF523 is not set
+# CONFIG_BF524 is not set
# CONFIG_BF525 is not set
+# CONFIG_BF526 is not set
# CONFIG_BF527 is not set
# CONFIG_BF531 is not set
# CONFIG_BF532 is not set
@@ -238,7 +241,7 @@
# CONFIG_BFIN_KERNEL_CLOCK is not set
CONFIG_MAX_VCO_HZ=600000000
CONFIG_MIN_VCO_HZ=50000000
-CONFIG_MAX_SCLK_HZ=133000000
+CONFIG_MAX_SCLK_HZ=133333333
CONFIG_MIN_SCLK_HZ=27000000
#
@@ -311,6 +314,7 @@
# CONFIG_BFIN_WB is not set
CONFIG_BFIN_WT=y
CONFIG_L1_MAX_PIECE=16
+# CONFIG_MPU is not set
#
# Asynchonous Memory Configuration
@@ -512,7 +516,7 @@
# CONFIG_MTD_CONCAT is not set
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
#
# User Modules And Translation Layers
@@ -529,8 +533,8 @@
#
# RAM/ROM/Flash chip drivers
#
-# CONFIG_MTD_CFI is not set
-CONFIG_MTD_JEDECPROBE=m
+CONFIG_MTD_CFI=m
+# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_GEN_PROBE=m
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
@@ -544,9 +548,9 @@
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_CFI_INTELEXT is not set
-# CONFIG_MTD_CFI_AMDSTD is not set
+CONFIG_MTD_CFI_AMDSTD=m
# CONFIG_MTD_CFI_STAA is not set
-CONFIG_MTD_MW320D=m
+CONFIG_MTD_CFI_UTIL=m
CONFIG_MTD_RAM=y
CONFIG_MTD_ROM=m
# CONFIG_MTD_ABSENT is not set
@@ -554,12 +558,11 @@
#
# Mapping drivers for chip access
#
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-# CONFIG_MTD_PHYSMAP is not set
-# CONFIG_MTD_EZKIT561 is not set
-CONFIG_MTD_BF5xx=m
-CONFIG_BFIN_FLASH_SIZE=0x0400000
-CONFIG_EBIU_FLASH_BASE=0x20000000
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=m
+CONFIG_MTD_PHYSMAP_START=0x20000000
+CONFIG_MTD_PHYSMAP_LEN=0x0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
# CONFIG_MTD_UCLINUX is not set
# CONFIG_MTD_PLATRAM is not set
@@ -647,8 +650,8 @@
# CONFIG_SMSC911X is not set
# CONFIG_DM9000 is not set
CONFIG_NETDEV_1000=y
-CONFIG_NETDEV_10000=y
# CONFIG_AX88180 is not set
+CONFIG_NETDEV_10000=y
#
# Wireless LAN
@@ -717,7 +720,6 @@
# CONFIG_BFIN_SPORT is not set
# CONFIG_BFIN_TIMER_LATENCY is not set
# CONFIG_AD5304 is not set
-# CONFIG_BF5xx_FBDMA is not set
# CONFIG_VT is not set
# CONFIG_SERIAL_NONSTANDARD is not set
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
index 8a4cfb2..318b9b6 100644
--- a/arch/blackfin/kernel/Makefile
+++ b/arch/blackfin/kernel/Makefile
@@ -7,7 +7,7 @@
obj-y := \
entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \
sys_bfin.o time.o traps.o irqchip.o dma-mapping.o flat.o \
- fixed_code.o cplbinit.o cacheinit.o reboot.o bfin_gpio.o
+ fixed_code.o reboot.o bfin_gpio.o
obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o
obj-$(CONFIG_MODULES) += module.o
diff --git a/arch/blackfin/kernel/bfin_dma_5xx.c b/arch/blackfin/kernel/bfin_dma_5xx.c
index b544460..fa9debe8 100644
--- a/arch/blackfin/kernel/bfin_dma_5xx.c
+++ b/arch/blackfin/kernel/bfin_dma_5xx.c
@@ -339,13 +339,13 @@
unsigned short
set_bfin_dma_config(char direction, char flow_mode,
- char intr_mode, char dma_mode, char width)
+ char intr_mode, char dma_mode, char width, char syncmode)
{
unsigned short config;
config =
((direction << 1) | (width << 2) | (dma_mode << 4) |
- (intr_mode << 6) | (flow_mode << 12) | RESTART);
+ (intr_mode << 6) | (flow_mode << 12) | (syncmode << 5));
return config;
}
EXPORT_SYMBOL(set_bfin_dma_config);
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index ce85d4b..6bbe0a2 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -7,7 +7,7 @@
* Description: GPIO Abstraction Layer
*
* Modified:
- * Copyright 2007 Analog Devices Inc.
+ * Copyright 2008 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
@@ -83,6 +83,7 @@
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/err.h>
+#include <linux/proc_fs.h>
#include <asm/blackfin.h>
#include <asm/gpio.h>
#include <asm/portmux.h>
@@ -136,7 +137,6 @@
(unsigned short *) PORTG_FER,
(unsigned short *) PORTH_FER,
};
-
#endif
#ifdef BF527_FAMILY
@@ -178,15 +178,13 @@
#endif
static unsigned short reserved_gpio_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
-static unsigned short reserved_peri_map[gpio_bank(MAX_BLACKFIN_GPIOS + 16)];
+static unsigned short reserved_peri_map[gpio_bank(MAX_RESOURCES)];
-#define MAX_RESOURCES 256
#define RESOURCE_LABEL_SIZE 16
-struct str_ident {
+static struct str_ident {
char name[RESOURCE_LABEL_SIZE];
-} *str_ident;
-
+} str_ident[MAX_RESOURCES];
#ifdef CONFIG_PM
static unsigned short wakeup_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
@@ -212,7 +210,7 @@
#endif /* CONFIG_PM */
#if defined(BF548_FAMILY)
-inline int check_gpio(unsigned short gpio)
+inline int check_gpio(unsigned gpio)
{
if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
|| gpio == GPIO_PH14 || gpio == GPIO_PH15
@@ -222,7 +220,7 @@
return 0;
}
#else
-inline int check_gpio(unsigned short gpio)
+inline int check_gpio(unsigned gpio)
{
if (gpio >= MAX_BLACKFIN_GPIOS)
return -EINVAL;
@@ -230,9 +228,13 @@
}
#endif
+void gpio_error(unsigned gpio)
+{
+ printk(KERN_ERR "bfin-gpio: GPIO %d wasn't requested!\n", gpio);
+}
+
static void set_label(unsigned short ident, const char *label)
{
-
if (label && str_ident) {
strncpy(str_ident[ident].name, label,
RESOURCE_LABEL_SIZE);
@@ -250,6 +252,11 @@
static int cmp_label(unsigned short ident, const char *label)
{
+ if (label == NULL) {
+ dump_stack();
+ printk(KERN_ERR "Please provide none-null label\n");
+ }
+
if (label && str_ident)
return strncmp(str_ident[ident].name,
label, strlen(label));
@@ -258,7 +265,7 @@
}
#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
-static void port_setup(unsigned short gpio, unsigned short usage)
+static void port_setup(unsigned gpio, unsigned short usage)
{
if (!check_gpio(gpio)) {
if (usage == GPIO_USAGE)
@@ -269,7 +276,7 @@
}
}
#elif defined(BF548_FAMILY)
-static void port_setup(unsigned short gpio, unsigned short usage)
+static void port_setup(unsigned gpio, unsigned short usage)
{
if (usage == GPIO_USAGE)
gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
@@ -390,7 +397,7 @@
#endif
#ifndef BF548_FAMILY
-static void default_gpio(unsigned short gpio)
+static void default_gpio(unsigned gpio)
{
unsigned short bank, bitmask;
unsigned long flags;
@@ -410,7 +417,6 @@
gpio_bankb[bank]->edge &= ~bitmask;
AWA_DUMMY_READ(edge);
local_irq_restore(flags);
-
}
#else
# define default_gpio(...) do { } while (0)
@@ -418,12 +424,6 @@
static int __init bfin_gpio_init(void)
{
- str_ident = kcalloc(MAX_RESOURCES,
- sizeof(struct str_ident), GFP_KERNEL);
- if (str_ident == NULL)
- return -ENOMEM;
-
- memset(str_ident, 0, MAX_RESOURCES * sizeof(struct str_ident));
printk(KERN_INFO "Blackfin GPIO Controller\n");
@@ -454,10 +454,9 @@
/* Set a specific bit */
#define SET_GPIO(name) \
-void set_gpio_ ## name(unsigned short gpio, unsigned short arg) \
+void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
{ \
unsigned long flags; \
- BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))); \
local_irq_save(flags); \
if (arg) \
gpio_bankb[gpio_bank(gpio)]->name |= gpio_bit(gpio); \
@@ -477,10 +476,9 @@
#if ANOMALY_05000311 || ANOMALY_05000323
#define SET_GPIO_SC(name) \
-void set_gpio_ ## name(unsigned short gpio, unsigned short arg) \
+void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
{ \
unsigned long flags; \
- BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))); \
local_irq_save(flags); \
if (arg) \
gpio_bankb[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
@@ -492,9 +490,8 @@
EXPORT_SYMBOL(set_gpio_ ## name);
#else
#define SET_GPIO_SC(name) \
-void set_gpio_ ## name(unsigned short gpio, unsigned short arg) \
+void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
{ \
- BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))); \
if (arg) \
gpio_bankb[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
else \
@@ -508,19 +505,17 @@
SET_GPIO_SC(data)
#if ANOMALY_05000311 || ANOMALY_05000323
-void set_gpio_toggle(unsigned short gpio)
+void set_gpio_toggle(unsigned gpio)
{
unsigned long flags;
- BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
local_irq_save(flags);
gpio_bankb[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
AWA_DUMMY_READ(toggle);
local_irq_restore(flags);
}
#else
-void set_gpio_toggle(unsigned short gpio)
+void set_gpio_toggle(unsigned gpio)
{
- BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
gpio_bankb[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
}
#endif
@@ -531,7 +526,7 @@
#if ANOMALY_05000311 || ANOMALY_05000323
#define SET_GPIO_P(name) \
-void set_gpiop_ ## name(unsigned short gpio, unsigned short arg) \
+void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \
{ \
unsigned long flags; \
local_irq_save(flags); \
@@ -542,7 +537,7 @@
EXPORT_SYMBOL(set_gpiop_ ## name);
#else
#define SET_GPIO_P(name) \
-void set_gpiop_ ## name(unsigned short gpio, unsigned short arg) \
+void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \
{ \
gpio_bankb[gpio_bank(gpio)]->name = arg; \
} \
@@ -558,11 +553,10 @@
SET_GPIO_P(maska)
SET_GPIO_P(maskb)
-
/* Get a specific bit */
#if ANOMALY_05000311 || ANOMALY_05000323
#define GET_GPIO(name) \
-unsigned short get_gpio_ ## name(unsigned short gpio) \
+unsigned short get_gpio_ ## name(unsigned gpio) \
{ \
unsigned long flags; \
unsigned short ret; \
@@ -575,7 +569,7 @@
EXPORT_SYMBOL(get_gpio_ ## name);
#else
#define GET_GPIO(name) \
-unsigned short get_gpio_ ## name(unsigned short gpio) \
+unsigned short get_gpio_ ## name(unsigned gpio) \
{ \
return (0x01 & (gpio_bankb[gpio_bank(gpio)]->name >> gpio_sub_n(gpio))); \
} \
@@ -595,7 +589,7 @@
#if ANOMALY_05000311 || ANOMALY_05000323
#define GET_GPIO_P(name) \
-unsigned short get_gpiop_ ## name(unsigned short gpio) \
+unsigned short get_gpiop_ ## name(unsigned gpio) \
{ \
unsigned long flags; \
unsigned short ret; \
@@ -608,7 +602,7 @@
EXPORT_SYMBOL(get_gpiop_ ## name);
#else
#define GET_GPIO_P(name) \
-unsigned short get_gpiop_ ## name(unsigned short gpio) \
+unsigned short get_gpiop_ ## name(unsigned gpio) \
{ \
return (gpio_bankb[gpio_bank(gpio)]->name);\
} \
@@ -645,7 +639,7 @@
*************************************************************
* MODIFICATION HISTORY :
**************************************************************/
-int gpio_pm_wakeup_request(unsigned short gpio, unsigned char type)
+int gpio_pm_wakeup_request(unsigned gpio, unsigned char type)
{
unsigned long flags;
@@ -653,7 +647,6 @@
return -EINVAL;
local_irq_save(flags);
-
wakeup_map[gpio_bank(gpio)] |= gpio_bit(gpio);
wakeup_flags_map[gpio] = type;
local_irq_restore(flags);
@@ -662,7 +655,7 @@
}
EXPORT_SYMBOL(gpio_pm_wakeup_request);
-void gpio_pm_wakeup_free(unsigned short gpio)
+void gpio_pm_wakeup_free(unsigned gpio)
{
unsigned long flags;
@@ -677,7 +670,7 @@
}
EXPORT_SYMBOL(gpio_pm_wakeup_free);
-static int bfin_gpio_wakeup_type(unsigned short gpio, unsigned char type)
+static int bfin_gpio_wakeup_type(unsigned gpio, unsigned char type)
{
port_setup(gpio, GPIO_USAGE);
set_gpio_dir(gpio, 0);
@@ -784,6 +777,14 @@
}
#endif
+#else /* BF548_FAMILY */
+
+unsigned short get_gpio_dir(unsigned gpio)
+{
+ return (0x01 & (gpio_array[gpio_bank(gpio)]->port_dir_clear >> gpio_sub_n(gpio)));
+}
+EXPORT_SYMBOL(get_gpio_dir);
+
#endif /* BF548_FAMILY */
/***********************************************************
@@ -1028,7 +1029,7 @@
* MODIFICATION HISTORY :
**************************************************************/
-int gpio_request(unsigned short gpio, const char *label)
+int gpio_request(unsigned gpio, const char *label)
{
unsigned long flags;
@@ -1075,7 +1076,7 @@
}
EXPORT_SYMBOL(gpio_request);
-void gpio_free(unsigned short gpio)
+void gpio_free(unsigned gpio)
{
unsigned long flags;
@@ -1085,7 +1086,7 @@
local_irq_save(flags);
if (unlikely(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
- printk(KERN_ERR "bfin-gpio: GPIO %d wasn't reserved!\n", gpio);
+ gpio_error(gpio);
dump_stack();
local_irq_restore(flags);
return;
@@ -1101,44 +1102,55 @@
}
EXPORT_SYMBOL(gpio_free);
+
#ifdef BF548_FAMILY
-void gpio_direction_input(unsigned short gpio)
+int gpio_direction_input(unsigned gpio)
{
unsigned long flags;
- BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
+ if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
+ gpio_error(gpio);
+ return -EINVAL;
+ }
local_irq_save(flags);
gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio);
gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio);
local_irq_restore(flags);
+
+ return 0;
}
EXPORT_SYMBOL(gpio_direction_input);
-void gpio_direction_output(unsigned short gpio)
+int gpio_direction_output(unsigned gpio, int value)
{
unsigned long flags;
- BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
+ if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
+ gpio_error(gpio);
+ return -EINVAL;
+ }
local_irq_save(flags);
gpio_array[gpio_bank(gpio)]->port_inen &= ~gpio_bit(gpio);
+ gpio_set_value(gpio, value);
gpio_array[gpio_bank(gpio)]->port_dir_set = gpio_bit(gpio);
local_irq_restore(flags);
+
+ return 0;
}
EXPORT_SYMBOL(gpio_direction_output);
-void gpio_set_value(unsigned short gpio, unsigned short arg)
+void gpio_set_value(unsigned gpio, int arg)
{
if (arg)
gpio_array[gpio_bank(gpio)]->port_set = gpio_bit(gpio);
else
gpio_array[gpio_bank(gpio)]->port_clear = gpio_bit(gpio);
-
}
EXPORT_SYMBOL(gpio_set_value);
-unsigned short gpio_get_value(unsigned short gpio)
+int gpio_get_value(unsigned gpio)
{
return (1 & (gpio_array[gpio_bank(gpio)]->port_data >> gpio_sub_n(gpio)));
}
@@ -1146,31 +1158,47 @@
#else
-void gpio_direction_input(unsigned short gpio)
+int gpio_direction_input(unsigned gpio)
{
unsigned long flags;
- BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
+ if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
+ gpio_error(gpio);
+ return -EINVAL;
+ }
local_irq_save(flags);
gpio_bankb[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
gpio_bankb[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
AWA_DUMMY_READ(inen);
local_irq_restore(flags);
+
+ return 0;
}
EXPORT_SYMBOL(gpio_direction_input);
-void gpio_direction_output(unsigned short gpio)
+int gpio_direction_output(unsigned gpio, int value)
{
unsigned long flags;
- BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
+ if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
+ gpio_error(gpio);
+ return -EINVAL;
+ }
local_irq_save(flags);
gpio_bankb[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
+
+ if (value)
+ gpio_bankb[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
+ else
+ gpio_bankb[gpio_bank(gpio)]->data_clear = gpio_bit(gpio);
+
gpio_bankb[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
AWA_DUMMY_READ(dir);
local_irq_restore(flags);
+
+ return 0;
}
EXPORT_SYMBOL(gpio_direction_output);
@@ -1190,7 +1218,40 @@
port_setup(gpio, GPIO_USAGE);
gpio_bankb[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
+ AWA_DUMMY_READ(data_set);
udelay(1);
}
#endif /*BF548_FAMILY */
+
+#if defined(CONFIG_PROC_FS)
+static int gpio_proc_read(char *buf, char **start, off_t offset,
+ int len, int *unused_i, void *unused_v)
+{
+ int c, outlen = 0;
+
+ for (c = 0; c < MAX_RESOURCES; c++) {
+ if (!check_gpio(c) && (reserved_gpio_map[gpio_bank(c)] & gpio_bit(c)))
+ len = sprintf(buf, "GPIO_%d: %s \t\tGPIO %s\n", c,
+ get_label(c), get_gpio_dir(c) ? "OUTPUT" : "INPUT");
+ else if (reserved_peri_map[gpio_bank(c)] & gpio_bit(c))
+ len = sprintf(buf, "GPIO_%d: %s \t\tPeripheral\n", c, get_label(c));
+ else
+ continue;
+ buf += len;
+ outlen += len;
+ }
+ return outlen;
+}
+
+static __init int gpio_register_proc(void)
+{
+ struct proc_dir_entry *proc_gpio;
+
+ proc_gpio = create_proc_entry("gpio", S_IRUGO, NULL);
+ if (proc_gpio)
+ proc_gpio->read_proc = gpio_proc_read;
+ return proc_gpio != NULL;
+}
+__initcall(gpio_register_proc);
+#endif
diff --git a/arch/blackfin/kernel/cplb-mpu/Makefile b/arch/blackfin/kernel/cplb-mpu/Makefile
new file mode 100644
index 0000000..286b693
--- /dev/null
+++ b/arch/blackfin/kernel/cplb-mpu/Makefile
@@ -0,0 +1,8 @@
+#
+# arch/blackfin/kernel/cplb-nompu/Makefile
+#
+
+obj-y := cplbinit.o cacheinit.o cplbmgr.o
+
+obj-$(CONFIG_CPLB_INFO) += cplbinfo.o
+
diff --git a/arch/blackfin/kernel/cacheinit.c b/arch/blackfin/kernel/cplb-mpu/cacheinit.c
similarity index 74%
copy from arch/blackfin/kernel/cacheinit.c
copy to arch/blackfin/kernel/cplb-mpu/cacheinit.c
index 62cbba7..9eecfa4 100644
--- a/arch/blackfin/kernel/cacheinit.c
+++ b/arch/blackfin/kernel/cplb-mpu/cacheinit.c
@@ -27,41 +27,36 @@
#if defined(CONFIG_BFIN_ICACHE)
void bfin_icache_init(void)
{
- unsigned long *table = icplb_table;
unsigned long ctrl;
int i;
+ SSYNC();
for (i = 0; i < MAX_CPLBS; i++) {
- unsigned long addr = *table++;
- unsigned long data = *table++;
- if (addr == (unsigned long)-1)
- break;
- bfin_write32(ICPLB_ADDR0 + i * 4, addr);
- bfin_write32(ICPLB_DATA0 + i * 4, data);
+ bfin_write32(ICPLB_ADDR0 + i * 4, icplb_tbl[i].addr);
+ bfin_write32(ICPLB_DATA0 + i * 4, icplb_tbl[i].data);
}
ctrl = bfin_read_IMEM_CONTROL();
ctrl |= IMC | ENICPLB;
bfin_write_IMEM_CONTROL(ctrl);
+ SSYNC();
}
#endif
#if defined(CONFIG_BFIN_DCACHE)
void bfin_dcache_init(void)
{
- unsigned long *table = dcplb_table;
unsigned long ctrl;
int i;
+ SSYNC();
for (i = 0; i < MAX_CPLBS; i++) {
- unsigned long addr = *table++;
- unsigned long data = *table++;
- if (addr == (unsigned long)-1)
- break;
- bfin_write32(DCPLB_ADDR0 + i * 4, addr);
- bfin_write32(DCPLB_DATA0 + i * 4, data);
+ bfin_write32(DCPLB_ADDR0 + i * 4, dcplb_tbl[i].addr);
+ bfin_write32(DCPLB_DATA0 + i * 4, dcplb_tbl[i].data);
}
+
ctrl = bfin_read_DMEM_CONTROL();
ctrl |= DMEM_CNTR;
bfin_write_DMEM_CONTROL(ctrl);
+ SSYNC();
}
#endif
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbinfo.c b/arch/blackfin/kernel/cplb-mpu/cplbinfo.c
new file mode 100644
index 0000000..bd07229
--- /dev/null
+++ b/arch/blackfin/kernel/cplb-mpu/cplbinfo.c
@@ -0,0 +1,144 @@
+/*
+ * File: arch/blackfin/mach-common/cplbinfo.c
+ * Based on:
+ * Author: Sonic Zhang <sonic.zhang@analog.com>
+ *
+ * Created: Jan. 2005
+ * Description: Display CPLB status
+ *
+ * Modified:
+ * Copyright 2004-2006 Analog Devices Inc.
+ *
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/proc_fs.h>
+#include <linux/uaccess.h>
+
+#include <asm/current.h>
+#include <asm/system.h>
+#include <asm/cplb.h>
+#include <asm/cplbinit.h>
+#include <asm/blackfin.h>
+
+#define CPLB_I 1
+#define CPLB_D 2
+
+#define SYNC_SYS SSYNC()
+#define SYNC_CORE CSYNC()
+
+#define CPLB_BIT_PAGESIZE 0x30000
+
+static char page_size_string_table[][4] = { "1K", "4K", "1M", "4M" };
+
+static char *cplb_print_entry(char *buf, struct cplb_entry *tbl, int switched)
+{
+ int i;
+ buf += sprintf(buf, "Index\tAddress\t\tData\tSize\tU/RD\tU/WR\tS/WR\tSwitch\n");
+ for (i = 0; i < MAX_CPLBS; i++) {
+ unsigned long data = tbl[i].data;
+ unsigned long addr = tbl[i].addr;
+ if (!(data & CPLB_VALID))
+ continue;
+
+ buf +=
+ sprintf(buf,
+ "%d\t0x%08lx\t%06lx\t%s\t%c\t%c\t%c\t%c\n",
+ i, addr, data,
+ page_size_string_table[(data & 0x30000) >> 16],
+ (data & CPLB_USER_RD) ? 'Y' : 'N',
+ (data & CPLB_USER_WR) ? 'Y' : 'N',
+ (data & CPLB_SUPV_WR) ? 'Y' : 'N',
+ i < switched ? 'N' : 'Y');
+ }
+ buf += sprintf(buf, "\n");
+
+ return buf;
+}
+
+int cplbinfo_proc_output(char *buf)
+{
+ char *p;
+
+ p = buf;
+
+ p += sprintf(p, "------------------ CPLB Information ------------------\n\n");
+
+ if (bfin_read_IMEM_CONTROL() & ENICPLB) {
+ p += sprintf(p, "Instruction CPLB entry:\n");
+ p = cplb_print_entry(p, icplb_tbl, first_switched_icplb);
+ } else
+ p += sprintf(p, "Instruction CPLB is disabled.\n\n");
+
+ if (1 || bfin_read_DMEM_CONTROL() & ENDCPLB) {
+ p += sprintf(p, "Data CPLB entry:\n");
+ p = cplb_print_entry(p, dcplb_tbl, first_switched_dcplb);
+ } else
+ p += sprintf(p, "Data CPLB is disabled.\n");
+
+ p += sprintf(p, "ICPLB miss: %d\nICPLB supervisor miss: %d\n",
+ nr_icplb_miss, nr_icplb_supv_miss);
+ p += sprintf(p, "DCPLB miss: %d\nDCPLB protection fault:%d\n",
+ nr_dcplb_miss, nr_dcplb_prot);
+ p += sprintf(p, "CPLB flushes: %d\n",
+ nr_cplb_flush);
+
+ return p - buf;
+}
+
+static int cplbinfo_read_proc(char *page, char **start, off_t off,
+ int count, int *eof, void *data)
+{
+ int len;
+
+ len = cplbinfo_proc_output(page);
+ if (len <= off + count)
+ *eof = 1;
+ *start = page + off;
+ len -= off;
+ if (len > count)
+ len = count;
+ if (len < 0)
+ len = 0;
+ return len;
+}
+
+static int __init cplbinfo_init(void)
+{
+ struct proc_dir_entry *entry;
+
+ entry = create_proc_entry("cplbinfo", 0, NULL);
+ if (!entry)
+ return -ENOMEM;
+
+ entry->read_proc = cplbinfo_read_proc;
+ entry->data = NULL;
+
+ return 0;
+}
+
+static void __exit cplbinfo_exit(void)
+{
+ remove_proc_entry("cplbinfo", NULL);
+}
+
+module_init(cplbinfo_init);
+module_exit(cplbinfo_exit);
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbinit.c b/arch/blackfin/kernel/cplb-mpu/cplbinit.c
new file mode 100644
index 0000000..e2e2b50
--- /dev/null
+++ b/arch/blackfin/kernel/cplb-mpu/cplbinit.c
@@ -0,0 +1,91 @@
+/*
+ * Blackfin CPLB initialization
+ *
+ * Copyright 2004-2007 Analog Devices Inc.
+ *
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include <linux/module.h>
+
+#include <asm/blackfin.h>
+#include <asm/cplb.h>
+#include <asm/cplbinit.h>
+
+struct cplb_entry icplb_tbl[MAX_CPLBS];
+struct cplb_entry dcplb_tbl[MAX_CPLBS];
+
+int first_switched_icplb, first_switched_dcplb;
+int first_mask_dcplb;
+
+void __init generate_cpl_tables(void)
+{
+ int i_d, i_i;
+ unsigned long addr;
+ unsigned long d_data, i_data;
+ unsigned long d_cache = 0, i_cache = 0;
+
+#ifdef CONFIG_BFIN_ICACHE
+ i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
+#endif
+
+#ifdef CONFIG_BFIN_DCACHE
+ d_cache = CPLB_L1_CHBL;
+#ifdef CONFIG_BLKFIN_WT
+ d_cache |= CPLB_L1_AOW | CPLB_WT;
+#endif
+#endif
+ i_d = i_i = 0;
+
+ /* Set up the zero page. */
+ dcplb_tbl[i_d].addr = 0;
+ dcplb_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
+
+#if 0
+ icplb_tbl[i_i].addr = 0;
+ icplb_tbl[i_i++].data = i_cache | CPLB_USER_RD | PAGE_SIZE_4KB;
+#endif
+
+ /* Cover kernel memory with 4M pages. */
+ addr = 0;
+ d_data = d_cache | CPLB_SUPV_WR | CPLB_VALID | PAGE_SIZE_4MB | CPLB_DIRTY;
+ i_data = i_cache | CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4MB;
+
+ for (; addr < memory_start; addr += 4 * 1024 * 1024) {
+ dcplb_tbl[i_d].addr = addr;
+ dcplb_tbl[i_d++].data = d_data;
+ icplb_tbl[i_i].addr = addr;
+ icplb_tbl[i_i++].data = i_data | (addr == 0 ? CPLB_USER_RD : 0);
+ }
+
+ /* Cover L1 memory. One 4M area for code and data each is enough. */
+#if L1_DATA_A_LENGTH > 0 || L1_DATA_B_LENGTH > 0
+ dcplb_tbl[i_d].addr = L1_DATA_A_START;
+ dcplb_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
+#endif
+ icplb_tbl[i_i].addr = L1_CODE_START;
+ icplb_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
+
+ first_mask_dcplb = i_d;
+ first_switched_dcplb = i_d + (1 << page_mask_order);
+ first_switched_icplb = i_i;
+
+ while (i_d < MAX_CPLBS)
+ dcplb_tbl[i_d++].data = 0;
+ while (i_i < MAX_CPLBS)
+ icplb_tbl[i_i++].data = 0;
+}
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
new file mode 100644
index 0000000..c426a22
--- /dev/null
+++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
@@ -0,0 +1,338 @@
+/*
+ * Blackfin CPLB exception handling.
+ * Copyright 2004-2007 Analog Devices Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include <linux/module.h>
+#include <linux/mm.h>
+
+#include <asm/blackfin.h>
+#include <asm/cplbinit.h>
+#include <asm/mmu_context.h>
+
+#ifdef CONFIG_BFIN_ICACHE
+
+#define FAULT_RW (1 << 16)
+#define FAULT_USERSUPV (1 << 17)
+
+int page_mask_nelts;
+int page_mask_order;
+unsigned long *current_rwx_mask;
+
+int nr_dcplb_miss, nr_icplb_miss, nr_icplb_supv_miss, nr_dcplb_prot;
+int nr_cplb_flush;
+
+static inline void disable_dcplb(void)
+{
+ unsigned long ctrl;
+ SSYNC();
+ ctrl = bfin_read_DMEM_CONTROL();
+ ctrl &= ~ENDCPLB;
+ bfin_write_DMEM_CONTROL(ctrl);
+ SSYNC();
+}
+
+static inline void enable_dcplb(void)
+{
+ unsigned long ctrl;
+ SSYNC();
+ ctrl = bfin_read_DMEM_CONTROL();
+ ctrl |= ENDCPLB;
+ bfin_write_DMEM_CONTROL(ctrl);
+ SSYNC();
+}
+
+static inline void disable_icplb(void)
+{
+ unsigned long ctrl;
+ SSYNC();
+ ctrl = bfin_read_IMEM_CONTROL();
+ ctrl &= ~ENICPLB;
+ bfin_write_IMEM_CONTROL(ctrl);
+ SSYNC();
+}
+
+static inline void enable_icplb(void)
+{
+ unsigned long ctrl;
+ SSYNC();
+ ctrl = bfin_read_IMEM_CONTROL();
+ ctrl |= ENICPLB;
+ bfin_write_IMEM_CONTROL(ctrl);
+ SSYNC();
+}
+
+/*
+ * Given the contents of the status register, return the index of the
+ * CPLB that caused the fault.
+ */
+static inline int faulting_cplb_index(int status)
+{
+ int signbits = __builtin_bfin_norm_fr1x32(status & 0xFFFF);
+ return 30 - signbits;
+}
+
+/*
+ * Given the contents of the status register and the DCPLB_DATA contents,
+ * return true if a write access should be permitted.
+ */
+static inline int write_permitted(int status, unsigned long data)
+{
+ if (status & FAULT_USERSUPV)
+ return !!(data & CPLB_SUPV_WR);
+ else
+ return !!(data & CPLB_USER_WR);
+}
+
+/* Counters to implement round-robin replacement. */
+static int icplb_rr_index, dcplb_rr_index;
+
+/*
+ * Find an ICPLB entry to be evicted and return its index.
+ */
+static int evict_one_icplb(void)
+{
+ int i;
+ for (i = first_switched_icplb; i < MAX_CPLBS; i++)
+ if ((icplb_tbl[i].data & CPLB_VALID) == 0)
+ return i;
+ i = first_switched_icplb + icplb_rr_index;
+ if (i >= MAX_CPLBS) {
+ i -= MAX_CPLBS - first_switched_icplb;
+ icplb_rr_index -= MAX_CPLBS - first_switched_icplb;
+ }
+ icplb_rr_index++;
+ return i;
+}
+
+static int evict_one_dcplb(void)
+{
+ int i;
+ for (i = first_switched_dcplb; i < MAX_CPLBS; i++)
+ if ((dcplb_tbl[i].data & CPLB_VALID) == 0)
+ return i;
+ i = first_switched_dcplb + dcplb_rr_index;
+ if (i >= MAX_CPLBS) {
+ i -= MAX_CPLBS - first_switched_dcplb;
+ dcplb_rr_index -= MAX_CPLBS - first_switched_dcplb;
+ }
+ dcplb_rr_index++;
+ return i;
+}
+
+static noinline int dcplb_miss(void)
+{
+ unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
+ int status = bfin_read_DCPLB_STATUS();
+ unsigned long *mask;
+ int idx;
+ unsigned long d_data;
+
+ nr_dcplb_miss++;
+ if (addr >= _ramend)
+ return CPLB_PROT_VIOL;
+
+ d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
+#ifdef CONFIG_BFIN_DCACHE
+ d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
+#ifdef CONFIG_BLKFIN_WT
+ d_data |= CPLB_L1_AOW | CPLB_WT;
+#endif
+#endif
+ mask = current_rwx_mask;
+ if (mask) {
+ int page = addr >> PAGE_SHIFT;
+ int offs = page >> 5;
+ int bit = 1 << (page & 31);
+
+ if (mask[offs] & bit)
+ d_data |= CPLB_USER_RD;
+
+ mask += page_mask_nelts;
+ if (mask[offs] & bit)
+ d_data |= CPLB_USER_WR;
+ }
+
+ idx = evict_one_dcplb();
+
+ addr &= PAGE_MASK;
+ dcplb_tbl[idx].addr = addr;
+ dcplb_tbl[idx].data = d_data;
+
+ disable_dcplb();
+ bfin_write32(DCPLB_DATA0 + idx * 4, d_data);
+ bfin_write32(DCPLB_ADDR0 + idx * 4, addr);
+ enable_dcplb();
+
+ return 0;
+}
+
+static noinline int icplb_miss(void)
+{
+ unsigned long addr = bfin_read_ICPLB_FAULT_ADDR();
+ int status = bfin_read_ICPLB_STATUS();
+ int idx;
+ unsigned long i_data;
+
+ nr_icplb_miss++;
+ if (status & FAULT_USERSUPV)
+ nr_icplb_supv_miss++;
+
+ if (addr >= _ramend)
+ return CPLB_PROT_VIOL;
+
+ /*
+ * First, try to find a CPLB that matches this address. If we
+ * find one, then the fact that we're in the miss handler means
+ * that the instruction crosses a page boundary.
+ */
+ for (idx = first_switched_icplb; idx < MAX_CPLBS; idx++) {
+ if (icplb_tbl[idx].data & CPLB_VALID) {
+ unsigned long this_addr = icplb_tbl[idx].addr;
+ if (this_addr <= addr && this_addr + PAGE_SIZE > addr) {
+ addr += PAGE_SIZE;
+ break;
+ }
+ }
+ }
+
+ i_data = CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4KB;
+#ifdef CONFIG_BFIN_ICACHE
+ i_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
+#endif
+
+ /*
+ * Two cases to distinguish - a supervisor access must necessarily
+ * be for a module page; we grant it unconditionally (could do better
+ * here in the future). Otherwise, check the x bitmap of the current
+ * process.
+ */
+ if (!(status & FAULT_USERSUPV)) {
+ unsigned long *mask = current_rwx_mask;
+
+ if (mask) {
+ int page = addr >> PAGE_SHIFT;
+ int offs = page >> 5;
+ int bit = 1 << (page & 31);
+
+ mask += 2 * page_mask_nelts;
+ if (mask[offs] & bit)
+ i_data |= CPLB_USER_RD;
+ }
+ }
+
+ idx = evict_one_icplb();
+ addr &= PAGE_MASK;
+ icplb_tbl[idx].addr = addr;
+ icplb_tbl[idx].data = i_data;
+
+ disable_icplb();
+ bfin_write32(ICPLB_DATA0 + idx * 4, i_data);
+ bfin_write32(ICPLB_ADDR0 + idx * 4, addr);
+ enable_icplb();
+
+ return 0;
+}
+
+static noinline int dcplb_protection_fault(void)
+{
+ unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
+ int status = bfin_read_DCPLB_STATUS();
+
+ nr_dcplb_prot++;
+
+ if (status & FAULT_RW) {
+ int idx = faulting_cplb_index(status);
+ unsigned long data = dcplb_tbl[idx].data;
+ if (!(data & CPLB_WT) && !(data & CPLB_DIRTY) &&
+ write_permitted(status, data)) {
+ data |= CPLB_DIRTY;
+ dcplb_tbl[idx].data = data;
+ bfin_write32(DCPLB_DATA0 + idx * 4, data);
+ return 0;
+ }
+ }
+ return CPLB_PROT_VIOL;
+}
+
+int cplb_hdr(int seqstat, struct pt_regs *regs)
+{
+ int cause = seqstat & 0x3f;
+ switch (cause) {
+ case 0x23:
+ return dcplb_protection_fault();
+ case 0x2C:
+ return icplb_miss();
+ case 0x26:
+ return dcplb_miss();
+ default:
+ return 1;
+ panic_cplb_error(seqstat, regs);
+ }
+}
+
+void flush_switched_cplbs(void)
+{
+ int i;
+
+ nr_cplb_flush++;
+
+ disable_icplb();
+ for (i = first_switched_icplb; i < MAX_CPLBS; i++) {
+ icplb_tbl[i].data = 0;
+ bfin_write32(ICPLB_DATA0 + i * 4, 0);
+ }
+ enable_icplb();
+
+ disable_dcplb();
+ for (i = first_mask_dcplb; i < MAX_CPLBS; i++) {
+ dcplb_tbl[i].data = 0;
+ bfin_write32(DCPLB_DATA0 + i * 4, 0);
+ }
+ enable_dcplb();
+}
+
+void set_mask_dcplbs(unsigned long *masks)
+{
+ int i;
+ unsigned long addr = (unsigned long)masks;
+ unsigned long d_data;
+ current_rwx_mask = masks;
+
+ if (!masks)
+ return;
+
+ d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
+#ifdef CONFIG_BFIN_DCACHE
+ d_data |= CPLB_L1_CHBL;
+#ifdef CONFIG_BLKFIN_WT
+ d_data |= CPLB_L1_AOW | CPLB_WT;
+#endif
+#endif
+
+ disable_dcplb();
+ for (i = first_mask_dcplb; i < first_switched_dcplb; i++) {
+ dcplb_tbl[i].addr = addr;
+ dcplb_tbl[i].data = d_data;
+ bfin_write32(DCPLB_DATA0 + i * 4, d_data);
+ bfin_write32(DCPLB_ADDR0 + i * 4, addr);
+ addr += PAGE_SIZE;
+ }
+ enable_dcplb();
+}
+
+#endif
diff --git a/arch/blackfin/kernel/cplb-nompu/Makefile b/arch/blackfin/kernel/cplb-nompu/Makefile
new file mode 100644
index 0000000..d36ea9b
--- /dev/null
+++ b/arch/blackfin/kernel/cplb-nompu/Makefile
@@ -0,0 +1,8 @@
+#
+# arch/blackfin/kernel/cplb-nompu/Makefile
+#
+
+obj-y := cplbinit.o cacheinit.o cplbhdlr.o cplbmgr.o
+
+obj-$(CONFIG_CPLB_INFO) += cplbinfo.o
+
diff --git a/arch/blackfin/kernel/cacheinit.c b/arch/blackfin/kernel/cplb-nompu/cacheinit.c
similarity index 98%
rename from arch/blackfin/kernel/cacheinit.c
rename to arch/blackfin/kernel/cplb-nompu/cacheinit.c
index 62cbba7..8a18399 100644
--- a/arch/blackfin/kernel/cacheinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cacheinit.c
@@ -42,6 +42,7 @@
ctrl = bfin_read_IMEM_CONTROL();
ctrl |= IMC | ENICPLB;
bfin_write_IMEM_CONTROL(ctrl);
+ SSYNC();
}
#endif
@@ -63,5 +64,6 @@
ctrl = bfin_read_DMEM_CONTROL();
ctrl |= DMEM_CNTR;
bfin_write_DMEM_CONTROL(ctrl);
+ SSYNC();
}
#endif
diff --git a/arch/blackfin/mach-common/cplbhdlr.S b/arch/blackfin/kernel/cplb-nompu/cplbhdlr.S
similarity index 100%
rename from arch/blackfin/mach-common/cplbhdlr.S
rename to arch/blackfin/kernel/cplb-nompu/cplbhdlr.S
diff --git a/arch/blackfin/mach-common/cplbinfo.c b/arch/blackfin/kernel/cplb-nompu/cplbinfo.c
similarity index 100%
rename from arch/blackfin/mach-common/cplbinfo.c
rename to arch/blackfin/kernel/cplb-nompu/cplbinfo.c
diff --git a/arch/blackfin/kernel/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
similarity index 100%
rename from arch/blackfin/kernel/cplbinit.c
rename to arch/blackfin/kernel/cplb-nompu/cplbinit.c
diff --git a/arch/blackfin/mach-common/cplbmgr.S b/arch/blackfin/kernel/cplb-nompu/cplbmgr.S
similarity index 93%
rename from arch/blackfin/mach-common/cplbmgr.S
rename to arch/blackfin/kernel/cplb-nompu/cplbmgr.S
index 6f909cb..f5cf3ac 100644
--- a/arch/blackfin/mach-common/cplbmgr.S
+++ b/arch/blackfin/kernel/cplb-nompu/cplbmgr.S
@@ -75,6 +75,15 @@
* from the configuration table.
*/
+ /* A multi-word instruction can cross a page boundary. This means the
+ * first part of the instruction can be in a valid page, but the
+ * second part is not, and hence generates the instruction miss.
+ * However, the fault address is for the start of the instruction,
+ * not the part that's in the bad page. Therefore, we have to check
+ * whether the fault address applies to a page that is already present
+ * in the table.
+ */
+
P4.L = LO(ICPLB_FAULT_ADDR);
P4.H = HI(ICPLB_FAULT_ADDR);
@@ -87,7 +96,7 @@
R4 = [P4]; /* Get faulting address*/
R6 = 64; /* Advance past the fault address, which*/
R6 = R6 + R4; /* we'll use if we find a match*/
- R3 = ((16 << 8) | 2); /* Extract mask, bits 16 and 17.*/
+ R3 = ((16 << 8) | 2); /* Extract mask, two bits at posn 16 */
R5 = 0;
.Lisearch:
@@ -125,7 +134,9 @@
P4.L = LO(IMEM_CONTROL);
P4.H = HI(IMEM_CONTROL);
- /* disable cplbs */
+ /* Turn off CPLBs while we work, necessary according to HRM before
+ * modifying CPLB descriptors
+ */
R5 = [P4]; /* Control Register*/
BITCLR(R5,ENICPLB_P);
CLI R1;
@@ -179,7 +190,14 @@
[P0 - 4] = R0;
R0 = [P0 - 0x100];
[P0-0x104] = R0;
-.Lie_move:P0+=4;
+.Lie_move:
+ P0+=4;
+
+ /* Clear ICPLB_DATA15, in case we don't find a replacement
+ * otherwise, we would have a duplicate entry, and will crash
+ */
+ R0 = 0;
+ [P0 - 4] = R0;
/* We've made space in the ICPLB table, so that ICPLB15
* is now free to be overwritten. Next, we have to determine
@@ -504,14 +522,23 @@
R0 = [P0++]; /* move data */
[P0 - 8] = R0;
R0 = [P0-0x104] /* move address */
-.Lde_move: [P0-0x108] = R0;
+.Lde_move:
+ [P0-0x108] = R0;
+
+.Lde_moved:
+ NOP;
+
+ /* Clear DCPLB_DATA15, in case we don't find a replacement
+ * otherwise, we would have a duplicate entry, and will crash
+ */
+ R0 = 0;
+ [P0 - 0x4] = R0;
/* We've now made space in DCPLB15 for the new CPLB to be
* installed. The next stage is to locate a CPLB in the
* config table that covers the faulting address.
*/
-.Lde_moved:NOP;
R0 = I0; /* Our faulting address */
P2.L = _dpdt_table;
diff --git a/arch/blackfin/kernel/early_printk.c b/arch/blackfin/kernel/early_printk.c
index 724f4a5..60f67f9 100644
--- a/arch/blackfin/kernel/early_printk.c
+++ b/arch/blackfin/kernel/early_printk.c
@@ -187,7 +187,7 @@
bfin_write_EVT15(early_trap);
CSYNC();
- /* Set all the return from interupt, exception, NMI to a known place
+ /* Set all the return from interrupt, exception, NMI to a known place
* so if we do a RETI, RETX or RETN by mistake - we go somewhere known
* Note - don't change RETS - we are in a subroutine, or
* RETE - since it might screw up if emulator is attached
@@ -205,7 +205,7 @@
if (likely(early_console == NULL))
setup_early_printk(DEFAULT_EARLY_PORT);
- dump_bfin_mem((void *)fp->retx);
+ dump_bfin_mem(fp);
show_regs(fp);
dump_bfin_trace_buffer();
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c
index 5bf1512..023dc80 100644
--- a/arch/blackfin/kernel/process.c
+++ b/arch/blackfin/kernel/process.c
@@ -39,9 +39,6 @@
#include <asm/blackfin.h>
#include <asm/fixed_code.h>
-#define LED_ON 0
-#define LED_OFF 1
-
asmlinkage void ret_from_fork(void);
/* Points to the SDRAM backup memory for the stack that is currently in
@@ -70,32 +67,6 @@
EXPORT_SYMBOL(pm_power_off);
/*
- * We are using a different LED from the one used to indicate timer interrupt.
- */
-#if defined(CONFIG_BFIN_IDLE_LED)
-static inline void leds_switch(int flag)
-{
- unsigned short tmp = 0;
-
- tmp = bfin_read_CONFIG_BFIN_IDLE_LED_PORT();
- SSYNC();
-
- if (flag == LED_ON)
- tmp &= ~CONFIG_BFIN_IDLE_LED_PIN; /* light on */
- else
- tmp |= CONFIG_BFIN_IDLE_LED_PIN; /* light off */
-
- bfin_write_CONFIG_BFIN_IDLE_LED_PORT(tmp);
- SSYNC();
-
-}
-#else
-static inline void leds_switch(int flag)
-{
-}
-#endif
-
-/*
* The idle loop on BFIN
*/
#ifdef CONFIG_IDLE_L1
@@ -106,12 +77,10 @@
void default_idle(void)
{
while (!need_resched()) {
- leds_switch(LED_OFF);
local_irq_disable();
if (likely(!need_resched()))
idle_with_irq_disabled();
local_irq_enable();
- leds_switch(LED_ON);
}
}
@@ -327,6 +296,7 @@
}
#if defined(CONFIG_ACCESS_CHECK)
+/* Return 1 if access to memory range is OK, 0 otherwise */
int _access_ok(unsigned long addr, unsigned long size)
{
if (size == 0)
diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c
index ae28aac..483f93d 100644
--- a/arch/blackfin/kernel/reboot.c
+++ b/arch/blackfin/kernel/reboot.c
@@ -19,6 +19,11 @@
#define SYSCR_VAL 0x10
#endif
+/*
+ * Delay min 5 SCLK cycles using worst case CCLK/SCLK ratio (15)
+ */
+#define SWRST_DELAY (5 * 15)
+
/* A system soft reset makes external memory unusable
* so force this function into L1.
*/
@@ -34,7 +39,13 @@
while (1) {
/* initiate system soft reset with magic 0x7 */
bfin_write_SWRST(0x7);
- asm("ssync;");
+
+ /* Wait for System reset to actually reset, needs to be 5 SCLKs, */
+ /* Assume CCLK / SCLK ratio is worst case (15), and use 5*15 */
+
+ asm("LSETUP(.Lfoo,.Lfoo) LC0 = %0\n .Lfoo: NOP;\n"
+ : : "a" (SWRST_DELAY) : "LC0", "LT0", "LB0");
+
/* clear system soft reset */
bfin_write_SWRST(0);
asm("ssync;");
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index d282201..462cae8 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -238,7 +238,13 @@
memory_end = _ramend - DMA_UNCACHED_REGION;
_ramstart = (unsigned long)__bss_stop;
+ _rambase = (unsigned long)_stext;
+#ifdef CONFIG_MPU
+ /* Round up to multiple of 4MB. */
+ memory_start = (_ramstart + 0x3fffff) & ~0x3fffff;
+#else
memory_start = PAGE_ALIGN(_ramstart);
+#endif
#if defined(CONFIG_MTD_UCLINUX)
/* generic memory mapped MTD driver */
@@ -307,6 +313,11 @@
printk(KERN_NOTICE "Warning: limiting memory to %liMB due to hardware anomaly 05000263\n", memory_end >> 20);
#endif /* ANOMALY_05000263 */
+#ifdef CONFIG_MPU
+ page_mask_nelts = ((_ramend >> PAGE_SHIFT) + 31) / 32;
+ page_mask_order = get_order(3 * page_mask_nelts * sizeof(long));
+#endif
+
#if !defined(CONFIG_MTD_UCLINUX)
memory_end -= SIZE_4K; /*In case there is no valid CPLB behind memory_end make sure we don't get to close*/
#endif
@@ -315,8 +326,6 @@
init_mm.end_data = (unsigned long)_edata;
init_mm.brk = (unsigned long)0;
- init_leds();
-
_bfin_swrst = bfin_read_SWRST();
if (_bfin_swrst & RESET_DOUBLE)
diff --git a/arch/blackfin/kernel/time.c b/arch/blackfin/kernel/time.c
index beef057..5bd64e3 100644
--- a/arch/blackfin/kernel/time.c
+++ b/arch/blackfin/kernel/time.c
@@ -42,75 +42,6 @@
static void time_sched_init(irqreturn_t(*timer_routine)
(int, void *));
static unsigned long gettimeoffset(void);
-static inline void do_leds(void);
-
-#if (defined(CONFIG_BFIN_ALIVE_LED) || defined(CONFIG_BFIN_IDLE_LED))
-void __init init_leds(void)
-{
- unsigned int tmp = 0;
-
-#if defined(CONFIG_BFIN_ALIVE_LED)
- /* config pins as output. */
- tmp = bfin_read_CONFIG_BFIN_ALIVE_LED_DPORT();
- SSYNC();
- bfin_write_CONFIG_BFIN_ALIVE_LED_DPORT(tmp | CONFIG_BFIN_ALIVE_LED_PIN);
- SSYNC();
-
- /* First set led be off */
- tmp = bfin_read_CONFIG_BFIN_ALIVE_LED_PORT();
- SSYNC();
- bfin_write_CONFIG_BFIN_ALIVE_LED_PORT(tmp | CONFIG_BFIN_ALIVE_LED_PIN); /* light off */
- SSYNC();
-#endif
-
-#if defined(CONFIG_BFIN_IDLE_LED)
- /* config pins as output. */
- tmp = bfin_read_CONFIG_BFIN_IDLE_LED_DPORT();
- SSYNC();
- bfin_write_CONFIG_BFIN_IDLE_LED_DPORT(tmp | CONFIG_BFIN_IDLE_LED_PIN);
- SSYNC();
-
- /* First set led be off */
- tmp = bfin_read_CONFIG_BFIN_IDLE_LED_PORT();
- SSYNC();
- bfin_write_CONFIG_BFIN_IDLE_LED_PORT(tmp | CONFIG_BFIN_IDLE_LED_PIN); /* light off */
- SSYNC();
-#endif
-}
-#else
-void __init init_leds(void)
-{
-}
-#endif
-
-#if defined(CONFIG_BFIN_ALIVE_LED)
-static inline void do_leds(void)
-{
- static unsigned int count = 50;
- static int flag;
- unsigned short tmp = 0;
-
- if (--count == 0) {
- count = 50;
- flag = ~flag;
- }
- tmp = bfin_read_CONFIG_BFIN_ALIVE_LED_PORT();
- SSYNC();
-
- if (flag)
- tmp &= ~CONFIG_BFIN_ALIVE_LED_PIN; /* light on */
- else
- tmp |= CONFIG_BFIN_ALIVE_LED_PIN; /* light off */
-
- bfin_write_CONFIG_BFIN_ALIVE_LED_PORT(tmp);
- SSYNC();
-
-}
-#else
-static inline void do_leds(void)
-{
-}
-#endif
static struct irqaction bfin_timer_irq = {
.name = "BFIN Timer Tick",
@@ -205,7 +136,6 @@
write_seqlock(&xtime_lock);
do_timer(1);
- do_leds();
#ifndef CONFIG_SMP
update_process_times(user_mode(get_irq_regs()));
diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c
index 21a55ef..66b5f3e 100644
--- a/arch/blackfin/kernel/traps.c
+++ b/arch/blackfin/kernel/traps.c
@@ -36,8 +36,10 @@
#include <asm/cacheflush.h>
#include <asm/blackfin.h>
#include <asm/irq_handler.h>
+#include <linux/irq.h>
#include <asm/trace.h>
#include <asm/fixed_code.h>
+#include <asm/dma.h>
#ifdef CONFIG_KGDB
# include <linux/debugger.h>
@@ -170,7 +172,7 @@
oops_in_progress = 1;
printk(KERN_EMERG "\n" KERN_EMERG "Double Fault\n");
dump_bfin_process(fp);
- dump_bfin_mem((void *)fp->retx);
+ dump_bfin_mem(fp);
show_regs(fp);
panic("Double Fault - unrecoverable event\n");
@@ -195,9 +197,13 @@
* we will kernel panic, so the system reboots.
* If KGDB is enabled, don't set this for kernel breakpoints
*/
- if ((bfin_read_IPEND() & 0xFFC0)
+
+ /* TODO: check to see if we are in some sort of deferred HWERR
+ * that we should be able to recover from, not kernel panic
+ */
+ if ((bfin_read_IPEND() & 0xFFC0) && (trapnr != VEC_STEP)
#ifdef CONFIG_KGDB
- && trapnr != VEC_EXCPT02
+ && (trapnr != VEC_EXCPT02)
#endif
){
console_verbose();
@@ -433,6 +439,36 @@
/* 0x3D - Reserved, Caught by default */
/* 0x3E - Reserved, Caught by default */
/* 0x3F - Reserved, Caught by default */
+ case VEC_HWERR:
+ info.si_code = BUS_ADRALN;
+ sig = SIGBUS;
+ switch (fp->seqstat & SEQSTAT_HWERRCAUSE) {
+ /* System MMR Error */
+ case (SEQSTAT_HWERRCAUSE_SYSTEM_MMR):
+ info.si_code = BUS_ADRALN;
+ sig = SIGBUS;
+ printk(KERN_NOTICE HWC_x2(KERN_NOTICE));
+ break;
+ /* External Memory Addressing Error */
+ case (SEQSTAT_HWERRCAUSE_EXTERN_ADDR):
+ info.si_code = BUS_ADRERR;
+ sig = SIGBUS;
+ printk(KERN_NOTICE HWC_x3(KERN_NOTICE));
+ break;
+ /* Performance Monitor Overflow */
+ case (SEQSTAT_HWERRCAUSE_PERF_FLOW):
+ printk(KERN_NOTICE HWC_x12(KERN_NOTICE));
+ break;
+ /* RAISE 5 instruction */
+ case (SEQSTAT_HWERRCAUSE_RAISE_5):
+ printk(KERN_NOTICE HWC_x18(KERN_NOTICE));
+ break;
+ default: /* Reserved */
+ printk(KERN_NOTICE HWC_default(KERN_NOTICE));
+ break;
+ }
+ CHK_DEBUGGER_TRAP();
+ break;
default:
info.si_code = TRAP_ILLTRAP;
sig = SIGTRAP;
@@ -447,7 +483,7 @@
if (sig != SIGTRAP) {
unsigned long stack;
dump_bfin_process(fp);
- dump_bfin_mem((void *)fp->retx);
+ dump_bfin_mem(fp);
show_regs(fp);
/* Print out the trace buffer if it makes sense */
@@ -461,6 +497,7 @@
dump_bfin_trace_buffer();
show_stack(current, &stack);
if (oops_in_progress) {
+ print_modules();
#ifndef CONFIG_ACCESS_CHECK
printk(KERN_EMERG "Please turn on "
"CONFIG_ACCESS_CHECK\n");
@@ -474,13 +511,6 @@
info.si_addr = (void *)fp->pc;
force_sig_info(sig, &info, current);
- /* Ensure that bad return addresses don't end up in an infinite
- * loop, due to speculative loads/reads. This needs to be done after
- * the signal has been sent.
- */
- if (trapnr == VEC_CPLB_I_M && sig != SIGTRAP)
- fp->pc = SAFE_USER_INSTRUCTION;
-
trace_buffer_restore(j);
return;
}
@@ -616,8 +646,10 @@
if (oops_in_progress)
printk(KERN_EMERG "Kernel OOPS in progress\n");
- if (context & 0x0020)
- printk(KERN_NOTICE "Deferred excecption or HW Error context\n");
+ if (context & 0x0020 && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR)
+ printk(KERN_NOTICE "HW Error context\n");
+ else if (context & 0x0020)
+ printk(KERN_NOTICE "Defered Exception context\n");
else if (context & 0x3FC0)
printk(KERN_NOTICE "Interrupt context\n");
else if (context & 0x4000)
@@ -645,59 +677,124 @@
"No Valid process in current context\n");
}
-void dump_bfin_mem(void *retaddr)
+void dump_bfin_mem(struct pt_regs *fp)
{
+ unsigned short *addr, *erraddr, val = 0, err = 0;
+ char sti = 0, buf[6];
- if (retaddr >= (void *)FIXED_CODE_START && retaddr < (void *)physical_mem_end
-#if L1_CODE_LENGTH != 0
- /* FIXME: Copy the code out of L1 Instruction SRAM through dma
- memcpy. */
- && !(retaddr >= (void *)L1_CODE_START
- && retaddr < (void *)(L1_CODE_START + L1_CODE_LENGTH))
-#endif
- ) {
- int i = ((unsigned int)retaddr & 0xFFFFFFF0) - 32;
- unsigned short x = 0;
- printk(KERN_NOTICE "return address: [0x%p]; contents of:", retaddr);
- for (; i < ((unsigned int)retaddr & 0xFFFFFFF0) + 32; i += 2) {
- if (!(i & 0xF))
- printk("\n" KERN_NOTICE "0x%08x: ", i);
+ if (unlikely((fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR))
+ erraddr = (void *)fp->pc;
+ else
+ erraddr = (void *)fp->retx;
- if (get_user(x, (unsigned short *)i))
- break;
+ printk(KERN_NOTICE "return address: [0x%p]; contents of:", erraddr);
+
+ for (addr = (unsigned short *)((unsigned long)erraddr & ~0xF) - 0x10;
+ addr < (unsigned short *)((unsigned long)erraddr & ~0xF) + 0x10;
+ addr++) {
+ if (!((unsigned long)addr & 0xF))
+ printk("\n" KERN_NOTICE "0x%p: ", addr);
+
+ if (get_user(val, addr)) {
+ if (addr >= (unsigned short *)L1_CODE_START &&
+ addr < (unsigned short *)(L1_CODE_START + L1_CODE_LENGTH)) {
+ dma_memcpy(&val, addr, sizeof(val));
+ sprintf(buf, "%04x", val);
+ } else if (addr >= (unsigned short *)FIXED_CODE_START &&
+ addr <= (unsigned short *)memory_start) {
+ val = bfin_read16(addr);
+ sprintf(buf, "%04x", val);
+ } else {
+ val = 0;
+ sprintf(buf, "????");
+ }
+ } else
+ sprintf(buf, "%04x", val);
+
+ if (addr == erraddr) {
+ printk("[%s]", buf);
+ err = val;
+ } else
+ printk(" %s ", buf);
+
+ /* Do any previous instructions turn on interrupts? */
+ if (addr <= erraddr && /* in the past */
+ ((val >= 0x0040 && val <= 0x0047) || /* STI instruction */
+ val == 0x017b)) /* [SP++] = RETI */
+ sti = 1;
+ }
+
+ printk("\n");
+
+ /* Hardware error interrupts can be deferred */
+ if (unlikely(sti && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR &&
+ oops_in_progress)){
+ printk(KERN_NOTICE "Looks like this was a deferred error - sorry\n");
#ifndef CONFIG_DEBUG_HWERR
- /* If one of the last few instructions was a STI
- * it is likely that the error occured awhile ago
- * and we just noticed. This only happens in kernel
- * context, which should mean an oops is happening
- */
- if (oops_in_progress && x >= 0x0040 && x <= 0x0047 && i <= 0)
- panic("\n\nWARNING : You should reconfigure"
- " the kernel to turn on\n"
- " 'Hardware error interrupt"
- " debugging'\n"
- " The rest of this error"
- " is meanless\n");
-#endif
- if (i == (unsigned int)retaddr)
- printk("[%04x]", x);
- else
- printk(" %04x ", x);
+ printk(KERN_NOTICE "The remaining message may be meaningless\n"
+ KERN_NOTICE "You should enable CONFIG_DEBUG_HWERR to get a"
+ " better idea where it came from\n");
+#else
+ /* If we are handling only one peripheral interrupt
+ * and current mm and pid are valid, and the last error
+ * was in that user space process's text area
+ * print it out - because that is where the problem exists
+ */
+ if ((!(((fp)->ipend & ~0x30) & (((fp)->ipend & ~0x30) - 1))) &&
+ (current->pid && current->mm)) {
+ /* And the last RETI points to the current userspace context */
+ if ((fp + 1)->pc >= current->mm->start_code &&
+ (fp + 1)->pc <= current->mm->end_code) {
+ printk(KERN_NOTICE "It might be better to look around here : \n");
+ printk(KERN_NOTICE "-------------------------------------------\n");
+ show_regs(fp + 1);
+ printk(KERN_NOTICE "-------------------------------------------\n");
+ }
}
- printk("\n");
- } else
- printk("\n" KERN_NOTICE
- "Cannot look at the [PC] <%p> for it is"
- " in unreadable memory - sorry\n", retaddr);
+#endif
+ }
}
void show_regs(struct pt_regs *fp)
{
char buf [150];
+ struct irqaction *action;
+ unsigned int i;
+ unsigned long flags;
- printk(KERN_NOTICE "\n" KERN_NOTICE "SEQUENCER STATUS:\n");
+ printk(KERN_NOTICE "\n" KERN_NOTICE "SEQUENCER STATUS:\t\t%s\n", print_tainted());
printk(KERN_NOTICE " SEQSTAT: %08lx IPEND: %04lx SYSCFG: %04lx\n",
(long)fp->seqstat, fp->ipend, fp->syscfg);
+ printk(KERN_NOTICE " HWERRCAUSE: 0x%lx\n",
+ (fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14);
+ printk(KERN_NOTICE " EXCAUSE : 0x%lx\n",
+ fp->seqstat & SEQSTAT_EXCAUSE);
+ for (i = 6; i <= 15 ; i++) {
+ if (fp->ipend & (1 << i)) {
+ decode_address(buf, bfin_read32(EVT0 + 4*i));
+ printk(KERN_NOTICE " physical IVG%i asserted : %s\n", i, buf);
+ }
+ }
+
+ /* if no interrupts are going off, don't print this out */
+ if (fp->ipend & ~0x3F) {
+ for (i = 0; i < (NR_IRQS - 1); i++) {
+ spin_lock_irqsave(&irq_desc[i].lock, flags);
+ action = irq_desc[i].action;
+ if (!action)
+ goto unlock;
+
+ decode_address(buf, (unsigned int)action->handler);
+ printk(KERN_NOTICE " logical irq %3d mapped : %s", i, buf);
+ for (action = action->next; action; action = action->next) {
+ decode_address(buf, (unsigned int)action->handler);
+ printk(", %s", buf);
+ }
+ printk("\n");
+unlock:
+ spin_unlock_irqrestore(&irq_desc[i].lock, flags);
+ }
+ }
decode_address(buf, fp->rete);
printk(KERN_NOTICE " RETE: %s\n", buf);
@@ -708,9 +805,10 @@
decode_address(buf, fp->rets);
printk(KERN_NOTICE " RETS: %s\n", buf);
decode_address(buf, fp->pc);
- printk(KERN_NOTICE " PC: %s\n", buf);
+ printk(KERN_NOTICE " PC : %s\n", buf);
- if ((long)fp->seqstat & SEQSTAT_EXCAUSE) {
+ if (((long)fp->seqstat & SEQSTAT_EXCAUSE) &&
+ (((long)fp->seqstat & SEQSTAT_EXCAUSE) != VEC_HWERR)) {
decode_address(buf, bfin_read_DCPLB_FAULT_ADDR());
printk(KERN_NOTICE "DCPLB_FAULT_ADDR: %s\n", buf);
decode_address(buf, bfin_read_ICPLB_FAULT_ADDR());
@@ -824,7 +922,7 @@
printk(KERN_EMERG "DCPLB_FAULT_ADDR=%p\n", (void *)bfin_read_DCPLB_FAULT_ADDR());
printk(KERN_EMERG "ICPLB_FAULT_ADDR=%p\n", (void *)bfin_read_ICPLB_FAULT_ADDR());
dump_bfin_process(fp);
- dump_bfin_mem((void *)fp->retx);
+ dump_bfin_mem(fp);
show_regs(fp);
dump_stack();
panic("Unrecoverable event\n");
diff --git a/arch/blackfin/lib/memcpy.S b/arch/blackfin/lib/memcpy.S
index 2e63364..e654a18 100644
--- a/arch/blackfin/lib/memcpy.S
+++ b/arch/blackfin/lib/memcpy.S
@@ -70,8 +70,8 @@
/* Check for aligned data.*/
R3 = R1 | R0;
- R0 = 0x3;
- R3 = R3 & R0;
+ R1 = 0x3;
+ R3 = R3 & R1;
CC = R3; /* low bits set on either address? */
IF CC JUMP .Lnot_aligned;
@@ -83,7 +83,6 @@
/* less than eight bytes... */
P2 = R2;
LSETUP(.Lthree_start, .Lthree_end) LC0=P2;
- R0 = R1; /* setup src address for return */
.Lthree_start:
R3 = B[P1++] (X);
.Lthree_end:
@@ -95,7 +94,6 @@
/* There's at least eight bytes to copy. */
P2 += -1; /* because we unroll one iteration */
LSETUP(.Lword_loops, .Lword_loope) LC0=P2;
- R0 = R1;
I1 = P1;
R3 = [I1++];
#if ANOMALY_05000202
@@ -120,7 +118,6 @@
.Lnot_aligned:
/* From here, we're copying byte-by-byte. */
LSETUP (.Lbyte_start, .Lbyte_end) LC0=P2;
- R0 = R1; /* Save src address for return */
.Lbyte_start:
R1 = B[P1++] (X);
.Lbyte_end:
@@ -135,7 +132,6 @@
* Don't bother to work out alignment for
* the reverse case.
*/
- R0 = R1; /* save src for later. */
P0 = P0 + P2;
P0 += -1;
P1 = P1 + P2;
diff --git a/arch/blackfin/mach-bf527/Kconfig b/arch/blackfin/mach-bf527/Kconfig
index 5c73683..3cde4be 100644
--- a/arch/blackfin/mach-bf527/Kconfig
+++ b/arch/blackfin/mach-bf527/Kconfig
@@ -43,7 +43,7 @@
choice
prompt "UART1"
- default BF527_UART1_PORTG
+ default BF527_UART1_PORTF
help
Select PORT used for UART1. See Hardware Reference Manual
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index 003e2ac..f8c411a 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -8,7 +8,7 @@
*
* Modified:
* Copyright 2005 National ICT Australia (NICTA)
- * Copyright 2004-2007 Analog Devices Inc.
+ * Copyright 2004-2008 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
@@ -41,6 +41,7 @@
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/usb/sl811.h>
+#include <linux/usb/musb.h>
#include <asm/cplb.h>
#include <asm/dma.h>
#include <asm/bfin5xx_spi.h>
@@ -105,6 +106,69 @@
arch_initcall(bfin_isp1761_init);
#endif
+#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
+static struct resource musb_resources[] = {
+ [0] = {
+ .start = 0xffc03800,
+ .end = 0xffc03cff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = { /* general IRQ */
+ .start = IRQ_USB_INT0,
+ .end = IRQ_USB_INT0,
+ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
+ },
+ [2] = { /* DMA IRQ */
+ .start = IRQ_USB_DMA,
+ .end = IRQ_USB_DMA,
+ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
+ },
+};
+
+static struct musb_hdrc_platform_data musb_plat = {
+#if defined(CONFIG_USB_MUSB_OTG)
+ .mode = MUSB_OTG,
+#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
+ .mode = MUSB_HOST,
+#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
+ .mode = MUSB_PERIPHERAL,
+#endif
+ .multipoint = 0,
+};
+
+static u64 musb_dmamask = ~(u32)0;
+
+static struct platform_device musb_device = {
+ .name = "musb_hdrc",
+ .id = 0,
+ .dev = {
+ .dma_mask = &musb_dmamask,
+ .coherent_dma_mask = 0xffffffff,
+ .platform_data = &musb_plat,
+ },
+ .num_resources = ARRAY_SIZE(musb_resources),
+ .resource = musb_resources,
+};
+#endif
+
+#if defined(CONFIG_FB_BFIN_T350MCQB) || defined(CONFIG_FB_BFIN_T350MCQB_MODULE)
+
+static struct resource bf52x_t350mcqb_resources[] = {
+ {
+ .start = IRQ_PPI_ERROR,
+ .end = IRQ_PPI_ERROR,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device bf52x_t350mcqb_device = {
+ .name = "bfin-t350mcqb",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(bf52x_t350mcqb_resources),
+ .resource = bf52x_t350mcqb_resources,
+};
+#endif
+
#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
static struct mtd_partition partition_info[] = {
{
@@ -253,12 +317,7 @@
void sl811_port_power(struct device *dev, int is_on)
{
gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS");
- gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS);
-
- if (is_on)
- gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 1);
- else
- gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 0);
+ gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on);
}
#endif
@@ -718,6 +777,28 @@
};
#endif
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+
+static struct gpio_keys_button bfin_gpio_keys_table[] = {
+ {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
+ {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
+};
+
+static struct gpio_keys_platform_data bfin_gpio_keys_data = {
+ .buttons = bfin_gpio_keys_table,
+ .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
+};
+
+static struct platform_device bfin_device_gpiokeys = {
+ .name = "gpio-keys",
+ .dev = {
+ .platform_data = &bfin_gpio_keys_data,
+ },
+};
+#endif
+
static struct platform_device *stamp_devices[] __initdata = {
#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
&bf5xx_nand_device,
@@ -739,6 +820,10 @@
&isp1362_hcd_device,
#endif
+#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
+ &musb_device,
+#endif
+
#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
&smc91x_device,
#endif
@@ -763,6 +848,10 @@
&bfin_fb_device,
#endif
+#if defined(CONFIG_FB_BFIN_T350MCQB) || defined(CONFIG_FB_BFIN_T350MCQB_MODULE)
+ &bf52x_t350mcqb_device,
+#endif
+
#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
&bfin_fb_adv7393_device,
#endif
@@ -783,6 +872,10 @@
#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
&bfin_pata_device,
#endif
+
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+ &bfin_device_gpiokeys,
+#endif
};
static int __init stamp_init(void)
diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c
index 6bcf404..a72c7a6 100644
--- a/arch/blackfin/mach-bf533/boards/H8606.c
+++ b/arch/blackfin/mach-bf533/boards/H8606.c
@@ -40,6 +40,7 @@
#endif
#include <linux/pata_platform.h>
#include <linux/irq.h>
+
#include <asm/dma.h>
#include <asm/bfin5xx_spi.h>
#include <asm/reboot.h>
@@ -303,7 +304,77 @@
};
#endif
-static struct platform_device *stamp_devices[] __initdata = {
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+
+#include <linux/serial_8250.h>
+#include <linux/serial.h>
+
+/*
+ * Configuration for two 16550 UARTS in FPGA at addresses 0x20200000 and 0x202000010.
+ * running at half system clock, both with interrupt output or-ed to PF8. Change to
+ * suit different FPGA configuration, or to suit real 16550 UARTS connected to the bus
+ */
+
+static struct plat_serial8250_port serial8250_platform_data [] = {
+ {
+ .membase = 0x20200000,
+ .mapbase = 0x20200000,
+ .irq = IRQ_PF8,
+ .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE,
+ .iotype = UPIO_MEM,
+ .regshift = 1,
+ .uartclk = 66666667,
+ }, {
+ .membase = 0x20200010,
+ .mapbase = 0x20200010,
+ .irq = IRQ_PF8,
+ .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE,
+ .iotype = UPIO_MEM,
+ .regshift = 1,
+ .uartclk = 66666667,
+ }, {
+ }
+};
+
+static struct platform_device serial8250_device = {
+ .id = PLAT8250_DEV_PLATFORM,
+ .name = "serial8250",
+ .dev = {
+ .platform_data = serial8250_platform_data,
+ },
+};
+
+#endif
+
+#if defined(CONFIG_KEYBOARD_OPENCORES) || defined(CONFIG_KEYBOARD_OPENCORES_MODULE)
+
+/*
+ * Configuration for one OpenCores keyboard controller in FPGA at address 0x20200030,
+ * interrupt output wired to PF9. Change to suit different FPGA configuration
+ */
+
+static struct resource opencores_kbd_resources[] = {
+ [0] = {
+ .start = 0x20200030,
+ .end = 0x20300030 + 2,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_PF9,
+ .end = IRQ_PF9,
+ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
+ },
+};
+
+static struct platform_device opencores_kbd_device = {
+ .id = -1,
+ .name = "opencores-kbd",
+ .resource = opencores_kbd_resources,
+ .num_resources = ARRAY_SIZE(opencores_kbd_resources),
+};
+#endif
+
+static struct platform_device *h8606_devices[] __initdata = {
#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
&rtc_device,
#endif
@@ -327,13 +398,21 @@
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
&bfin_uart_device,
#endif
+
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+ &serial8250_device,
+#endif
+
+#if defined(CONFIG_KEYBOARD_OPENCORES) || defined(CONFIG_KEYBOARD_OPENCORES_MODULE)
+ &opencores_kbd_device,
+#endif
};
static int __init H8606_init(void)
{
printk(KERN_INFO "HV Sistemas H8606 board support by http://www.hvsistemas.com\n");
printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
- platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
+ platform_add_devices(h8606_devices, ARRAY_SIZE(h8606_devices));
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
#endif
diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c
index be85203..c37dd45 100644
--- a/arch/blackfin/mach-bf533/boards/ezkit.c
+++ b/arch/blackfin/mach-bf533/boards/ezkit.c
@@ -256,6 +256,50 @@
};
#endif
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+
+static struct gpio_keys_button bfin_gpio_keys_table[] = {
+ {BTN_0, GPIO_PF7, 1, "gpio-keys: BTN0"},
+ {BTN_1, GPIO_PF8, 1, "gpio-keys: BTN1"},
+ {BTN_2, GPIO_PF9, 1, "gpio-keys: BTN2"},
+ {BTN_3, GPIO_PF10, 1, "gpio-keys: BTN3"},
+};
+
+static struct gpio_keys_platform_data bfin_gpio_keys_data = {
+ .buttons = bfin_gpio_keys_table,
+ .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
+};
+
+static struct platform_device bfin_device_gpiokeys = {
+ .name = "gpio-keys",
+ .dev = {
+ .platform_data = &bfin_gpio_keys_data,
+ },
+};
+#endif
+
+#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
+#include <linux/i2c-gpio.h>
+
+static struct i2c_gpio_platform_data i2c_gpio_data = {
+ .sda_pin = 1,
+ .scl_pin = 0,
+ .sda_is_open_drain = 0,
+ .scl_is_open_drain = 0,
+ .udelay = 40,
+};
+
+static struct platform_device i2c_gpio_device = {
+ .name = "i2c-gpio",
+ .id = 0,
+ .dev = {
+ .platform_data = &i2c_gpio_data,
+ },
+};
+#endif
+
static struct platform_device *ezkit_devices[] __initdata = {
#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
&smc91x_device,
@@ -280,6 +324,14 @@
#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
&bfin_pata_device,
#endif
+
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+ &bfin_device_gpiokeys,
+#endif
+
+#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
+ &i2c_gpio_device,
+#endif
};
static int __init ezkit_init(void)
diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c
index 8fde8d8..ac52b04 100644
--- a/arch/blackfin/mach-bf533/boards/stamp.c
+++ b/arch/blackfin/mach-bf533/boards/stamp.c
@@ -32,6 +32,7 @@
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
@@ -108,6 +109,50 @@
};
#endif
+static struct mtd_partition stamp_partitions[] = {
+ {
+ .name = "Bootloader",
+ .size = 0x20000,
+ .offset = 0,
+ }, {
+ .name = "Kernel",
+ .size = 0xE0000,
+ .offset = MTDPART_OFS_APPEND,
+ }, {
+ .name = "RootFS",
+ .size = MTDPART_SIZ_FULL,
+ .offset = MTDPART_OFS_APPEND,
+ }
+};
+
+static struct physmap_flash_data stamp_flash_data = {
+ .width = 2,
+ .parts = stamp_partitions,
+ .nr_parts = ARRAY_SIZE(stamp_partitions),
+};
+
+static struct resource stamp_flash_resource[] = {
+ {
+ .name = "cfi_probe",
+ .start = 0x20000000,
+ .end = 0x203fffff,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = CONFIG_ENET_FLASH_PIN,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static struct platform_device stamp_flash_device = {
+ .name = "BF5xx-Flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &stamp_flash_data,
+ },
+ .num_resources = ARRAY_SIZE(stamp_flash_resource),
+ .resource = stamp_flash_resource,
+};
+
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
/* all SPI peripherals info goes here */
@@ -373,6 +418,49 @@
};
#endif
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+
+static struct gpio_keys_button bfin_gpio_keys_table[] = {
+ {BTN_0, GPIO_PF5, 1, "gpio-keys: BTN0"},
+ {BTN_1, GPIO_PF6, 1, "gpio-keys: BTN1"},
+ {BTN_2, GPIO_PF8, 1, "gpio-keys: BTN2"},
+};
+
+static struct gpio_keys_platform_data bfin_gpio_keys_data = {
+ .buttons = bfin_gpio_keys_table,
+ .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
+};
+
+static struct platform_device bfin_device_gpiokeys = {
+ .name = "gpio-keys",
+ .dev = {
+ .platform_data = &bfin_gpio_keys_data,
+ },
+};
+#endif
+
+#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
+#include <linux/i2c-gpio.h>
+
+static struct i2c_gpio_platform_data i2c_gpio_data = {
+ .sda_pin = 2,
+ .scl_pin = 3,
+ .sda_is_open_drain = 0,
+ .scl_is_open_drain = 0,
+ .udelay = 40,
+};
+
+static struct platform_device i2c_gpio_device = {
+ .name = "i2c-gpio",
+ .id = 0,
+ .dev = {
+ .platform_data = &i2c_gpio_data,
+ },
+};
+#endif
+
static struct platform_device *stamp_devices[] __initdata = {
#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
&rtc_device,
@@ -406,6 +494,15 @@
#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
&bfin_pata_device,
#endif
+
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+ &bfin_device_gpiokeys,
+#endif
+
+#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
+ &i2c_gpio_device,
+#endif
+ &stamp_flash_device,
};
static int __init stamp_init(void)
@@ -418,12 +515,10 @@
return ret;
#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
-# if defined(CONFIG_BFIN_SHARED_FLASH_ENET)
/* setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC */
bfin_write_FIO_DIR(bfin_read_FIO_DIR() | (1 << CONFIG_ENET_FLASH_PIN));
bfin_write_FIO_FLAG_S(1 << CONFIG_ENET_FLASH_PIN);
SSYNC();
-# endif
#endif
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
@@ -440,10 +535,8 @@
void native_machine_restart(char *cmd)
{
-#if defined(CONFIG_BFIN_SHARED_FLASH_ENET)
-# define BIT_TO_SET (1 << CONFIG_ENET_FLASH_PIN)
+#define BIT_TO_SET (1 << CONFIG_ENET_FLASH_PIN)
bfin_write_FIO_INEN(~BIT_TO_SET);
bfin_write_FIO_DIR(BIT_TO_SET);
bfin_write_FIO_FLAG_C(BIT_TO_SET);
-#endif
}
diff --git a/arch/blackfin/mach-bf537/boards/Kconfig b/arch/blackfin/mach-bf537/boards/Kconfig
index 96a1519..7e789db 100644
--- a/arch/blackfin/mach-bf537/boards/Kconfig
+++ b/arch/blackfin/mach-bf537/boards/Kconfig
@@ -21,6 +21,12 @@
help
PNAV board support.
+config CAMSIG_MINOTAUR
+ bool "Cambridge Signal Processing LTD Minotaur"
+ depends on (BF537)
+ help
+ Board supply package for CSP Minotaur
+
config GENERIC_BF537_BOARD
bool "Generic"
help
diff --git a/arch/blackfin/mach-bf537/boards/Makefile b/arch/blackfin/mach-bf537/boards/Makefile
index 94a8517..87e450f 100644
--- a/arch/blackfin/mach-bf537/boards/Makefile
+++ b/arch/blackfin/mach-bf537/boards/Makefile
@@ -6,3 +6,4 @@
obj-$(CONFIG_BFIN537_STAMP) += stamp.o led.o
obj-$(CONFIG_BFIN537_BLUETECHNIX_CM) += cm_bf537.o
obj-$(CONFIG_PNAV10) += pnav10.o
+obj-$(CONFIG_CAMSIG_MINOTAUR) += minotaur.o
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537.c b/arch/blackfin/mach-bf537/boards/cm_bf537.c
index c0fb06d..8703b67 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537.c
@@ -29,6 +29,7 @@
*/
#include <linux/device.h>
+#include <linux/etherdevice.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
@@ -216,6 +217,12 @@
};
#endif
+#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
+static struct platform_device hitachi_fb_device = {
+ .name = "hitachi-tx09",
+};
+#endif
+
#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
static struct resource smc91x_resources[] = {
{
@@ -374,6 +381,10 @@
#endif
static struct platform_device *cm_bf537_devices[] __initdata = {
+#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
+ &hitachi_fb_device,
+#endif
+
#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
&rtc_device,
#endif
diff --git a/arch/blackfin/mach-bf537/boards/generic_board.c b/arch/blackfin/mach-bf537/boards/generic_board.c
index 09f4bfb..3e52f3f 100644
--- a/arch/blackfin/mach-bf537/boards/generic_board.c
+++ b/arch/blackfin/mach-bf537/boards/generic_board.c
@@ -8,7 +8,7 @@
*
* Modified:
* Copyright 2005 National ICT Australia (NICTA)
- * Copyright 2004-2007 Analog Devices Inc.
+ * Copyright 2004-2008 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
@@ -29,6 +29,7 @@
*/
#include <linux/device.h>
+#include <linux/etherdevice.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
@@ -204,12 +205,8 @@
void sl811_port_power(struct device *dev, int is_on)
{
gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS");
- gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS);
+ gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on);
- if (is_on)
- gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 1);
- else
- gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 0);
}
#endif
@@ -733,9 +730,11 @@
bfin_gpio_reset_spi0_ssel1();
}
+#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
void bfin_get_ether_addr(char *addr)
{
random_ether_addr(addr);
printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__);
}
EXPORT_SYMBOL(bfin_get_ether_addr);
+#endif
diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c
new file mode 100644
index 0000000..b8bbba8
--- /dev/null
+++ b/arch/blackfin/mach-bf537/boards/minotaur.c
@@ -0,0 +1,317 @@
+/*
+ */
+
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
+#include <linux/usb_isp1362.h>
+#endif
+#include <linux/pata_platform.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/usb_sl811.h>
+#include <asm/dma.h>
+#include <asm/bfin5xx_spi.h>
+#include <asm/reboot.h>
+#include <linux/spi/ad7877.h>
+
+/*
+ * Name the Board for the /proc/cpuinfo
+ */
+char *bfin_board_name = "CamSig Minotaur BF537";
+
+#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
+static struct resource bfin_pcmcia_cf_resources[] = {
+ {
+ .start = 0x20310000, /* IO PORT */
+ .end = 0x20312000,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = 0x20311000, /* Attribute Memory */
+ .end = 0x20311FFF,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_PF4,
+ .end = IRQ_PF4,
+ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
+ }, {
+ .start = IRQ_PF6, /* Card Detect PF6 */
+ .end = IRQ_PF6,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device bfin_pcmcia_cf_device = {
+ .name = "bfin_cf_pcmcia",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
+ .resource = bfin_pcmcia_cf_resources,
+};
+#endif
+
+#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+static struct platform_device rtc_device = {
+ .name = "rtc-bfin",
+ .id = -1,
+};
+#endif
+
+#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+static struct platform_device bfin_mac_device = {
+ .name = "bfin_mac",
+};
+#endif
+
+#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+static struct resource net2272_bfin_resources[] = {
+ {
+ .start = 0x20300000,
+ .end = 0x20300000 + 0x100,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_PF7,
+ .end = IRQ_PF7,
+ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
+ },
+};
+
+static struct platform_device net2272_bfin_device = {
+ .name = "net2272",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(net2272_bfin_resources),
+ .resource = net2272_bfin_resources,
+};
+#endif
+
+#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+/* all SPI peripherals info goes here */
+
+#if defined(CONFIG_MTD_M25P80) \
+ || defined(CONFIG_MTD_M25P80_MODULE)
+
+/* Partition sizes */
+#define FLASH_SIZE 0x00400000
+#define PSIZE_UBOOT 0x00030000
+#define PSIZE_INITRAMFS 0x00240000
+
+static struct mtd_partition bfin_spi_flash_partitions[] = {
+ {
+ .name = "uboot",
+ .size = PSIZE_UBOOT,
+ .offset = 0x000000,
+ .mask_flags = MTD_CAP_ROM
+ }, {
+ .name = "initramfs",
+ .size = PSIZE_INITRAMFS,
+ .offset = PSIZE_UBOOT
+ }, {
+ .name = "opt",
+ .size = FLASH_SIZE - (PSIZE_UBOOT + PSIZE_INITRAMFS),
+ .offset = PSIZE_UBOOT + PSIZE_INITRAMFS,
+ }
+};
+
+static struct flash_platform_data bfin_spi_flash_data = {
+ .name = "m25p80",
+ .parts = bfin_spi_flash_partitions,
+ .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
+ .type = "m25p64",
+};
+
+/* SPI flash chip (m25p64) */
+static struct bfin5xx_spi_chip spi_flash_chip_info = {
+ .enable_dma = 0, /* use dma transfer with this chip*/
+ .bits_per_word = 8,
+};
+#endif
+
+#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
+static struct bfin5xx_spi_chip spi_mmc_chip_info = {
+ .enable_dma = 1,
+ .bits_per_word = 8,
+};
+#endif
+
+static struct spi_board_info bfin_spi_board_info[] __initdata = {
+#if defined(CONFIG_MTD_M25P80) \
+ || defined(CONFIG_MTD_M25P80_MODULE)
+ {
+ /* the modalias must be the same as spi device driver name */
+ .modalias = "m25p80", /* Name of spi_driver for this device */
+ .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
+ .bus_num = 0, /* Framework bus number */
+ .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
+ .platform_data = &bfin_spi_flash_data,
+ .controller_data = &spi_flash_chip_info,
+ .mode = SPI_MODE_3,
+ },
+#endif
+
+#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
+ {
+ .modalias = "spi_mmc_dummy",
+ .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
+ .bus_num = 0,
+ .chip_select = 0,
+ .platform_data = NULL,
+ .controller_data = &spi_mmc_chip_info,
+ .mode = SPI_MODE_3,
+ },
+ {
+ .modalias = "spi_mmc",
+ .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
+ .bus_num = 0,
+ .chip_select = CONFIG_SPI_MMC_CS_CHAN,
+ .platform_data = NULL,
+ .controller_data = &spi_mmc_chip_info,
+ .mode = SPI_MODE_3,
+ },
+#endif
+};
+
+/* SPI controller data */
+static struct bfin5xx_spi_master bfin_spi0_info = {
+ .num_chipselect = 8,
+ .enable_dma = 1, /* master has the ability to do dma transfer */
+};
+
+/* SPI (0) */
+static struct resource bfin_spi0_resource[] = {
+ [0] = {
+ .start = SPI0_REGBASE,
+ .end = SPI0_REGBASE + 0xFF,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = CH_SPI,
+ .end = CH_SPI,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device bfin_spi0_device = {
+ .name = "bfin-spi",
+ .id = 0, /* Bus number */
+ .num_resources = ARRAY_SIZE(bfin_spi0_resource),
+ .resource = bfin_spi0_resource,
+ .dev = {
+ .platform_data = &bfin_spi0_info, /* Passed to driver */
+ },
+};
+#endif /* spi master and devices */
+
+#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+static struct resource bfin_uart_resources[] = {
+ {
+ .start = 0xFFC00400,
+ .end = 0xFFC004FF,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = 0xFFC02000,
+ .end = 0xFFC020FF,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device bfin_uart_device = {
+ .name = "bfin-uart",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(bfin_uart_resources),
+ .resource = bfin_uart_resources,
+};
+#endif
+
+#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+static struct resource bfin_twi0_resource[] = {
+ [0] = {
+ .start = TWI0_REGBASE,
+ .end = TWI0_REGBASE + 0xFF,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_TWI,
+ .end = IRQ_TWI,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device i2c_bfin_twi_device = {
+ .name = "i2c-bfin-twi",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(bfin_twi0_resource),
+ .resource = bfin_twi0_resource,
+};
+#endif
+
+#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+static struct platform_device bfin_sport0_uart_device = {
+ .name = "bfin-sport-uart",
+ .id = 0,
+};
+
+static struct platform_device bfin_sport1_uart_device = {
+ .name = "bfin-sport-uart",
+ .id = 1,
+};
+#endif
+
+static struct platform_device *minotaur_devices[] __initdata = {
+#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
+ &bfin_pcmcia_cf_device,
+#endif
+
+#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+ &rtc_device,
+#endif
+
+#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+ &bfin_mac_device,
+#endif
+
+#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+ &net2272_bfin_device,
+#endif
+
+#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+ &bfin_spi0_device,
+#endif
+
+#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+ &bfin_uart_device,
+#endif
+
+#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+ &i2c_bfin_twi_device,
+#endif
+
+#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+ &bfin_sport0_uart_device,
+ &bfin_sport1_uart_device,
+#endif
+
+};
+
+static int __init minotaur_init(void)
+{
+ printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
+ platform_add_devices(minotaur_devices, ARRAY_SIZE(minotaur_devices));
+#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+ spi_register_board_info(bfin_spi_board_info,
+ ARRAY_SIZE(bfin_spi_board_info));
+#endif
+
+ return 0;
+}
+
+arch_initcall(minotaur_init);
+
+void native_machine_restart(char *cmd)
+{
+ /* workaround reboot hang when booting from SPI */
+ if ((bfin_read_SYSCR() & 0x7) == 0x3)
+ bfin_gpio_reset_spi0_ssel1();
+}
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c
index fd5f4a6..509a8a2 100644
--- a/arch/blackfin/mach-bf537/boards/pnav10.c
+++ b/arch/blackfin/mach-bf537/boards/pnav10.c
@@ -8,7 +8,7 @@
*
* Modified:
* Copyright 2005 National ICT Australia (NICTA)
- * Copyright 2004-2006 Analog Devices Inc.
+ * Copyright 2004-2008 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
@@ -29,6 +29,7 @@
*/
#include <linux/device.h>
+#include <linux/etherdevice.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
@@ -133,12 +134,8 @@
void sl811_port_power(struct device *dev, int is_on)
{
gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS");
- gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS);
+ gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on);
- if (is_on)
- gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 1);
- else
- gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 0);
}
#endif
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index 07b0dc2..7725415 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -32,6 +32,7 @@
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
@@ -103,6 +104,30 @@
arch_initcall(bfin_isp1761_init);
#endif
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+
+static struct gpio_keys_button bfin_gpio_keys_table[] = {
+ {BTN_0, GPIO_PF2, 1, "gpio-keys: BTN0"},
+ {BTN_1, GPIO_PF3, 1, "gpio-keys: BTN1"},
+ {BTN_2, GPIO_PF4, 1, "gpio-keys: BTN2"},
+ {BTN_3, GPIO_PF5, 1, "gpio-keys: BTN3"},
+};
+
+static struct gpio_keys_platform_data bfin_gpio_keys_data = {
+ .buttons = bfin_gpio_keys_table,
+ .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
+};
+
+static struct platform_device bfin_device_gpiokeys = {
+ .name = "gpio-keys",
+ .dev = {
+ .platform_data = &bfin_gpio_keys_data,
+ },
+};
+#endif
+
#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
static struct resource bfin_pcmcia_cf_resources[] = {
{
@@ -226,12 +251,7 @@
void sl811_port_power(struct device *dev, int is_on)
{
gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS");
- gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS);
-
- if (is_on)
- gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 1);
- else
- gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 0);
+ gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on);
}
#endif
@@ -320,6 +340,49 @@
};
#endif
+static struct mtd_partition stamp_partitions[] = {
+ {
+ .name = "Bootloader",
+ .size = 0x20000,
+ .offset = 0,
+ }, {
+ .name = "Kernel",
+ .size = 0xE0000,
+ .offset = MTDPART_OFS_APPEND,
+ }, {
+ .name = "RootFS",
+ .size = 0x400000 - 0x20000 - 0xE0000 - 0x10000,
+ .offset = MTDPART_OFS_APPEND,
+ }, {
+ .name = "MAC Address",
+ .size = MTDPART_SIZ_FULL,
+ .offset = 0x3F0000,
+ .mask_flags = MTD_WRITEABLE,
+ }
+};
+
+static struct physmap_flash_data stamp_flash_data = {
+ .width = 2,
+ .parts = stamp_partitions,
+ .nr_parts = ARRAY_SIZE(stamp_partitions),
+};
+
+static struct resource stamp_flash_resource = {
+ .start = 0x20000000,
+ .end = 0x203fffff,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device stamp_flash_device = {
+ .name = "physmap-flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &stamp_flash_data,
+ },
+ .num_resources = 1,
+ .resource = &stamp_flash_resource,
+};
+
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
/* all SPI peripherals info goes here */
@@ -738,6 +801,11 @@
#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
&bfin_pata_device,
#endif
+
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+ &bfin_device_gpiokeys,
+#endif
+ &stamp_flash_device,
};
static int __init stamp_init(void)
diff --git a/arch/blackfin/mach-bf548/Kconfig b/arch/blackfin/mach-bf548/Kconfig
index d8bd3b49..1bfcd8f 100644
--- a/arch/blackfin/mach-bf548/Kconfig
+++ b/arch/blackfin/mach-bf548/Kconfig
@@ -7,7 +7,7 @@
config DEB_DMA_URGENT
bool "DMA has priority over core for ext. accesses"
depends on BF54x
- default n
+ default y
help
Treat any DEB1, DEB2 and DEB3 request as Urgent
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index d37d665..14860f0 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -32,6 +32,7 @@
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <linux/irq.h>
@@ -206,23 +207,6 @@
};
#endif
-#if defined(CONFIG_USB_BF54x_HCD) || defined(CONFIG_USB_BF54x_HCD_MODULE)
-static struct resource bf54x_hcd_resources[] = {
- {
- .start = 0xFFC03C00,
- .end = 0xFFC040FF,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device bf54x_hcd = {
- .name = "bf54x-hcd",
- .id = 0,
- .num_resources = ARRAY_SIZE(bf54x_hcd_resources),
- .resource = bf54x_hcd_resources,
-};
-#endif
-
#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
static struct resource musb_resources[] = {
[0] = {
@@ -243,14 +227,14 @@
};
static struct musb_hdrc_platform_data musb_plat = {
-#ifdef CONFIG_USB_MUSB_OTG
+#if defined(CONFIG_USB_MUSB_OTG)
.mode = MUSB_OTG,
-#elif CONFIG_USB_MUSB_HDRC_HCD
+#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
.mode = MUSB_HOST,
-#elif CONFIG_USB_GADGET_MUSB_HDRC
+#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
.mode = MUSB_PERIPHERAL,
#endif
- .multipoint = 1,
+ .multipoint = 0,
};
static u64 musb_dmamask = ~(u32)0;
@@ -344,6 +328,44 @@
};
#endif
+static struct mtd_partition ezkit_partitions[] = {
+ {
+ .name = "Bootloader",
+ .size = 0x20000,
+ .offset = 0,
+ }, {
+ .name = "Kernel",
+ .size = 0xE0000,
+ .offset = MTDPART_OFS_APPEND,
+ }, {
+ .name = "RootFS",
+ .size = MTDPART_SIZ_FULL,
+ .offset = MTDPART_OFS_APPEND,
+ }
+};
+
+static struct physmap_flash_data ezkit_flash_data = {
+ .width = 2,
+ .parts = ezkit_partitions,
+ .nr_parts = ARRAY_SIZE(ezkit_partitions),
+};
+
+static struct resource ezkit_flash_resource = {
+ .start = 0x20000000,
+ .end = 0x20ffffff,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device ezkit_flash_device = {
+ .name = "physmap-flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &ezkit_flash_data,
+ },
+ .num_resources = 1,
+ .resource = &ezkit_flash_resource,
+};
+
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
/* all SPI peripherals info goes here */
#if defined(CONFIG_MTD_M25P80) \
@@ -531,6 +553,29 @@
#endif
#endif
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#include <linux/gpio_keys.h>
+
+static struct gpio_keys_button bfin_gpio_keys_table[] = {
+ {BTN_0, GPIO_PB8, 1, "gpio-keys: BTN0"},
+ {BTN_1, GPIO_PB9, 1, "gpio-keys: BTN1"},
+ {BTN_2, GPIO_PB10, 1, "gpio-keys: BTN2"},
+ {BTN_3, GPIO_PB11, 1, "gpio-keys: BTN3"},
+};
+
+static struct gpio_keys_platform_data bfin_gpio_keys_data = {
+ .buttons = bfin_gpio_keys_table,
+ .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
+};
+
+static struct platform_device bfin_device_gpiokeys = {
+ .name = "gpio-keys",
+ .dev = {
+ .platform_data = &bfin_gpio_keys_data,
+ },
+};
+#endif
+
static struct platform_device *ezkit_devices[] __initdata = {
#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
&rtc_device,
@@ -548,10 +593,6 @@
&smsc911x_device,
#endif
-#if defined(CONFIG_USB_BF54x_HCD) || defined(CONFIG_USB_BF54x_HCD_MODULE)
- &bf54x_hcd,
-#endif
-
#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
&musb_device,
#endif
@@ -583,6 +624,11 @@
&i2c_bfin_twi1_device,
#endif
#endif
+
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+ &bfin_device_gpiokeys,
+#endif
+ &ezkit_flash_device,
};
static int __init stamp_init(void)
diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S
index 74b34c7..74fe258 100644
--- a/arch/blackfin/mach-bf548/head.S
+++ b/arch/blackfin/mach-bf548/head.S
@@ -298,8 +298,8 @@
w[p0] = r0.l;
ssync;
- p0.h = hi(SIC_IWR);
- p0.l = lo(SIC_IWR);
+ p0.h = hi(SIC_IWR0);
+ p0.l = lo(SIC_IWR0);
r0.l = 0x1;
r0.h = 0x0;
[p0] = r0;
@@ -324,12 +324,25 @@
w[p0] = r0.l;
ssync;
+#if defined(CONFIG_BF54x)
+ P2.H = hi(EBIU_RSTCTL);
+ P2.L = lo(EBIU_RSTCTL);
+ R0 = [P2];
+ BITSET (R0, 3);
+#else
P2.H = hi(EBIU_SDGCTL);
P2.L = lo(EBIU_SDGCTL);
R0 = [P2];
BITSET (R0, 24);
+#endif
[P2] = R0;
SSYNC;
+#if defined(CONFIG_BF54x)
+.LSRR_MODE:
+ R0 = [P2];
+ CC = BITTST(R0, 4);
+ if !CC JUMP .LSRR_MODE;
+#endif
r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
r0 = r0 << 9; /* Shift it over, */
@@ -361,6 +374,39 @@
w[p0] = r0.l;
ssync;
+#if defined(CONFIG_BF54x)
+ P2.H = hi(EBIU_RSTCTL);
+ P2.L = lo(EBIU_RSTCTL);
+ R0 = [P2];
+ CC = BITTST(R0, 0);
+ if CC jump .Lskipddrrst;
+ BITSET (R0, 0);
+.Lskipddrrst:
+ BITCLR (R0, 3);
+ [P2] = R0;
+ SSYNC;
+
+ p0.l = lo(EBIU_DDRCTL0);
+ p0.h = hi(EBIU_DDRCTL0);
+ r0.l = lo(mem_DDRCTL0);
+ r0.h = hi(mem_DDRCTL0);
+ [p0] = r0;
+ ssync;
+
+ p0.l = lo(EBIU_DDRCTL1);
+ p0.h = hi(EBIU_DDRCTL1);
+ r0.l = lo(mem_DDRCTL1);
+ r0.h = hi(mem_DDRCTL1);
+ [p0] = r0;
+ ssync;
+
+ p0.l = lo(EBIU_DDRCTL2);
+ p0.h = hi(EBIU_DDRCTL2);
+ r0.l = lo(mem_DDRCTL2);
+ r0.h = hi(mem_DDRCTL2);
+ [p0] = r0;
+ ssync;
+#else
p0.l = lo(EBIU_SDRRC);
p0.h = hi(EBIU_SDRRC);
r0 = mem_SDRRC;
@@ -394,9 +440,10 @@
R1 = R1 | R0;
[P2] = R1;
SSYNC;
+#endif
- p0.h = hi(SIC_IWR);
- p0.l = lo(SIC_IWR);
+ p0.h = hi(SIC_IWR0);
+ p0.l = lo(SIC_IWR0);
r0.l = lo(IWR_ENABLE_ALL);
r0.h = hi(IWR_ENABLE_ALL);
[p0] = r0;
diff --git a/arch/blackfin/mach-bf548/ints-priority.c b/arch/blackfin/mach-bf548/ints-priority.c
index cb0ebac..2665653 100644
--- a/arch/blackfin/mach-bf548/ints-priority.c
+++ b/arch/blackfin/mach-bf548/ints-priority.c
@@ -4,7 +4,7 @@
* Author: Michael Hennerich
*
* Created:
- * Description: Set up the interupt priorities
+ * Description: Set up the interrupt priorities
*
* Modified:
* Copyright 2004-2006 Analog Devices Inc.
@@ -58,7 +58,7 @@
((CONFIG_IRQ_PINT1 - 7) << IRQ_PINT1_POS) |
((CONFIG_IRQ_MDMAS0 - 7) << IRQ_MDMAS0_POS) |
((CONFIG_IRQ_MDMAS1 - 7) << IRQ_MDMAS1_POS) |
- ((CONFIG_IRQ_WATCHDOG - 7) << IRQ_WATCHDOG_POS));
+ ((CONFIG_IRQ_WATCHDOG - 7) << IRQ_WATCH_POS));
bfin_write_SIC_IAR3(((CONFIG_IRQ_DMAC1_ERR - 7) << IRQ_DMAC1_ERR_POS) |
((CONFIG_IRQ_SPORT2_ERR - 7) << IRQ_SPORT2_ERR_POS) |
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c
index c19cd29..3a79a90 100644
--- a/arch/blackfin/mach-bf561/boards/cm_bf561.c
+++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c
@@ -198,6 +198,13 @@
#endif /* spi master and devices */
+#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
+static struct platform_device hitachi_fb_device = {
+ .name = "hitachi-tx09",
+};
+#endif
+
+
#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
static struct resource smc91x_resources[] = {
@@ -315,6 +322,10 @@
static struct platform_device *cm_bf561_devices[] __initdata = {
+#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
+ &hitachi_fb_device,
+#endif
+
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
&bfin_uart_device,
#endif
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
index 4ff8f6e..7601c3b 100644
--- a/arch/blackfin/mach-bf561/boards/ezkit.c
+++ b/arch/blackfin/mach-bf561/boards/ezkit.c
@@ -29,6 +29,9 @@
#include <linux/device.h>
#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
#include <linux/spi/spi.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
@@ -155,6 +158,44 @@
};
#endif
+static struct mtd_partition ezkit_partitions[] = {
+ {
+ .name = "Bootloader",
+ .size = 0x20000,
+ .offset = 0,
+ }, {
+ .name = "Kernel",
+ .size = 0xE0000,
+ .offset = MTDPART_OFS_APPEND,
+ }, {
+ .name = "RootFS",
+ .size = MTDPART_SIZ_FULL,
+ .offset = MTDPART_OFS_APPEND,
+ }
+};
+
+static struct physmap_flash_data ezkit_flash_data = {
+ .width = 2,
+ .parts = ezkit_partitions,
+ .nr_parts = ARRAY_SIZE(ezkit_partitions),
+};
+
+static struct resource ezkit_flash_resource = {
+ .start = 0x20000000,
+ .end = 0x207fffff,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device ezkit_flash_device = {
+ .name = "physmap-flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &ezkit_flash_data,
+ },
+ .num_resources = 1,
+ .resource = &ezkit_flash_resource,
+};
+
#ifdef CONFIG_SPI_BFIN
#if defined(CONFIG_SND_BLACKFIN_AD1836) \
|| defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
@@ -246,6 +287,50 @@
};
#endif
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+
+static struct gpio_keys_button bfin_gpio_keys_table[] = {
+ {BTN_0, GPIO_PF5, 1, "gpio-keys: BTN0"},
+ {BTN_1, GPIO_PF6, 1, "gpio-keys: BTN1"},
+ {BTN_2, GPIO_PF7, 1, "gpio-keys: BTN2"},
+ {BTN_3, GPIO_PF8, 1, "gpio-keys: BTN3"},
+};
+
+static struct gpio_keys_platform_data bfin_gpio_keys_data = {
+ .buttons = bfin_gpio_keys_table,
+ .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
+};
+
+static struct platform_device bfin_device_gpiokeys = {
+ .name = "gpio-keys",
+ .dev = {
+ .platform_data = &bfin_gpio_keys_data,
+ },
+};
+#endif
+
+#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
+#include <linux/i2c-gpio.h>
+
+static struct i2c_gpio_platform_data i2c_gpio_data = {
+ .sda_pin = 1,
+ .scl_pin = 0,
+ .sda_is_open_drain = 0,
+ .scl_is_open_drain = 0,
+ .udelay = 40,
+};
+
+static struct platform_device i2c_gpio_device = {
+ .name = "i2c-gpio",
+ .id = 0,
+ .dev = {
+ .platform_data = &i2c_gpio_data,
+ },
+};
+#endif
+
static struct platform_device *ezkit_devices[] __initdata = {
#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
&smc91x_device,
@@ -258,12 +343,23 @@
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
&bfin_spi0_device,
#endif
+
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
&bfin_uart_device,
#endif
+
#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
&bfin_pata_device,
#endif
+
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+ &bfin_device_gpiokeys,
+#endif
+
+#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
+ &i2c_gpio_device,
+#endif
+ &ezkit_flash_device,
};
static int __init ezkit_init(void)
diff --git a/arch/blackfin/mach-bf561/coreb.c b/arch/blackfin/mach-bf561/coreb.c
index 5d1d21b..1b44e9e 100644
--- a/arch/blackfin/mach-bf561/coreb.c
+++ b/arch/blackfin/mach-bf561/coreb.c
@@ -33,7 +33,9 @@
#include <linux/ioport.h>
#include <linux/module.h>
#include <linux/uaccess.h>
+#include <linux/fs.h>
#include <asm/dma.h>
+#include <asm/cacheflush.h>
#define MODULE_VER "v0.1"
@@ -90,11 +92,12 @@
coreb_dma_done = 0;
+ flush_dcache_range((unsigned long)buf, (unsigned long)(buf+len));
/* Source Channel */
set_dma_start_addr(CH_MEM_STREAM2_SRC, (unsigned long)buf);
set_dma_x_count(CH_MEM_STREAM2_SRC, len);
set_dma_x_modify(CH_MEM_STREAM2_SRC, sizeof(char));
- set_dma_config(CH_MEM_STREAM2_SRC, RESTART);
+ set_dma_config(CH_MEM_STREAM2_SRC, 0);
/* Destination Channel */
set_dma_start_addr(CH_MEM_STREAM2_DEST, coreb_base + p);
set_dma_x_count(CH_MEM_STREAM2_DEST, len);
@@ -135,11 +138,12 @@
coreb_dma_done = 0;
+ invalidate_dcache_range((unsigned long)buf, (unsigned long)(buf+len));
/* Source Channel */
set_dma_start_addr(CH_MEM_STREAM2_SRC, coreb_base + p);
set_dma_x_count(CH_MEM_STREAM2_SRC, len);
set_dma_x_modify(CH_MEM_STREAM2_SRC, sizeof(char));
- set_dma_config(CH_MEM_STREAM2_SRC, RESTART);
+ set_dma_config(CH_MEM_STREAM2_SRC, 0);
/* Destination Channel */
set_dma_start_addr(CH_MEM_STREAM2_DEST, (unsigned long)buf);
set_dma_x_count(CH_MEM_STREAM2_DEST, len);
@@ -266,7 +270,7 @@
coreb_status |= COREB_IS_RUNNING;
bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~0x0020);
SSYNC();
- spin_lock_irq(&coreb_lock);
+ spin_unlock_irq(&coreb_lock);
break;
#if defined(CONFIG_BF561_COREB_RESET)
case CMD_COREB_STOP:
@@ -275,7 +279,7 @@
bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() | 0x0020);
bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
coreb_status &= ~COREB_IS_RUNNING;
- spin_lock_irq(&coreb_lock);
+ spin_unlock_irq(&coreb_lock);
break;
case CMD_COREB_RESET:
printk(KERN_INFO "Resetting Core B\n");
diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile
index 4d7733d..8636d42 100644
--- a/arch/blackfin/mach-common/Makefile
+++ b/arch/blackfin/mach-common/Makefile
@@ -3,10 +3,9 @@
#
obj-y := \
- cache.o cacheinit.o cplbhdlr.o cplbmgr.o entry.o \
+ cache.o cacheinit.o entry.o \
interrupt.o lock.o irqpanic.o arch_checks.o
-obj-$(CONFIG_CPLB_INFO) += cplbinfo.o
obj-$(CONFIG_BFIN_SINGLE_CORE) += ints-priority-sc.o
obj-$(CONFIG_BFIN_DUAL_CORE) += ints-priority-dc.o
obj-$(CONFIG_PM) += pm.o dpmc.o
diff --git a/arch/blackfin/mach-common/dpmc.S b/arch/blackfin/mach-common/dpmc.S
index 39fbc28..b82c096e 100644
--- a/arch/blackfin/mach-common/dpmc.S
+++ b/arch/blackfin/mach-common/dpmc.S
@@ -38,6 +38,9 @@
#if defined(CONFIG_BF561)
P0.H = hi(SICA_IWR1);
P0.L = lo(SICA_IWR1);
+#elif defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
+ P0.h = HI(SIC_IWR0);
+ P0.l = LO(SIC_IWR0);
#else
P0.h = HI(SIC_IWR);
P0.l = LO(SIC_IWR);
@@ -172,7 +175,7 @@
call _set_sic_iwr;
R0 = 0xFFFF (Z);
- call _set_rtc_istat
+ call _set_rtc_istat;
P0.H = hi(PLL_CTL);
P0.L = lo(PLL_CTL);
@@ -210,7 +213,7 @@
call _set_sic_iwr;
R0 = 0xFFFF (Z);
- call _set_rtc_istat
+ call _set_rtc_istat;
P0.H = hi(VR_CTL);
P0.L = lo(VR_CTL);
@@ -236,7 +239,7 @@
call _set_sic_iwr;
- call _set_sdram_srfs;
+ call _set_dram_srfs;
/* Clear all the interrupts,bits sticky */
R0 = 0xFFFF (Z);
@@ -253,7 +256,7 @@
SSYNC;
IDLE;
- call _unset_sdram_srfs;
+ call _unset_dram_srfs;
call _test_pll_locked;
@@ -285,23 +288,22 @@
P3 = R0;
R0 = IWR_ENABLE(0);
call _set_sic_iwr;
- call _set_sdram_srfs;
+ call _set_dram_srfs; /* Set SDRAM Self Refresh */
/* Clear all the interrupts,bits sticky */
R0 = 0xFFFF (Z);
- call _set_rtc_istat
-
+ call _set_rtc_istat;
P0.H = hi(PLL_DIV);
P0.L = lo(PLL_DIV);
R6 = W[P0](z);
R0.L = 0xF;
- W[P0] = R0.l;
+ W[P0] = R0.l; /* Set Max VCO to SCLK divider */
P0.H = hi(PLL_CTL);
P0.L = lo(PLL_CTL);
R5 = W[P0](z);
R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
- W[P0] = R0.l;
+ W[P0] = R0.l; /* Set Min CLKIN to VCO multiplier */
SSYNC;
IDLE;
@@ -317,29 +319,28 @@
R1 = R1|R2;
R2 = DEPOSIT(R7, R1);
- W[P0] = R2;
+ W[P0] = R2; /* Set Min Core Voltage */
SSYNC;
IDLE;
call _test_pll_locked;
+ R0 = P3;
+ call _set_sic_iwr; /* Set Awake from IDLE */
+
P0.H = hi(PLL_CTL);
P0.L = lo(PLL_CTL);
R0 = W[P0](z);
BITSET (R0, 3);
- W[P0] = R0.L;
-
- R0 = P3;
- call _set_sic_iwr;
-
+ W[P0] = R0.L; /* Turn CCLK OFF */
SSYNC;
IDLE;
call _test_pll_locked;
R0 = IWR_ENABLE(0);
- call _set_sic_iwr;
+ call _set_sic_iwr; /* Set Awake from IDLE PLL */
P0.H = hi(VR_CTL);
P0.L = lo(VR_CTL);
@@ -352,15 +353,15 @@
P0.H = hi(PLL_DIV);
P0.L = lo(PLL_DIV);
- W[P0]= R6;
+ W[P0]= R6; /* Restore CCLK and SCLK divider */
P0.H = hi(PLL_CTL);
P0.L = lo(PLL_CTL);
- w[p0] = R5;
+ w[p0] = R5; /* Restore VCO multiplier */
IDLE;
call _test_pll_locked;
- call _unset_sdram_srfs;
+ call _unset_dram_srfs; /* SDRAM Self Refresh Off */
STI R4;
@@ -368,25 +369,47 @@
( R7:0, P5:0 ) = [SP++];
RTS;
-ENTRY(_set_sdram_srfs)
- /* set the sdram to self refresh mode */
+ENTRY(_set_dram_srfs)
+ /* set the dram to self refresh mode */
+#if defined(CONFIG_BF54x)
+ P0.H = hi(EBIU_RSTCTL);
+ P0.L = lo(EBIU_RSTCTL);
+ R2 = [P0];
+ R3.H = hi(SRREQ);
+ R3.L = lo(SRREQ);
+#else
P0.H = hi(EBIU_SDGCTL);
P0.L = lo(EBIU_SDGCTL);
R2 = [P0];
R3.H = hi(SRFS);
R3.L = lo(SRFS);
+#endif
R2 = R2|R3;
[P0] = R2;
ssync;
+#if defined(CONFIG_BF54x)
+.LSRR_MODE:
+ R2 = [P0];
+ CC = BITTST(R2, 4);
+ if !CC JUMP .LSRR_MODE;
+#endif
RTS;
-ENTRY(_unset_sdram_srfs)
- /* set the sdram out of self refresh mode */
+ENTRY(_unset_dram_srfs)
+ /* set the dram out of self refresh mode */
+#if defined(CONFIG_BF54x)
+ P0.H = hi(EBIU_RSTCTL);
+ P0.L = lo(EBIU_RSTCTL);
+ R2 = [P0];
+ R3.H = hi(SRREQ);
+ R3.L = lo(SRREQ);
+#else
P0.H = hi(EBIU_SDGCTL);
P0.L = lo(EBIU_SDGCTL);
R2 = [P0];
R3.H = hi(SRFS);
R3.L = lo(SRFS);
+#endif
R3 = ~R3;
R2 = R2&R3;
[P0] = R2;
@@ -394,8 +417,13 @@
RTS;
ENTRY(_set_sic_iwr)
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
+ P0.H = hi(SIC_IWR0);
+ P0.L = lo(SIC_IWR0);
+#else
P0.H = hi(SIC_IWR);
P0.L = lo(SIC_IWR);
+#endif
[P0] = R0;
SSYNC;
RTS;
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index dc9d3ee..56ff51b 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -95,6 +95,9 @@
R6 = 0x26; /* Data CPLB Miss */
cc = R6 == R7;
if cc jump _ex_dcplb_miss (BP);
+ R6 = 0x23; /* Data CPLB Miss */
+ cc = R6 == R7;
+ if cc jump _ex_dcplb_viol (BP);
/* Handle 0x23 Data CPLB Protection Violation
* and Data CPLB Multiple Hits - Linux Trap Zero
*/
@@ -102,17 +105,33 @@
ENDPROC(_ex_workaround_261)
#else
+#ifdef CONFIG_MPU
+#define _ex_dviol _ex_dcplb_viol
+#else
#define _ex_dviol _ex_trap_c
+#endif
#define _ex_dmiss _ex_dcplb_miss
#define _ex_dmult _ex_trap_c
#endif
+
+ENTRY(_ex_dcplb_viol)
ENTRY(_ex_dcplb_miss)
ENTRY(_ex_icplb_miss)
(R7:6,P5:4) = [sp++];
ASTAT = [sp++];
SAVE_ALL_SYS
+#ifdef CONFIG_MPU
+ R0 = SEQSTAT;
+ R1 = SP;
+ sp += -12;
+ call _cplb_hdr;
+ sp += 12;
+ CC = R0 == 0;
+ IF !CC JUMP _handle_bad_cplb;
+#else
call __cplb_hdr;
+#endif
DEBUG_START_HWTRACE(p5, r7)
RESTORE_ALL_SYS
SP = EX_SCRATCH_REG;
@@ -329,7 +348,7 @@
R7 = R7 + R6;
P5 = R7;
R1 = [P5];
- [SP + 8] = r1;
+ [SP + PT_SEQSTAT] = r1;
r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
SP += -12;
@@ -633,9 +652,7 @@
[sp + PT_IPEND] = r0;
1:
- r1 = 0x37(Z);
- r2 = ~r1;
- r2.h = 0;
+ r2 = LO(~0x37) (Z);
r0 = r2 & r0;
cc = r0 == 0;
if !cc jump 4f; /* if not return to user mode, get out */
@@ -1364,6 +1381,7 @@
.long _sys_set_robust_list
.long _sys_get_robust_list /* 355 */
.long _sys_fallocate
+ .long _sys_semtimedop
.rept NR_syscalls-(.-_sys_call_table)/4
.long _sys_ni_syscall
.endr
diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S
index 4de3764..7f752c8 100644
--- a/arch/blackfin/mach-common/interrupt.S
+++ b/arch/blackfin/mach-common/interrupt.S
@@ -34,9 +34,13 @@
#include <asm/entry.h>
#include <asm/asm-offsets.h>
#include <asm/trace.h>
+#include <asm/traps.h>
+#include <asm/thread_info.h>
#include <asm/mach-common/context.S>
+.extern _ret_from_exception
+
#ifdef CONFIG_I_ENTRY_L1
.section .l1.text
#else
@@ -117,8 +121,8 @@
#if ANOMALY_05000283 || ANOMALY_05000315
cc = r7 == r7;
- p5.h = 0xffc0;
- p5.l = 0x0014;
+ p5.h = HI(CHIPID);
+ p5.l = LO(CHIPID);
if cc jump 1f;
r7.l = W[p5];
1:
@@ -134,26 +138,22 @@
/* interrupt routine for ivhw - 5 */
ENTRY(_evt_ivhw)
- SAVE_CONTEXT
+ SAVE_ALL_SYS
#ifdef CONFIG_FRAME_POINTER
fp = 0;
#endif
+
#if ANOMALY_05000283
cc = r7 == r7;
- p5.h = 0xffc0;
- p5.l = 0x0014;
+ p5.h = HI(CHIPID);
+ p5.l = LO(CHIPID);
if cc jump 1f;
r7.l = W[p5];
1:
#endif
- trace_buffer_stop(p0, r0);
-
- r0 = IRQ_HWERR;
- r1 = sp;
-
#ifdef CONFIG_HARDWARE_PM
- r7 = SEQSTAT;
+ r7 = [sp + PT_SEQSTAT];
r7 = r7 >>> 0xe;
r6 = 0x1F;
r7 = r7 & r6;
@@ -161,11 +161,29 @@
cc = r7 == r5;
if cc jump .Lcall_do_ovf; /* deal with performance counter overflow */
#endif
+ # We are going to dump something out, so make sure we print IPEND properly
+ p2.l = lo(IPEND);
+ p2.h = hi(IPEND);
+ r0 = [p2];
+ [sp + PT_IPEND] = r0;
+ /* set the EXCAUSE to HWERR for trap_c */
+ r0 = [sp + PT_SEQSTAT];
+ R1.L = LO(VEC_HWERR);
+ R1.H = HI(VEC_HWERR);
+ R0 = R0 | R1;
+ [sp + PT_SEQSTAT] = R0;
+
+ r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
SP += -12;
- call _irq_panic;
+ call _trap_c;
SP += 12;
+
+ call _ret_from_exception;
+.Lcommon_restore_all_sys:
+ RESTORE_ALL_SYS
rti;
+
#ifdef CONFIG_HARDWARE_PM
.Lcall_do_ovf:
@@ -173,9 +191,11 @@
call _pm_overflow;
SP += 12;
- jump .Lcommon_restore_context;
+ jump .Lcommon_restore_all_sys;
#endif
+ENDPROC(_evt_ivhw)
+
/* Interrupt routine for evt2 (NMI).
* We don't actually use this, so just return.
* For inner circle type details, please see:
diff --git a/arch/blackfin/mach-common/ints-priority-dc.c b/arch/blackfin/mach-common/ints-priority-dc.c
index 4882f0e..8d18d6b 100644
--- a/arch/blackfin/mach-common/ints-priority-dc.c
+++ b/arch/blackfin/mach-common/ints-priority-dc.c
@@ -222,11 +222,12 @@
static unsigned int bf561_gpio_irq_startup(unsigned int irq)
{
unsigned int ret;
+ char buf[8];
u16 gpionr = irq - IRQ_PF0;
if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
-
- ret = gpio_request(gpionr, "IRQ");
+ snprintf(buf, sizeof buf, "IRQ %d", irq);
+ ret = gpio_request(gpionr, buf);
if (ret)
return ret;
@@ -250,6 +251,7 @@
{
unsigned int ret;
+ char buf[8];
u16 gpionr = irq - IRQ_PF0;
@@ -265,8 +267,8 @@
IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
-
- ret = gpio_request(gpionr, "IRQ");
+ snprintf(buf, sizeof buf, "IRQ %d", irq);
+ ret = gpio_request(gpionr, buf);
if (ret)
return ret;
diff --git a/arch/blackfin/mach-common/ints-priority-sc.c b/arch/blackfin/mach-common/ints-priority-sc.c
index 147f073..dec42ac 100644
--- a/arch/blackfin/mach-common/ints-priority-sc.c
+++ b/arch/blackfin/mach-common/ints-priority-sc.c
@@ -313,6 +313,7 @@
static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
+
static void bfin_gpio_ack_irq(unsigned int irq)
{
u16 gpionr = irq - IRQ_PF0;
@@ -352,9 +353,11 @@
{
unsigned int ret;
u16 gpionr = irq - IRQ_PF0;
+ char buf[8];
if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
- ret = gpio_request(gpionr, "IRQ");
+ snprintf(buf, sizeof buf, "IRQ %d", irq);
+ ret = gpio_request(gpionr, buf);
if (ret)
return ret;
}
@@ -376,6 +379,7 @@
{
unsigned int ret;
+ char buf[8];
u16 gpionr = irq - IRQ_PF0;
if (type == IRQ_TYPE_PROBE) {
@@ -388,7 +392,8 @@
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
- ret = gpio_request(gpionr, "IRQ");
+ snprintf(buf, sizeof buf, "IRQ %d", irq);
+ ret = gpio_request(gpionr, buf);
if (ret)
return ret;
}
@@ -478,6 +483,10 @@
static unsigned char irq2pint_lut[NR_PINTS];
static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
+static unsigned int gpio_both_edge_triggered[NR_PINT_SYS_IRQS];
+static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
+
+
struct pin_int_t {
unsigned int mask_set;
unsigned int mask_clear;
@@ -544,13 +553,20 @@
}
-static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
-
static void bfin_gpio_ack_irq(unsigned int irq)
{
u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
+ u32 pintbit = PINT_BIT(pint_val);
+ u8 bank = PINT_2_BANK(pint_val);
- pint[PINT_2_BANK(pint_val)]->request = PINT_BIT(pint_val);
+ if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
+ if (pint[bank]->invert_set & pintbit)
+ pint[bank]->invert_clear = pintbit;
+ else
+ pint[bank]->invert_set = pintbit;
+ }
+ pint[bank]->request = pintbit;
+
SSYNC();
}
@@ -560,6 +576,13 @@
u32 pintbit = PINT_BIT(pint_val);
u8 bank = PINT_2_BANK(pint_val);
+ if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
+ if (pint[bank]->invert_set & pintbit)
+ pint[bank]->invert_clear = pintbit;
+ else
+ pint[bank]->invert_set = pintbit;
+ }
+
pint[bank]->request = pintbit;
pint[bank]->mask_clear = pintbit;
SSYNC();
@@ -587,7 +610,8 @@
static unsigned int bfin_gpio_irq_startup(unsigned int irq)
{
unsigned int ret;
- u16 gpionr = irq - IRQ_PA0;
+ char buf[8];
+ u16 gpionr = irq_to_gpio(irq);
u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
if (pint_val == IRQ_NOT_AVAIL) {
@@ -598,7 +622,8 @@
}
if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
- ret = gpio_request(gpionr, "IRQ");
+ snprintf(buf, sizeof buf, "IRQ %d", irq);
+ ret = gpio_request(gpionr, buf);
if (ret)
return ret;
}
@@ -611,16 +636,19 @@
static void bfin_gpio_irq_shutdown(unsigned int irq)
{
+ u16 gpionr = irq_to_gpio(irq);
+
bfin_gpio_mask_irq(irq);
- gpio_free(irq - IRQ_PA0);
- gpio_enabled[gpio_bank(irq - IRQ_PA0)] &= ~gpio_bit(irq - IRQ_PA0);
+ gpio_free(gpionr);
+ gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
}
static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
{
unsigned int ret;
- u16 gpionr = irq - IRQ_PA0;
+ char buf[8];
+ u16 gpionr = irq_to_gpio(irq);
u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
u32 pintbit = PINT_BIT(pint_val);
u8 bank = PINT_2_BANK(pint_val);
@@ -638,7 +666,8 @@
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
- ret = gpio_request(gpionr, "IRQ");
+ snprintf(buf, sizeof buf, "IRQ %d", irq);
+ ret = gpio_request(gpionr, buf);
if (ret)
return ret;
}
@@ -651,29 +680,34 @@
gpio_direction_input(gpionr);
- if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
- pint[bank]->edge_set = pintbit;
- } else {
- pint[bank]->edge_clear = pintbit;
- }
-
if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
else
- pint[bank]->invert_set = pintbit; /* high or rising edge denoted by zero */
+ pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
- if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
- pint[bank]->invert_set = pintbit;
- else
- pint[bank]->invert_set = pintbit;
+ if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
+ == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
+
+ gpio_both_edge_triggered[bank] |= pintbit;
+
+ if (gpio_get_value(gpionr))
+ pint[bank]->invert_set = pintbit;
+ else
+ pint[bank]->invert_clear = pintbit;
+ } else {
+ gpio_both_edge_triggered[bank] &= ~pintbit;
+ }
+
+ if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
+ pint[bank]->edge_set = pintbit;
+ set_irq_handler(irq, handle_edge_irq);
+ } else {
+ pint[bank]->edge_clear = pintbit;
+ set_irq_handler(irq, handle_level_irq);
+ }
SSYNC();
- if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
- set_irq_handler(irq, handle_edge_irq);
- else
- set_irq_handler(irq, handle_level_irq);
-
return 0;
}
diff --git a/arch/blackfin/mach-common/irqpanic.c b/arch/blackfin/mach-common/irqpanic.c
index b22959b..606ded9 100644
--- a/arch/blackfin/mach-common/irqpanic.c
+++ b/arch/blackfin/mach-common/irqpanic.c
@@ -46,9 +46,6 @@
*/
asmlinkage void irq_panic(int reason, struct pt_regs *regs)
{
- int sig = 0;
- siginfo_t info;
-
#ifdef CONFIG_DEBUG_ICACHE_CHECK
unsigned int cmd, tag, ca, cache_hi, cache_lo, *pa;
unsigned short i, j, die;
@@ -136,53 +133,6 @@
}
#endif
- printk(KERN_EMERG "\n");
- printk(KERN_EMERG "Exception: IRQ 0x%x entered\n", reason);
- printk(KERN_EMERG " code=[0x%08lx], stack frame=0x%08lx, "
- " bad PC=0x%08lx\n",
- (unsigned long)regs->seqstat,
- (unsigned long)regs,
- (unsigned long)regs->pc);
- if (reason == 0x5) {
- printk(KERN_EMERG "----------- HARDWARE ERROR -----------\n");
-
- /* There is only need to check for Hardware Errors, since other
- * EXCEPTIONS are handled in TRAPS.c (MH)
- */
- switch (regs->seqstat & SEQSTAT_HWERRCAUSE) {
- case (SEQSTAT_HWERRCAUSE_SYSTEM_MMR): /* System MMR Error */
- info.si_code = BUS_ADRALN;
- sig = SIGBUS;
- printk(KERN_EMERG HWC_x2(KERN_EMERG));
- break;
- case (SEQSTAT_HWERRCAUSE_EXTERN_ADDR): /* External Memory Addressing Error */
- info.si_code = BUS_ADRERR;
- sig = SIGBUS;
- printk(KERN_EMERG HWC_x3(KERN_EMERG));
- break;
- case (SEQSTAT_HWERRCAUSE_PERF_FLOW): /* Performance Monitor Overflow */
- printk(KERN_EMERG HWC_x12(KERN_EMERG));
- break;
- case (SEQSTAT_HWERRCAUSE_RAISE_5): /* RAISE 5 instruction */
- printk(KERN_EMERG HWC_x18(KERN_EMERG));
- break;
- default: /* Reserved */
- printk(KERN_EMERG HWC_default(KERN_EMERG));
- break;
- }
- }
-
- regs->ipend = bfin_read_IPEND();
- dump_bfin_process(regs);
- dump_bfin_mem((void *)regs->pc);
- show_regs(regs);
- if (0 == (info.si_signo = sig) || 0 == user_mode(regs)) /* in kernelspace */
- panic("Unhandled IRQ or exceptions!\n");
- else { /* in userspace */
- info.si_errno = 0;
- info.si_addr = (void *)regs->pc;
- force_sig_info(sig, &info, current);
- }
}
#ifdef CONFIG_HARDWARE_PM
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c
index dac51fb..81930f7 100644
--- a/arch/blackfin/mach-common/pm.c
+++ b/arch/blackfin/mach-common/pm.c
@@ -77,7 +77,15 @@
gpio_pm_restore();
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
+ bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
+ bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
+# ifdef CONFIG_BF54x
+ bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
+# endif
+#else
bfin_write_SIC_IWR(IWR_ENABLE_ALL);
+#endif
local_irq_restore(flags);
}
@@ -85,7 +93,15 @@
#if defined(CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR)
sleep_deeper(CONFIG_PM_WAKEUP_SIC_IWR);
+# if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
+ bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
+ bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
+# ifdef CONFIG_BF54x
+ bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
+# endif
+# else
bfin_write_SIC_IWR(IWR_ENABLE_ALL);
+# endif
#endif /* CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR */
}
diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c
index e97ea8f..eb1a12a 100644
--- a/arch/blackfin/mm/init.c
+++ b/arch/blackfin/mm/init.c
@@ -128,8 +128,8 @@
void __init mem_init(void)
{
unsigned int codek = 0, datak = 0, initk = 0;
+ unsigned int reservedpages = 0, freepages = 0;
unsigned long tmp;
- unsigned int len = _ramend - _rambase;
unsigned long start_mem = memory_start;
unsigned long end_mem = memory_end;
@@ -138,19 +138,36 @@
start_mem = PAGE_ALIGN(start_mem);
max_mapnr = num_physpages = MAP_NR(high_memory);
- printk(KERN_INFO "Physical pages: %lx\n", num_physpages);
+ printk(KERN_INFO "Kernel managed physical pages: %lu\n",
+ num_physpages);
/* This will put all memory onto the freelists. */
totalram_pages = free_all_bootmem();
- codek = (_etext - _stext) >> 10;
- datak = (__bss_stop - __bss_start) >> 10;
- initk = (__init_end - __init_begin) >> 10;
+ reservedpages = 0;
+ for (tmp = 0; tmp < max_mapnr; tmp++)
+ if (PageReserved(pfn_to_page(tmp)))
+ reservedpages++;
+ freepages = max_mapnr - reservedpages;
- tmp = nr_free_pages() << PAGE_SHIFT;
+ /* do not count in kernel image between _rambase and _ramstart */
+ reservedpages -= (_ramstart - _rambase) >> PAGE_SHIFT;
+#if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263)
+ reservedpages += (_ramend - memory_end - DMA_UNCACHED_REGION) >>
+ PAGE_SHIFT;
+#endif
+
+ codek = (_etext - _stext) >> 10;
+ initk = (__init_end - __init_begin) >> 10;
+ datak = ((_ramstart - _rambase) >> 10) - codek - initk;
+
printk(KERN_INFO
- "Memory available: %luk/%uk RAM, (%uk init code, %uk kernel code, %uk data, %uk dma)\n",
- tmp >> 10, len >> 10, initk, codek, datak, DMA_UNCACHED_REGION >> 10);
+ "Memory available: %luk/%luk RAM, "
+ "(%uk init code, %uk kernel code, "
+ "%uk data, %uk dma, %uk reserved)\n",
+ (unsigned long) freepages << (PAGE_SHIFT-10), _ramend >> 10,
+ initk, codek, datak, DMA_UNCACHED_REGION >> 10,
+ (reservedpages << (PAGE_SHIFT-10)));
/* Initialize the blackfin L1 Memory. */
l1sram_init();
@@ -184,13 +201,15 @@
#ifdef CONFIG_BLK_DEV_INITRD
void __init free_initrd_mem(unsigned long start, unsigned long end)
{
+#ifndef CONFIG_MPU
free_init_pages("initrd memory", start, end);
+#endif
}
#endif
void __init free_initmem(void)
{
-#ifdef CONFIG_RAMKERNEL
+#if defined CONFIG_RAMKERNEL && !defined CONFIG_MPU
free_init_pages("unused kernel memory",
(unsigned long)(&__init_begin),
(unsigned long)(&__init_end));
diff --git a/drivers/serial/bfin_5xx.c b/drivers/serial/bfin_5xx.c
index 6f475b6..ac2a3ef 100644
--- a/drivers/serial/bfin_5xx.c
+++ b/drivers/serial/bfin_5xx.c
@@ -442,7 +442,8 @@
set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP,
INTR_ON_BUF,
DIMENSION_LINEAR,
- DATA_SIZE_8));
+ DATA_SIZE_8,
+ DMA_SYNC_RESTART));
set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail));
set_dma_x_count(uart->tx_dma_channel, uart->tx_count);
set_dma_x_modify(uart->tx_dma_channel, 1);
@@ -689,7 +690,8 @@
set_dma_config(uart->rx_dma_channel,
set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO,
INTR_ON_ROW, DIMENSION_2D,
- DATA_SIZE_8));
+ DATA_SIZE_8,
+ DMA_SYNC_RESTART));
set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT);
set_dma_x_modify(uart->rx_dma_channel, 1);
set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT);
diff --git a/drivers/video/bf54x-lq043fb.c b/drivers/video/bf54x-lq043fb.c
index 74d11c3..c8e7427 100644
--- a/drivers/video/bf54x-lq043fb.c
+++ b/drivers/video/bf54x-lq043fb.c
@@ -224,7 +224,8 @@
set_dma_config(CH_EPPI0,
set_bfin_dma_config(DIR_READ, DMA_FLOW_AUTO,
INTR_DISABLE, DIMENSION_2D,
- DATA_SIZE_32));
+ DATA_SIZE_32,
+ DMA_NOSYNC_KEEP_DMA_BUF));
set_dma_x_count(CH_EPPI0, (LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE);
set_dma_x_modify(CH_EPPI0, DMA_BUS_SIZE / 8);
set_dma_y_count(CH_EPPI0, LCD_Y_RES);
@@ -263,8 +264,7 @@
}
}
- gpio_direction_output(disp);
- gpio_set_value(disp, 1);
+ gpio_direction_output(disp, 1);
return 0;
}
diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h
index 39bdd86..6ae0619 100644
--- a/include/asm-blackfin/bfin-global.h
+++ b/include/asm-blackfin/bfin-global.h
@@ -51,7 +51,7 @@
extern unsigned long usecs_to_sclk(unsigned long usecs);
extern void dump_bfin_process(struct pt_regs *regs);
-extern void dump_bfin_mem(void *retaddr);
+extern void dump_bfin_mem(struct pt_regs *regs);
extern void dump_bfin_trace_buffer(void);
extern int init_arch_irq(void);
diff --git a/include/asm-blackfin/cplb-mpu.h b/include/asm-blackfin/cplb-mpu.h
new file mode 100644
index 0000000..75c67b9
--- /dev/null
+++ b/include/asm-blackfin/cplb-mpu.h
@@ -0,0 +1,61 @@
+/*
+ * File: include/asm-blackfin/cplbinit.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Modified:
+ * Copyright 2004-2006 Analog Devices Inc.
+ *
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#ifndef __ASM_BFIN_CPLB_MPU_H
+#define __ASM_BFIN_CPLB_MPU_H
+
+struct cplb_entry {
+ unsigned long data, addr;
+};
+
+struct mem_region {
+ unsigned long start, end;
+ unsigned long dcplb_data;
+ unsigned long icplb_data;
+};
+
+extern struct cplb_entry dcplb_tbl[MAX_CPLBS];
+extern struct cplb_entry icplb_tbl[MAX_CPLBS];
+extern int first_switched_icplb;
+extern int first_mask_dcplb;
+extern int first_switched_dcplb;
+
+extern int nr_dcplb_miss, nr_icplb_miss, nr_icplb_supv_miss, nr_dcplb_prot;
+extern int nr_cplb_flush;
+
+extern int page_mask_order;
+extern int page_mask_nelts;
+
+extern unsigned long *current_rwx_mask;
+
+extern void flush_switched_cplbs(void);
+extern void set_mask_dcplbs(unsigned long *);
+
+extern void __noreturn panic_cplb_error(int seqstat, struct pt_regs *);
+
+#endif /* __ASM_BFIN_CPLB_MPU_H */
diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h
index 06828d7..654375c 100644
--- a/include/asm-blackfin/cplb.h
+++ b/include/asm-blackfin/cplb.h
@@ -65,7 +65,11 @@
#define SIZE_1M 0x00100000 /* 1M */
#define SIZE_4M 0x00400000 /* 4M */
+#ifdef CONFIG_MPU
+#define MAX_CPLBS 16
+#else
#define MAX_CPLBS (16 * 2)
+#endif
#define ASYNC_MEMORY_CPLB_COVERAGE ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M)
diff --git a/include/asm-blackfin/cplbinit.h b/include/asm-blackfin/cplbinit.h
index c4d0596..0eb1c1b 100644
--- a/include/asm-blackfin/cplbinit.h
+++ b/include/asm-blackfin/cplbinit.h
@@ -33,6 +33,12 @@
#include <asm/blackfin.h>
#include <asm/cplb.h>
+#ifdef CONFIG_MPU
+
+#include <asm/cplb-mpu.h>
+
+#else
+
#define INITIAL_T 0x1
#define SWITCH_T 0x2
#define I_CPLB 0x4
@@ -79,6 +85,8 @@
extern u_long dpdt_swapcount_table[];
#endif
+#endif /* CONFIG_MPU */
+
extern unsigned long reserved_mem_dcache_on;
extern unsigned long reserved_mem_icache_on;
diff --git a/include/asm-blackfin/dma.h b/include/asm-blackfin/dma.h
index b469505..5abaa2c 100644
--- a/include/asm-blackfin/dma.h
+++ b/include/asm-blackfin/dma.h
@@ -76,6 +76,9 @@
#define INTR_ON_BUF 2
#define INTR_ON_ROW 3
+#define DMA_NOSYNC_KEEP_DMA_BUF 0
+#define DMA_SYNC_RESTART 1
+
struct dmasg {
unsigned long next_desc_addr;
unsigned long start_addr;
@@ -157,7 +160,8 @@
void set_dma_y_modify(unsigned int channel, short y_modify);
void set_dma_config(unsigned int channel, unsigned short config);
unsigned short set_bfin_dma_config(char direction, char flow_mode,
- char intr_mode, char dma_mode, char width);
+ char intr_mode, char dma_mode, char width,
+ char syncmode);
void set_dma_curr_addr(unsigned int channel, unsigned long addr);
/* get curr status for polling */
diff --git a/include/asm-blackfin/gpio.h b/include/asm-blackfin/gpio.h
index 33ce98e..d0426c1 100644
--- a/include/asm-blackfin/gpio.h
+++ b/include/asm-blackfin/gpio.h
@@ -7,7 +7,7 @@
* Description:
*
* Modified:
- * Copyright 2004-2006 Analog Devices Inc.
+ * Copyright 2004-2008 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
@@ -304,39 +304,39 @@
**************************************************************/
#ifndef BF548_FAMILY
-void set_gpio_dir(unsigned short, unsigned short);
-void set_gpio_inen(unsigned short, unsigned short);
-void set_gpio_polar(unsigned short, unsigned short);
-void set_gpio_edge(unsigned short, unsigned short);
-void set_gpio_both(unsigned short, unsigned short);
-void set_gpio_data(unsigned short, unsigned short);
-void set_gpio_maska(unsigned short, unsigned short);
-void set_gpio_maskb(unsigned short, unsigned short);
-void set_gpio_toggle(unsigned short);
-void set_gpiop_dir(unsigned short, unsigned short);
-void set_gpiop_inen(unsigned short, unsigned short);
-void set_gpiop_polar(unsigned short, unsigned short);
-void set_gpiop_edge(unsigned short, unsigned short);
-void set_gpiop_both(unsigned short, unsigned short);
-void set_gpiop_data(unsigned short, unsigned short);
-void set_gpiop_maska(unsigned short, unsigned short);
-void set_gpiop_maskb(unsigned short, unsigned short);
-unsigned short get_gpio_dir(unsigned short);
-unsigned short get_gpio_inen(unsigned short);
-unsigned short get_gpio_polar(unsigned short);
-unsigned short get_gpio_edge(unsigned short);
-unsigned short get_gpio_both(unsigned short);
-unsigned short get_gpio_maska(unsigned short);
-unsigned short get_gpio_maskb(unsigned short);
-unsigned short get_gpio_data(unsigned short);
-unsigned short get_gpiop_dir(unsigned short);
-unsigned short get_gpiop_inen(unsigned short);
-unsigned short get_gpiop_polar(unsigned short);
-unsigned short get_gpiop_edge(unsigned short);
-unsigned short get_gpiop_both(unsigned short);
-unsigned short get_gpiop_maska(unsigned short);
-unsigned short get_gpiop_maskb(unsigned short);
-unsigned short get_gpiop_data(unsigned short);
+void set_gpio_dir(unsigned, unsigned short);
+void set_gpio_inen(unsigned, unsigned short);
+void set_gpio_polar(unsigned, unsigned short);
+void set_gpio_edge(unsigned, unsigned short);
+void set_gpio_both(unsigned, unsigned short);
+void set_gpio_data(unsigned, unsigned short);
+void set_gpio_maska(unsigned, unsigned short);
+void set_gpio_maskb(unsigned, unsigned short);
+void set_gpio_toggle(unsigned);
+void set_gpiop_dir(unsigned, unsigned short);
+void set_gpiop_inen(unsigned, unsigned short);
+void set_gpiop_polar(unsigned, unsigned short);
+void set_gpiop_edge(unsigned, unsigned short);
+void set_gpiop_both(unsigned, unsigned short);
+void set_gpiop_data(unsigned, unsigned short);
+void set_gpiop_maska(unsigned, unsigned short);
+void set_gpiop_maskb(unsigned, unsigned short);
+unsigned short get_gpio_dir(unsigned);
+unsigned short get_gpio_inen(unsigned);
+unsigned short get_gpio_polar(unsigned);
+unsigned short get_gpio_edge(unsigned);
+unsigned short get_gpio_both(unsigned);
+unsigned short get_gpio_maska(unsigned);
+unsigned short get_gpio_maskb(unsigned);
+unsigned short get_gpio_data(unsigned);
+unsigned short get_gpiop_dir(unsigned);
+unsigned short get_gpiop_inen(unsigned);
+unsigned short get_gpiop_polar(unsigned);
+unsigned short get_gpiop_edge(unsigned);
+unsigned short get_gpiop_both(unsigned);
+unsigned short get_gpiop_maska(unsigned);
+unsigned short get_gpiop_maskb(unsigned);
+unsigned short get_gpiop_data(unsigned);
struct gpio_port_t {
unsigned short data;
@@ -382,8 +382,8 @@
#define PM_WAKE_LOW 0x8
#define PM_WAKE_BOTH_EDGES (PM_WAKE_RISING | PM_WAKE_FALLING)
-int gpio_pm_wakeup_request(unsigned short gpio, unsigned char type);
-void gpio_pm_wakeup_free(unsigned short gpio);
+int gpio_pm_wakeup_request(unsigned gpio, unsigned char type);
+void gpio_pm_wakeup_free(unsigned gpio);
unsigned int gpio_pm_setup(void);
void gpio_pm_restore(void);
@@ -426,19 +426,19 @@
* MODIFICATION HISTORY :
**************************************************************/
-int gpio_request(unsigned short, const char *);
-void gpio_free(unsigned short);
+int gpio_request(unsigned, const char *);
+void gpio_free(unsigned);
-void gpio_set_value(unsigned short gpio, unsigned short arg);
-unsigned short gpio_get_value(unsigned short gpio);
+void gpio_set_value(unsigned gpio, int arg);
+int gpio_get_value(unsigned gpio);
#ifndef BF548_FAMILY
#define gpio_get_value(gpio) get_gpio_data(gpio)
#define gpio_set_value(gpio, value) set_gpio_data(gpio, value)
#endif
-void gpio_direction_input(unsigned short gpio);
-void gpio_direction_output(unsigned short gpio);
+int gpio_direction_input(unsigned gpio);
+int gpio_direction_output(unsigned gpio, int value);
#include <asm-generic/gpio.h> /* cansleep wrappers */
#include <asm/irq.h>
diff --git a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
index 0b867e6..15dbc21 100644
--- a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
@@ -146,7 +146,7 @@
if (uart->rts_pin >= 0) {
gpio_request(uart->rts_pin, DRIVER_NAME);
- gpio_direction_output(uart->rts_pin);
+ gpio_direction_output(uart->rts_pin, 0);
}
#endif
}
diff --git a/include/asm-blackfin/mach-bf527/portmux.h b/include/asm-blackfin/mach-bf527/portmux.h
index dcf001a..ae4d205 100644
--- a/include/asm-blackfin/mach-bf527/portmux.h
+++ b/include/asm-blackfin/mach-bf527/portmux.h
@@ -1,6 +1,8 @@
#ifndef _MACH_PORTMUX_H_
#define _MACH_PORTMUX_H_
+#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
+
#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h
index f36ff5af..98209d4 100644
--- a/include/asm-blackfin/mach-bf533/anomaly.h
+++ b/include/asm-blackfin/mach-bf533/anomaly.h
@@ -7,9 +7,7 @@
*/
/* This file shoule be up to date with:
- * - Revision X, March 23, 2007; ADSP-BF533 Blackfin Processor Anomaly List
- * - Revision AB, March 23, 2007; ADSP-BF532 Blackfin Processor Anomaly List
- * - Revision W, March 23, 2007; ADSP-BF531 Blackfin Processor Anomaly List
+ * - Revision B, 12/10/2007; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
@@ -17,7 +15,7 @@
/* We do not support 0.1 or 0.2 silicon - sorry */
#if __SILICON_REVISION__ < 3
-# error Kernel will not work on BF533 silicon version 0.0, 0.1, or 0.2
+# error will not work on BF533 silicon version 0.0, 0.1, or 0.2
#endif
#if defined(__ADSPBF531__)
@@ -251,6 +249,12 @@
#define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
/* Internal Voltage Regulator may not start up */
#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
+/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
+#define ANOMALY_05000357 (1)
+/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
+#define ANOMALY_05000366 (1)
+/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
+#define ANOMALY_05000371 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000266 (0)
diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
index 69b9f8e..7871d43 100644
--- a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
@@ -111,7 +111,7 @@
}
if (uart->rts_pin >= 0) {
gpio_request(uart->rts_pin, DRIVER_NAME);
- gpio_direction_input(uart->rts_pin);
+ gpio_direction_input(uart->rts_pin, 0);
}
#endif
}
diff --git a/include/asm-blackfin/mach-bf533/portmux.h b/include/asm-blackfin/mach-bf533/portmux.h
index 137f488..685a265 100644
--- a/include/asm-blackfin/mach-bf533/portmux.h
+++ b/include/asm-blackfin/mach-bf533/portmux.h
@@ -1,6 +1,8 @@
#ifndef _MACH_PORTMUX_H_
#define _MACH_PORTMUX_H_
+#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
+
#define P_PPI0_CLK (P_DONTCARE)
#define P_PPI0_FS1 (P_DONTCARE)
#define P_PPI0_FS2 (P_DONTCARE)
diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h
index 2b66ecf..746a794 100644
--- a/include/asm-blackfin/mach-bf537/anomaly.h
+++ b/include/asm-blackfin/mach-bf537/anomaly.h
@@ -7,9 +7,7 @@
*/
/* This file shoule be up to date with:
- * - Revision M, March 13, 2007; ADSP-BF537 Blackfin Processor Anomaly List
- * - Revision L, March 13, 2007; ADSP-BF536 Blackfin Processor Anomaly List
- * - Revision M, March 13, 2007; ADSP-BF534 Blackfin Processor Anomaly List
+ * - Revision A, 09/04/2007; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
@@ -17,7 +15,7 @@
/* We do not support 0.1 silicon - sorry */
#if __SILICON_REVISION__ < 2
-# error Kernel will not work on BF537 silicon version 0.0 or 0.1
+# error will not work on BF537 silicon version 0.0 or 0.1
#endif
#if defined(__ADSPBF534__)
@@ -44,6 +42,8 @@
#define ANOMALY_05000122 (1)
/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
+/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
+#define ANOMALY_05000167 (1)
/* PPI_DELAY not functional in PPI modes with 0 frame syncs */
#define ANOMALY_05000180 (1)
/* Instruction Cache Is Not Functional */
@@ -130,6 +130,12 @@
#define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */
#define ANOMALY_05000322 (1)
+/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
+#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
+/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
+#define ANOMALY_05000357 (1)
+/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
+#define ANOMALY_05000359 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000125 (0)
diff --git a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
index 6fb328f..86e45c3 100644
--- a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
@@ -146,7 +146,7 @@
if (uart->rts_pin >= 0) {
gpio_request(uart->rts_pin, DRIVER_NAME);
- gpio_direction_output(uart->rts_pin);
+ gpio_direction_output(uart->rts_pin, 0);
}
#endif
}
diff --git a/include/asm-blackfin/mach-bf537/portmux.h b/include/asm-blackfin/mach-bf537/portmux.h
index 5a3f7d3..78fee6e 100644
--- a/include/asm-blackfin/mach-bf537/portmux.h
+++ b/include/asm-blackfin/mach-bf537/portmux.h
@@ -1,6 +1,8 @@
#ifndef _MACH_PORTMUX_H_
#define _MACH_PORTMUX_H_
+#define MAX_RESOURCES (MAX_BLACKFIN_GPIOS + GPIO_BANKSIZE) /* We additionally handle PORTJ */
+
#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h
index c5b6375..850dc12 100644
--- a/include/asm-blackfin/mach-bf548/anomaly.h
+++ b/include/asm-blackfin/mach-bf548/anomaly.h
@@ -7,7 +7,7 @@
*/
/* This file shoule be up to date with:
- * - Revision C, July 16, 2007; ADSP-BF549 Silicon Anomaly List
+ * - Revision E, 11/28/2007; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
@@ -26,47 +26,59 @@
/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
#define ANOMALY_05000272 (1)
/* False Hardware Error Exception when ISR context is not restored */
-#define ANOMALY_05000281 (1)
+#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
-#define ANOMALY_05000304 (1)
+#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000310 (1)
/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (1)
+#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
/* TWI Slave Boot Mode Is Not Functional */
-#define ANOMALY_05000324 (1)
+#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
/* External FIFO Boot Mode Is Not Functional */
-#define ANOMALY_05000325 (1)
+#define ANOMALY_05000325 (__SILICON_REVISION__ < 1)
/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
-#define ANOMALY_05000327 (1)
+#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
/* Incorrect Access of OTP_STATUS During otp_write() Function */
-#define ANOMALY_05000328 (1)
+#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
/* Synchronous Burst Flash Boot Mode Is Not Functional */
-#define ANOMALY_05000329 (1)
+#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
/* Host DMA Boot Mode Is Not Functional */
-#define ANOMALY_05000330 (1)
+#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
-#define ANOMALY_05000334 (1)
+#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
/* Inadequate Rotary Debounce Logic Duration */
-#define ANOMALY_05000335 (1)
+#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
-#define ANOMALY_05000336 (1)
+#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
-#define ANOMALY_05000337 (1)
+#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
-#define ANOMALY_05000338 (1)
+#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
-#define ANOMALY_05000340 (1)
+#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
-#define ANOMALY_05000344 (1)
+#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
/* USB Calibration Value Is Not Intialized */
-#define ANOMALY_05000346 (1)
+#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
-#define ANOMALY_05000347 (1)
+#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
/* Data Lost when Core Reads SDH Data FIFO */
-#define ANOMALY_05000349 (1)
+#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
/* PLL Status Register Is Inaccurate */
-#define ANOMALY_05000351 (1)
+#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
+/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
+#define ANOMALY_05000357 (1)
+/* External Memory Read Access Hangs Core With PLL Bypass */
+#define ANOMALY_05000360 (1)
+/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
+#define ANOMALY_05000365 (1)
+/* Addressing Conflict between Boot ROM and Asynchronous Memory */
+#define ANOMALY_05000369 (1)
+/* Mobile DDR Operation Not Functional */
+#define ANOMALY_05000377 (1)
+/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
+#define ANOMALY_05000378 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000125 (0)
diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
index f21a162..3770aa3 100644
--- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
@@ -186,7 +186,7 @@
if (uart->rts_pin >= 0) {
gpio_request(uart->rts_pin, DRIVER_NAME);
- gpio_direction_output(uart->rts_pin);
+ gpio_direction_output(uart->rts_pin, 0);
}
#endif
}
diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
index aefab3f..19ddcd8 100644
--- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
@@ -244,39 +244,6 @@
#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
-#define bfin_read_TWI_CLKDIV() bfin_read16(TWI0_CLKDIV)
-#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val)
-#define bfin_read_TWI_CONTROL() bfin_read16(TWI0_CONTROL)
-#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI0_CONTROL, val)
-#define bfin_read_TWI_SLAVE_CTRL() bfin_read16(TWI0_SLAVE_CTRL)
-#define bfin_write_TWI_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val)
-#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT)
-#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
-#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
-#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
-#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI0_MASTER_CTRL)
-#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTRL, val)
-#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT)
-#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
-#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
-#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
-#define bfin_read_TWI_INT_STAT() bfin_read16(TWI0_INT_STAT)
-#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val)
-#define bfin_read_TWI_INT_MASK() bfin_read16(TWI0_INT_MASK)
-#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val)
-#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI0_FIFO_CTRL)
-#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTRL, val)
-#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT)
-#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
-#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8)
-#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
-#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16)
-#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
-#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8)
-#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
-#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
-#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
-
/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
/* SPORT1 Registers */
diff --git a/include/asm-blackfin/mach-bf548/defBF542.h b/include/asm-blackfin/mach-bf548/defBF542.h
index 32d0713..a7c809f 100644
--- a/include/asm-blackfin/mach-bf548/defBF542.h
+++ b/include/asm-blackfin/mach-bf548/defBF542.h
@@ -432,8 +432,8 @@
#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
-#define CMD_TIMEOUT 0x4 /* CMD Time Out */
-#define DAT_TIMEOUT 0x8 /* Data Time Out */
+#define CMD_TIME_OUT 0x4 /* CMD Time Out */
+#define DAT_TIME_OUT 0x8 /* Data Time Out */
#define TX_UNDERRUN 0x10 /* Transmit Underrun */
#define RX_OVERRUN 0x20 /* Receive Overrun */
#define CMD_RESP_END 0x40 /* CMD Response End */
diff --git a/include/asm-blackfin/mach-bf548/defBF548.h b/include/asm-blackfin/mach-bf548/defBF548.h
index ecbca95..e46f568 100644
--- a/include/asm-blackfin/mach-bf548/defBF548.h
+++ b/include/asm-blackfin/mach-bf548/defBF548.h
@@ -1095,8 +1095,8 @@
#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
-#define CMD_TIMEOUT 0x4 /* CMD Time Out */
-#define DAT_TIMEOUT 0x8 /* Data Time Out */
+#define CMD_TIME_OUT 0x4 /* CMD Time Out */
+#define DAT_TIME_OUT 0x8 /* Data Time Out */
#define TX_UNDERRUN 0x10 /* Transmit Underrun */
#define RX_OVERRUN 0x20 /* Receive Overrun */
#define CMD_RESP_END 0x40 /* CMD Response End */
diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h
index 319a485..08f90c2 100644
--- a/include/asm-blackfin/mach-bf548/defBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h
@@ -1772,17 +1772,36 @@
#define TRP 0x3c0000 /* Pre charge-to-active command period */
#define TRAS 0x3c00000 /* Min Active-to-pre charge time */
#define TRC 0x3c000000 /* Active-to-active time */
+#define DDR_TRAS(x) ((x<<22)&TRAS) /* DDR tRAS = (1~15) cycles */
+#define DDR_TRP(x) ((x<<18)&TRP) /* DDR tRP = (1~15) cycles */
+#define DDR_TRC(x) ((x<<26)&TRC) /* DDR tRC = (1~15) cycles */
+#define DDR_TRFC(x) ((x<<14)&TRFC) /* DDR tRFC = (1~15) cycles */
+#define DDR_TREFI(x) (x&TREFI) /* DDR tRFC = (1~15) cycles */
/* Bit masks for EBIU_DDRCTL1 */
#define TRCD 0xf /* Active-to-Read/write delay */
-#define MRD 0xf0 /* Mode register set to active */
+#define TMRD 0xf0 /* Mode register set to active */
#define TWR 0x300 /* Write Recovery time */
#define DDRDATWIDTH 0x3000 /* DDR data width */
#define EXTBANKS 0xc000 /* External banks */
#define DDRDEVWIDTH 0x30000 /* DDR device width */
#define DDRDEVSIZE 0xc0000 /* DDR device size */
-#define TWWTR 0xf0000000 /* Write-to-read delay */
+#define TWTR 0xf0000000 /* Write-to-read delay */
+#define DDR_TWTR(x) ((x<<28)&TWTR) /* DDR tWTR = (1~15) cycles */
+#define DDR_TMRD(x) ((x<<4)&TMRD) /* DDR tMRD = (1~15) cycles */
+#define DDR_TWR(x) ((x<<8)&TWR) /* DDR tWR = (1~15) cycles */
+#define DDR_TRCD(x) (x&TRCD) /* DDR tRCD = (1~15) cycles */
+#define DDR_DATWIDTH 0x2000 /* DDR data width */
+#define EXTBANK_1 0 /* 1 external bank */
+#define EXTBANK_2 0x4000 /* 2 external banks */
+#define DEVSZ_64 0x40000 /* DDR External Bank Size = 64MB */
+#define DEVSZ_128 0x80000 /* DDR External Bank Size = 128MB */
+#define DEVSZ_256 0xc0000 /* DDR External Bank Size = 256MB */
+#define DEVSZ_512 0 /* DDR External Bank Size = 512MB */
+#define DEVWD_4 0 /* DDR Device Width = 4 Bits */
+#define DEVWD_8 0x10000 /* DDR Device Width = 8 Bits */
+#define DEVWD_16 0x20000 /* DDR Device Width = 16 Bits */
/* Bit masks for EBIU_DDRCTL2 */
@@ -1790,6 +1809,10 @@
#define CASLATENCY 0x70 /* CAS latency */
#define DLLRESET 0x100 /* DLL Reset */
#define REGE 0x1000 /* Register mode enable */
+#define CL_1_5 0x50 /* DDR CAS Latency = 1.5 cycles */
+#define CL_2 0x20 /* DDR CAS Latency = 2 cycles */
+#define CL_2_5 0x60 /* DDR CAS Latency = 2.5 cycles */
+#define CL_3 0x30 /* DDR CAS Latency = 3 cycles */
/* Bit masks for EBIU_DDRCTL3 */
@@ -2257,6 +2280,10 @@
#define CSEL 0x30 /* Core Select */
#define SSEL 0xf /* System Select */
+#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
+#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
+#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
+#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
/* Bit masks for PLL_CTL */
diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h
index 9fb7bc5..c34507a 100644
--- a/include/asm-blackfin/mach-bf548/irq.h
+++ b/include/asm-blackfin/mach-bf548/irq.h
@@ -88,7 +88,7 @@
#define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */
#define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */
#define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */
-#define IRQ_WATCHDOG BFIN_IRQ(23) /* Watchdog Interrupt */
+#define IRQ_WATCH BFIN_IRQ(23) /* Watchdog Interrupt */
#define IRQ_DMAC1_ERROR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */
#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Error Interrupt */
#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Error Interrupt */
@@ -406,7 +406,7 @@
#define IRQ_PINT1_POS 16
#define IRQ_MDMAS0_POS 20
#define IRQ_MDMAS1_POS 24
-#define IRQ_WATCHDOG_POS 28
+#define IRQ_WATCH_POS 28
/* IAR3 BIT FIELDS */
#define IRQ_DMAC1_ERR_POS 0
diff --git a/include/asm-blackfin/mach-bf548/mem_init.h b/include/asm-blackfin/mach-bf548/mem_init.h
index 0cb279e..befc290 100644
--- a/include/asm-blackfin/mach-bf548/mem_init.h
+++ b/include/asm-blackfin/mach-bf548/mem_init.h
@@ -28,8 +28,68 @@
* If not, write to the Free Software Foundation,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
+#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
-#if (CONFIG_MEM_MT46V32M16)
+#if (CONFIG_MEM_MT46V32M16_6T)
+#define DDR_SIZE DEVSZ_512
+#define DDR_WIDTH DEVWD_16
+
+#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60))
+#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42))
+#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
+#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72))
+#define DDR_tREFI DDR_TREFI(MIN_DDR_SCLK(7800))
+
+#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
+#define DDR_tWTR DDR_TWTR(1)
+#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12))
+#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
+#endif
+
+#if (CONFIG_MEM_MT46V32M16_5B)
+#define DDR_SIZE DEVSZ_512
+#define DDR_WIDTH DEVWD_16
+
+#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55))
+#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40))
+#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
+#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70))
+#define DDR_tREFI DDR_TREFI(MIN_DDR_SCLK(7800))
+
+#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
+#define DDR_tWTR DDR_TWTR(2)
+#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10))
+#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
+#endif
+
+#if (CONFIG_MEM_GENERIC_BOARD)
+#define DDR_SIZE DEVSZ_512
+#define DDR_WIDTH DEVWD_16
+
+#define DDR_tRCD DDR_TRCD(3)
+#define DDR_tWTR DDR_TWTR(2)
+#define DDR_tWR DDR_TWR(2)
+#define DDR_tMRD DDR_TMRD(2)
+#define DDR_tRP DDR_TRP(3)
+#define DDR_tRAS DDR_TRAS(7)
+#define DDR_tRC DDR_TRC(10)
+#define DDR_tRFC DDR_TRFC(12)
+#define DDR_tREFI DDR_TREFI(1288)
+#endif
+
+#if (CONFIG_SCLK_HZ <= 133333333)
+#define DDR_CL CL_2
+#elif (CONFIG_SCLK_HZ <= 166666666)
+#define DDR_CL CL_2_5
+#else
+#define DDR_CL CL_3
+#endif
+
+#define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
+#define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
+ | DDR_tMRD | DDR_tWR | DDR_tRCD)
+#define mem_DDRCTL2 DDR_CL
+
#if defined CONFIG_CLKIN_HALF
#define CLKIN_HALF 1
diff --git a/include/asm-blackfin/mach-bf548/portmux.h b/include/asm-blackfin/mach-bf548/portmux.h
index 6b48512..8177a56 100644
--- a/include/asm-blackfin/mach-bf548/portmux.h
+++ b/include/asm-blackfin/mach-bf548/portmux.h
@@ -1,6 +1,8 @@
#ifndef _MACH_PORTMUX_H_
#define _MACH_PORTMUX_H_
+#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
+
#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h
index bed9564..0c1d461 100644
--- a/include/asm-blackfin/mach-bf561/anomaly.h
+++ b/include/asm-blackfin/mach-bf561/anomaly.h
@@ -7,7 +7,7 @@
*/
/* This file shoule be up to date with:
- * - Revision N, March 28, 2007; ADSP-BF561 Silicon Anomaly List
+ * - Revision O, 11/15/2007; ADSP-BF561 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
@@ -15,7 +15,7 @@
/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */
#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4
-# error Kernel will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
+# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
#endif
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
@@ -208,6 +208,8 @@
#define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
#define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
+/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */
+#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
/* False Hardware Error Exception When ISR Context Is Not Restored */
@@ -246,6 +248,18 @@
#define ANOMALY_05000332 (__SILICON_REVISION__ < 5)
/* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */
#define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
+/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available on Older Silicon) */
+#define ANOMALY_05000339 (__SILICON_REVISION__ < 5)
+/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */
+#define ANOMALY_05000343 (__SILICON_REVISION__ < 5)
+/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
+#define ANOMALY_05000357 (1)
+/* Conflicting Column Address Widths Causes SDRAM Errors */
+#define ANOMALY_05000362 (1)
+/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
+#define ANOMALY_05000366 (1)
+/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
+#define ANOMALY_05000371 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000158 (0)
diff --git a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
index 69b9f8e..7871d43 100644
--- a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
@@ -111,7 +111,7 @@
}
if (uart->rts_pin >= 0) {
gpio_request(uart->rts_pin, DRIVER_NAME);
- gpio_direction_input(uart->rts_pin);
+ gpio_direction_input(uart->rts_pin, 0);
}
#endif
}
diff --git a/include/asm-blackfin/mach-bf561/portmux.h b/include/asm-blackfin/mach-bf561/portmux.h
index 132ad31..a6ee820 100644
--- a/include/asm-blackfin/mach-bf561/portmux.h
+++ b/include/asm-blackfin/mach-bf561/portmux.h
@@ -1,6 +1,8 @@
#ifndef _MACH_PORTMUX_H_
#define _MACH_PORTMUX_H_
+#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
+
#define P_PPI0_CLK (P_DONTCARE)
#define P_PPI0_FS1 (P_DONTCARE)
#define P_PPI0_FS2 (P_DONTCARE)
diff --git a/include/asm-blackfin/mmu.h b/include/asm-blackfin/mmu.h
index 11d52f1..757e439 100644
--- a/include/asm-blackfin/mmu.h
+++ b/include/asm-blackfin/mmu.h
@@ -24,7 +24,9 @@
unsigned long exec_fdpic_loadmap;
unsigned long interp_fdpic_loadmap;
#endif
-
+#ifdef CONFIG_MPU
+ unsigned long *page_rwx_mask;
+#endif
} mm_context_t;
#endif
diff --git a/include/asm-blackfin/mmu_context.h b/include/asm-blackfin/mmu_context.h
index c5c71a6..b5eb675 100644
--- a/include/asm-blackfin/mmu_context.h
+++ b/include/asm-blackfin/mmu_context.h
@@ -30,9 +30,12 @@
#ifndef __BLACKFIN_MMU_CONTEXT_H__
#define __BLACKFIN_MMU_CONTEXT_H__
+#include <linux/gfp.h>
+#include <linux/sched.h>
#include <asm/setup.h>
#include <asm/page.h>
#include <asm/pgalloc.h>
+#include <asm/cplbinit.h>
extern void *current_l1_stack_save;
extern int nr_l1stack_tasks;
@@ -50,6 +53,12 @@
static inline int
init_new_context(struct task_struct *tsk, struct mm_struct *mm)
{
+#ifdef CONFIG_MPU
+ unsigned long p = __get_free_pages(GFP_KERNEL, page_mask_order);
+ mm->context.page_rwx_mask = (unsigned long *)p;
+ memset(mm->context.page_rwx_mask, 0,
+ page_mask_nelts * 3 * sizeof(long));
+#endif
return 0;
}
@@ -73,6 +82,11 @@
sram_free(tmp->addr);
kfree(tmp);
}
+#ifdef CONFIG_MPU
+ if (current_rwx_mask == mm->context.page_rwx_mask)
+ current_rwx_mask = NULL;
+ free_pages((unsigned long)mm->context.page_rwx_mask, page_mask_order);
+#endif
}
static inline unsigned long
@@ -106,9 +120,21 @@
#define deactivate_mm(tsk,mm) do { } while (0)
-static inline void activate_mm(struct mm_struct *prev_mm,
- struct mm_struct *next_mm)
+#define activate_mm(prev, next) switch_mm(prev, next, NULL)
+
+static inline void switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm,
+ struct task_struct *tsk)
{
+ if (prev_mm == next_mm)
+ return;
+#ifdef CONFIG_MPU
+ if (prev_mm->context.page_rwx_mask == current_rwx_mask) {
+ flush_switched_cplbs();
+ set_mask_dcplbs(next_mm->context.page_rwx_mask);
+ }
+#endif
+
+ /* L1 stack switching. */
if (!next_mm->context.l1_stack_save)
return;
if (next_mm->context.l1_stack_save == current_l1_stack_save)
@@ -120,10 +146,36 @@
memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len);
}
-static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
- struct task_struct *tsk)
+#ifdef CONFIG_MPU
+static inline void protect_page(struct mm_struct *mm, unsigned long addr,
+ unsigned long flags)
{
- activate_mm(prev, next);
+ unsigned long *mask = mm->context.page_rwx_mask;
+ unsigned long page = addr >> 12;
+ unsigned long idx = page >> 5;
+ unsigned long bit = 1 << (page & 31);
+
+ if (flags & VM_MAYREAD)
+ mask[idx] |= bit;
+ else
+ mask[idx] &= ~bit;
+ mask += page_mask_nelts;
+ if (flags & VM_MAYWRITE)
+ mask[idx] |= bit;
+ else
+ mask[idx] &= ~bit;
+ mask += page_mask_nelts;
+ if (flags & VM_MAYEXEC)
+ mask[idx] |= bit;
+ else
+ mask[idx] &= ~bit;
}
+static inline void update_protections(struct mm_struct *mm)
+{
+ flush_switched_cplbs();
+ set_mask_dcplbs(mm->context.page_rwx_mask);
+}
+#endif
+
#endif
diff --git a/include/asm-blackfin/traps.h b/include/asm-blackfin/traps.h
index ee1cbf7..f0e5f94 100644
--- a/include/asm-blackfin/traps.h
+++ b/include/asm-blackfin/traps.h
@@ -45,6 +45,10 @@
#define VEC_CPLB_I_M (44)
#define VEC_CPLB_I_MHIT (45)
#define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */
+/* The hardware reserves (63) for future use - we use it to tell our
+ * normal exception handling code we have a hardware error
+ */
+#define VEC_HWERR (63)
#ifndef __ASSEMBLY__
diff --git a/include/asm-blackfin/uaccess.h b/include/asm-blackfin/uaccess.h
index 2233f8f..22a410b 100644
--- a/include/asm-blackfin/uaccess.h
+++ b/include/asm-blackfin/uaccess.h
@@ -31,7 +31,7 @@
#define VERIFY_READ 0
#define VERIFY_WRITE 1
-#define access_ok(type,addr,size) _access_ok((unsigned long)(addr),(size))
+#define access_ok(type, addr, size) _access_ok((unsigned long)(addr), (size))
static inline int is_in_rom(unsigned long addr)
{
diff --git a/include/asm-blackfin/unistd.h b/include/asm-blackfin/unistd.h
index 07ffe8b..e981673 100644
--- a/include/asm-blackfin/unistd.h
+++ b/include/asm-blackfin/unistd.h
@@ -369,8 +369,9 @@
#define __NR_set_robust_list 354
#define __NR_get_robust_list 355
#define __NR_fallocate 356
+#define __NR_semtimedop 357
-#define __NR_syscall 357
+#define __NR_syscall 358
#define NR_syscalls __NR_syscall
/* Old optional stuff no one actually uses */
