| commit | 80fbe6ac9b47cbc11e174a9bf853834dc281da35 | [log] [tgz] |
|---|---|---|
| author | Daniel Glöckner <dg@emlix.com> | Mon Apr 06 11:50:22 2009 +0200 |
| committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | Mon Apr 06 11:18:39 2009 +0100 |
| tree | 1ad5a6dfdf219fd8e8ce3e0a0ec0be26b11d96a7 | |
| parent | 2b7dbbe0c9491e62b50978d1615193bec33a8291 [diff] |
ASoC: correct s6000 I2S clock polarity According to the data sheet data is clocked out on the falling edge and latched on the rising edge of the bit clock. While the left sample is transmitted the word clock line is low. Signed-off-by: Daniel Glöckner <dg@emlix.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>