[IA64] Altix system controller event handling
The following is an update of the patch I sent yesterday
(3/9/05) incorporating suggestions from Christoph Hellwig and
Andreas Schwab. It allows Altix and Altix-like systems to
handle environmental events generated by the system controllers,
and should apply on top of Jack Steiner's patch of 3/1/05 ("New
chipset support for SN platform") and Mark Goodwin's patch of
3/8/05 ("Altix SN topology support for new chipsets and pci
topology").
Signed-off-by: Greg Howard <ghoward@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
diff --git a/drivers/char/Makefile b/drivers/char/Makefile
index 3ea8cc8..e3f5c32 100644
--- a/drivers/char/Makefile
+++ b/drivers/char/Makefile
@@ -42,7 +42,7 @@
obj-$(CONFIG_RIO) += rio/ generic_serial.o
obj-$(CONFIG_HVC_CONSOLE) += hvc_console.o hvsi.o
obj-$(CONFIG_RAW_DRIVER) += raw.o
-obj-$(CONFIG_SGI_SNSC) += snsc.o
+obj-$(CONFIG_SGI_SNSC) += snsc.o snsc_event.o
obj-$(CONFIG_MMTIMER) += mmtimer.o
obj-$(CONFIG_VIOCONS) += viocons.o
obj-$(CONFIG_VIOTAPE) += viotape.o
diff --git a/drivers/char/snsc.c b/drivers/char/snsc.c
index ffb9143..e3c0b52 100644
--- a/drivers/char/snsc.c
+++ b/drivers/char/snsc.c
@@ -374,6 +374,7 @@
void *salbuf;
struct class_simple *snsc_class;
dev_t first_dev, dev;
+ nasid_t event_nasid = ia64_sn_get_console_nasid();
if (alloc_chrdev_region(&first_dev, 0, numionodes,
SYSCTL_BASENAME) < 0) {
@@ -441,6 +442,13 @@
ia64_sn_irtr_intr_enable(scd->scd_nasid,
0 /*ignored */ ,
SAL_IROUTER_INTR_RECV);
+
+ /* on the console nasid, prepare to receive
+ * system controller environmental events
+ */
+ if(scd->scd_nasid == event_nasid) {
+ scdrv_event_init(scd);
+ }
}
return 0;
}
diff --git a/drivers/char/snsc.h b/drivers/char/snsc.h
index c22c6c5..a9efc13 100644
--- a/drivers/char/snsc.h
+++ b/drivers/char/snsc.h
@@ -47,4 +47,44 @@
nasid_t scd_nasid; /* Node on which subchannels are opened. */
};
+
+/* argument types */
+#define IR_ARG_INT 0x00 /* 4-byte integer (big-endian) */
+#define IR_ARG_ASCII 0x01 /* null-terminated ASCII string */
+#define IR_ARG_UNKNOWN 0x80 /* unknown data type. The low
+ * 7 bits will contain the data
+ * length. */
+#define IR_ARG_UNKNOWN_LENGTH_MASK 0x7f
+
+
+/* system controller event codes */
+#define EV_CLASS_MASK 0xf000ul
+#define EV_SEVERITY_MASK 0x0f00ul
+#define EV_COMPONENT_MASK 0x00fful
+
+#define EV_CLASS_POWER 0x1000ul
+#define EV_CLASS_FAN 0x2000ul
+#define EV_CLASS_TEMP 0x3000ul
+#define EV_CLASS_ENV 0x4000ul
+#define EV_CLASS_TEST_FAULT 0x5000ul
+#define EV_CLASS_TEST_WARNING 0x6000ul
+#define EV_CLASS_PWRD_NOTIFY 0x8000ul
+
+#define EV_SEVERITY_POWER_STABLE 0x0000ul
+#define EV_SEVERITY_POWER_LOW_WARNING 0x0100ul
+#define EV_SEVERITY_POWER_HIGH_WARNING 0x0200ul
+#define EV_SEVERITY_POWER_HIGH_FAULT 0x0300ul
+#define EV_SEVERITY_POWER_LOW_FAULT 0x0400ul
+
+#define EV_SEVERITY_FAN_STABLE 0x0000ul
+#define EV_SEVERITY_FAN_WARNING 0x0100ul
+#define EV_SEVERITY_FAN_FAULT 0x0200ul
+
+#define EV_SEVERITY_TEMP_STABLE 0x0000ul
+#define EV_SEVERITY_TEMP_ADVISORY 0x0100ul
+#define EV_SEVERITY_TEMP_CRITICAL 0x0200ul
+#define EV_SEVERITY_TEMP_FAULT 0x0300ul
+
+void scdrv_event_init(struct sysctl_data_s *);
+
#endif /* _SN_SYSCTL_H_ */
diff --git a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h
index 123c1a5..f914f6d 100644
--- a/include/asm-ia64/sn/sn_sal.h
+++ b/include/asm-ia64/sn/sn_sal.h
@@ -64,6 +64,7 @@
#define SN_SAL_SYSCTL_IOBRICK_PCI_OP 0x02000042 // reentrant
#define SN_SAL_IROUTER_OP 0x02000043
+#define SN_SAL_SYSCTL_EVENT 0x02000044
#define SN_SAL_IOIF_INTERRUPT 0x0200004a
#define SN_SAL_HWPERF_OP 0x02000050 // lock
#define SN_SAL_IOIF_ERROR_INTERRUPT 0x02000051
@@ -850,6 +851,19 @@
return (int) rv.v0;
}
+/*
+ * Set up a node as the point of contact for system controller
+ * environmental event delivery.
+ */
+static inline int
+ia64_sn_sysctl_event_init(nasid_t nasid)
+{
+ struct ia64_sal_retval rv;
+ SAL_CALL_REENTRANT(rv, SN_SAL_SYSCTL_EVENT, (u64) nasid,
+ 0, 0, 0, 0, 0, 0);
+ return (int) rv.v0;
+}
+
/**
* ia64_sn_get_fit_compt - read a FIT entry from the PROM header
* @nasid: NASID of node to read
