commit 60189ddff03ffce1f0442a7591b2abafdf47e6a3
author Michael Chan <mchan@broadcom.com> Sun Dec 17 17:08:07 2006 -0800
committer David S. Miller <davem@sunset.davemloft.net> Sun Dec 17 21:59:22 2006 -0800
tree 25d3c5c8211fd57942ae0a57d82c66ad4b2110c5
parent c49a1561ee4b663d2819b5bea3e4684eae217b19

[TG3]: Power down/up 5906 PHY correctly.

The 5906 PHY requires a special register bit to power down and up the
PHY.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

drivers/net/tg3.c

diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 501ea6d..27c73b9 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -959,6 +959,13 @@
 	u32 phy_status;
 	int err;
 
+	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
+		u32 val;
+
+		val = tr32(GRC_MISC_CFG);
+		tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
+		udelay(40);
+	}
 	err  = tg3_readphy(tp, MII_BMSR, &phy_status);
 	err |= tg3_readphy(tp, MII_BMSR, &phy_status);
 	if (err != 0)
@@ -1170,7 +1177,15 @@
 	if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
 		return;
 
-	if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
+	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
+		u32 val;
+
+		tg3_bmcr_reset(tp);
+		val = tr32(GRC_MISC_CFG);
+		tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
+		udelay(40);
+		return;
+	} else {
 		tg3_writephy(tp, MII_TG3_EXT_CTRL,
 			     MII_TG3_EXT_CTRL_FORCE_LED_OFF);
 		tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);