pdc202xx_new: PLL detection fix
Fix a bitmask typo in the pdc202xx_new PLL frequency detection code
which causes it to truncate an intermediate difference to 26 bits
instead of the correct 30 bits (the PLL's bitwidth).
Signed-off-by: Mikael Pettersson <mikpe@it.uu.se>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
diff --git a/drivers/ide/pci/pdc202xx_new.c b/drivers/ide/pci/pdc202xx_new.c
index f74a02a..7b0e479 100644
--- a/drivers/ide/pci/pdc202xx_new.c
+++ b/drivers/ide/pci/pdc202xx_new.c
@@ -341,7 +341,7 @@
*/
usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
(end_time.tv_usec - start_time.tv_usec);
- pll_input = ((start_count - end_count) & 0x3ffffff) / 10 *
+ pll_input = ((start_count - end_count) & 0x3fffffff) / 10 *
(10000000 / usec_elapsed);
DBG("start[%ld] end[%ld]\n", start_count, end_count);
