tree ffcdb1fe79171bb0e6e02c0c197541d1b73ad5b0
parent 41c018b7ecb60b1c2c4d5dee0cd37d32a94c45af
author Russell King <rmk@dyn-67.arm.linux.org.uk> 1122579167 +0100
committer Russell King <rmk+kernel@arm.linux.org.uk> 1122579167 +0100

[ARM SMP] Ensure secondary CPUs have a clean TLB

Since ARMv6 CPUs will not flush the TLB on context switches, it is
possible that we may end up with some global TLB entries remaining
present, eventually upsetting userspace.  Explicitly flush the
entire TLB on secondary CPUs as they startup, after we have switched
to the init_mm page tables.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>