tree 9d05123c5b167ab8bb3b815e5becf537d54bfd92
parent 974edd30beafdb136cdfc6839a143e23c826dc89
author Mark Brown <broonie@opensource.wolfsonmicro.com> 1323520712 +0800
committer Mark Brown <broonie@opensource.wolfsonmicro.com> 1323543669 +0800

ASoC: Fix WM8996 24.576MHz clock operation

Record the clock after the divider as that is what all SYSCLK users see.
Without this the other clock configuration in the device comes out at
half rate.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: stable@kernel.org