tree 8cc17279410af8a36edd9c866ac2c7b98bb93ac2
parent 5335a639ecc5646cbe8e99086fb7e743b801ac58
author Viresh Kumar <viresh.kumar@st.com> 1334147663 +0530
committer Arnd Bergmann <arnd@arndb.de> 1336850367 +0200

SPEAr: clk: Add Fractional Synthesizer clock

All SPEAr SoC's contain Fractional Synthesizers. Their Fout is derived from
following equations:

Fout = Fin / (2 * div) (division factor)
div is 17 bits:-
     0-13 (fractional part)
     14-16 (integer part)
     div is (16-14 bits).(13-0 bits) (in binary)

     Fout = Fin/(2 * div)
     Fout = ((Fin / 10000)/(2 * div)) * 10000
     Fout = (2^14 * (Fin / 10000)/(2^14 * (2 * div))) * 10000
     Fout = (((Fin / 10000) << 14)/(2 * (div << 14))) * 10000

div << 14 is simply 17 bit value written at register.

This patch adds in support for this type of clock.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>