[MIPS] TRACE_IRQFLAGS_SUPPORT support.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h
index 13d44e1..e64abc0 100644
--- a/include/asm-mips/atomic.h
+++ b/include/asm-mips/atomic.h
@@ -22,8 +22,8 @@
#ifndef _ASM_ATOMIC_H
#define _ASM_ATOMIC_H
+#include <linux/irqflags.h>
#include <asm/cpu-features.h>
-#include <asm/interrupt.h>
#include <asm/war.h>
typedef struct { volatile int counter; } atomic_t;
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index 098cec2..1bb89c5 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -31,7 +31,7 @@
#ifdef __KERNEL__
-#include <asm/interrupt.h>
+#include <linux/irqflags.h>
#include <asm/sgidefs.h>
#include <asm/war.h>
diff --git a/include/asm-mips/interrupt.h b/include/asm-mips/irqflags.h
similarity index 80%
rename from include/asm-mips/interrupt.h
rename to include/asm-mips/irqflags.h
index a99d686..43ca09a 100644
--- a/include/asm-mips/interrupt.h
+++ b/include/asm-mips/irqflags.h
@@ -8,13 +8,15 @@
* Copyright (C) 1999 Silicon Graphics
* Copyright (C) 2000 MIPS Technologies, Inc.
*/
-#ifndef _ASM_INTERRUPT_H
-#define _ASM_INTERRUPT_H
+#ifndef _ASM_IRQFLAGS_H
+#define _ASM_IRQFLAGS_H
+
+#ifndef __ASSEMBLY__
#include <asm/hazards.h>
__asm__ (
- " .macro local_irq_enable \n"
+ " .macro raw_local_irq_enable \n"
" .set push \n"
" .set reorder \n"
" .set noat \n"
@@ -35,10 +37,10 @@
" .set pop \n"
" .endm");
-static inline void local_irq_enable(void)
+static inline void raw_local_irq_enable(void)
{
__asm__ __volatile__(
- "local_irq_enable"
+ "raw_local_irq_enable"
: /* no outputs */
: /* no inputs */
: "memory");
@@ -63,7 +65,7 @@
* Workaround: mask EXL bit of the result or place a nop before mfc0.
*/
__asm__ (
- " .macro local_irq_disable\n"
+ " .macro raw_local_irq_disable\n"
" .set push \n"
" .set noat \n"
#ifdef CONFIG_MIPS_MT_SMTC
@@ -84,17 +86,17 @@
" .set pop \n"
" .endm \n");
-static inline void local_irq_disable(void)
+static inline void raw_local_irq_disable(void)
{
__asm__ __volatile__(
- "local_irq_disable"
+ "raw_local_irq_disable"
: /* no outputs */
: /* no inputs */
: "memory");
}
__asm__ (
- " .macro local_save_flags flags \n"
+ " .macro raw_local_save_flags flags \n"
" .set push \n"
" .set reorder \n"
#ifdef CONFIG_MIPS_MT_SMTC
@@ -105,13 +107,13 @@
" .set pop \n"
" .endm \n");
-#define local_save_flags(x) \
+#define raw_local_save_flags(x) \
__asm__ __volatile__( \
- "local_save_flags %0" \
+ "raw_local_save_flags %0" \
: "=r" (x))
__asm__ (
- " .macro local_irq_save result \n"
+ " .macro raw_local_irq_save result \n"
" .set push \n"
" .set reorder \n"
" .set noat \n"
@@ -135,15 +137,15 @@
" .set pop \n"
" .endm \n");
-#define local_irq_save(x) \
+#define raw_local_irq_save(x) \
__asm__ __volatile__( \
- "local_irq_save\t%0" \
+ "raw_local_irq_save\t%0" \
: "=r" (x) \
: /* no inputs */ \
: "memory")
__asm__ (
- " .macro local_irq_restore flags \n"
+ " .macro raw_local_irq_restore flags \n"
" .set push \n"
" .set noreorder \n"
" .set noat \n"
@@ -182,40 +184,42 @@
" .set pop \n"
" .endm \n");
-#define local_irq_restore(flags) \
+#define raw_local_irq_restore(flags) \
do { \
unsigned long __tmp1; \
\
__asm__ __volatile__( \
- "local_irq_restore\t%0" \
+ "raw_local_irq_restore\t%0" \
: "=r" (__tmp1) \
: "0" (flags) \
: "memory"); \
} while(0)
-static inline int irqs_disabled(void)
+static inline int raw_irqs_disabled_flags(unsigned long flags)
{
#ifdef CONFIG_MIPS_MT_SMTC
/*
* SMTC model uses TCStatus.IXMT to disable interrupts for a thread/CPU
*/
- unsigned long __result;
-
- __asm__ __volatile__(
- " .set noreorder \n"
- " mfc0 %0, $2, 1 \n"
- " andi %0, 0x400 \n"
- " slt %0, $0, %0 \n"
- " .set reorder \n"
- : "=r" (__result));
-
- return __result;
+ return flags & 0x400;
#else
- unsigned long flags;
- local_save_flags(flags);
-
return !(flags & 1);
#endif
}
-#endif /* _ASM_INTERRUPT_H */
+#endif
+
+/*
+ * Do the CPU's IRQ-state tracing from assembly code.
+ */
+#ifdef CONFIG_TRACE_IRQFLAGS
+# define TRACE_IRQS_ON \
+ jal trace_hardirqs_on
+# define TRACE_IRQS_OFF \
+ jal trace_hardirqs_off
+#else
+# define TRACE_IRQS_ON
+# define TRACE_IRQS_OFF
+#endif
+
+#endif /* _ASM_IRQFLAGS_H */
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index b4169f0..6776688 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -1417,7 +1417,7 @@
#else /* SMTC versions that manage MT scheduling */
-#include <asm/interrupt.h>
+#include <linux/irqflags.h>
/*
* This is a duplicate of dmt() in mipsmtregs.h to avoid problems with
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
index 130333d..13c98dd 100644
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -13,13 +13,13 @@
#define _ASM_SYSTEM_H
#include <linux/types.h>
+#include <linux/irqflags.h>
#include <asm/addrspace.h>
#include <asm/cpu-features.h>
#include <asm/dsp.h>
#include <asm/ptrace.h>
#include <asm/war.h>
-#include <asm/interrupt.h>
/*
* read_barrier_depends - Flush all pending reads that subsequents reads
