tree 532191d0cef7cf975b70a07b1c69a293d6f552f7
parent 0803172778901e24a75ab074798d98c2b7411559
author Dan Williams <dan.j.williams@intel.com> 1252457584 -0700
committer Dan Williams <dan.j.williams@intel.com> 1252457584 -0700

ioat2,3: cacheline align software descriptor allocations

All the necessary fields for handling an ioat2,3 ring entry can fit into
one cacheline.  Move ->len prior to ->txd in struct ioat_ring_ent, and
move allocation of these entries to a hw-cache-aligned kmem cache to
reduce the number of cachelines dirtied for descriptor management.

Signed-off-by: Dan Williams <dan.j.williams@intel.com>