sh: hw-breakpoints: Add preliminary support for SH-4A UBC.
This adds preliminary support for the SH-4A UBC to the hw-breakpoints API.
Presently only a single channel is implemented, and the ptrace interface
still needs to be converted. This is the first step to cleaning up the
long-standing UBC mess, making the UBC more generally accessible, and
finally making it SMP safe.
An additional abstraction will be layered on top of this as with the perf
events code to permit the various CPU families to wire up support for
their own specific UBCs, as many variations exist.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
diff --git a/arch/sh/include/asm/processor_32.h b/arch/sh/include/asm/processor_32.h
index 9a87149..f4b5404 100644
--- a/arch/sh/include/asm/processor_32.h
+++ b/arch/sh/include/asm/processor_32.h
@@ -14,6 +14,7 @@
#include <asm/page.h>
#include <asm/types.h>
#include <asm/ptrace.h>
+#include <asm/ubc.h>
/*
* Default implementation of macro that returns current
@@ -99,8 +100,8 @@
unsigned long sp;
unsigned long pc;
- /* Hardware debugging registers */
- unsigned long ubc_pc;
+ /* Save middle states of ptrace breakpoints */
+ struct perf_event *ptrace_bps[NR_UBC_CHANNELS];
/* floating point info */
union sh_fpu_union fpu;
@@ -111,9 +112,6 @@
#endif
};
-/* Count of active tasks with UBC settings */
-extern int ubc_usercnt;
-
#define INIT_THREAD { \
.sp = sizeof(init_stack) + (long) &init_stack, \
}
