tree c8da161ad9f396773d05028b9e63e0faa62d701b
parent 568d9a8f6d4bf81e0672c74573dc02981d31e3ea
author Ma Ling <ling.ma@intel.com> 1237378403 +0800
committer Eric Anholt <eric@anholt.net> 1238190311 -0700

drm/i915: Use documented PLL timing limits for G4X platform

The values come from the internal reference spreadsheet on PLL
timing limits for the G4X chipsets.

Part of fixing fd.o bug #17508

Signed-off-by: Ma Ling <ling.ma@intel.com>
[anholt: Cleaned up some whitespace]
Signed-off-by: Eric Anholt <eric@anholt.net>